CN102969246A - Planar thyristor manufacturing method - Google Patents

Abstract

The invention provides a planar thyristor manufacturing method through which withstand voltage with more than 1000V and 1muA leakage current can be obtained. The method comprises the steps: through isolation, multilayer loop voltage division, deep base region diffusion, phosphorus diffusion emission region and stop ring and plane passivation technology. Due to adoption of plane manufacturing technology, the diameter of a wafer can be increased, the product fragment rate can be lowered, and the production efficiency can be improved by adopting automatic operation.

Description

A kind of plane controllable silicon manufacture method

Technical field

The present invention relates to a kind of plane controllable silicon manufacture method, be applied to the production of controllable silicon product.

Background technology

At present the controllable silicon production mainly adopts mesa technique, its structure as shown in Figure 1, technological process is as follows: carry out the oxidation masking layer growth at maximum 4 cun wafers, then do isolation to wearing diffusion, then carry out base, emitter region diffusion; After finishing, the emitter region need between front isolation and base, erode away more than the dark 50um of reaching; surpass the wide groove of 150um, hardened coating one deck glass cement in groove, and through high temperature sintering formation protective layer; finally finish aluminium lamination and back process, form 4 layers of PNPN structure controllable silicon.

Because need to corroding a degree of depth, mesa technique surpasses 50um even the dark groove of 100um, filling glass in the groove, and the wafer gross thickness generally is not more than 260um, and the thermal coefficient of expansion of glass is inconsistent in silicon, and therefore the wafer after the corrosion is very easy to fragmentation.Etching tank is negative bevel structure (see figure 2) for surperficial base (P), substrate (N), and surface field causes controllable silicon VDRM to be difficult to accomplish more than the 1000V greater than the body internal electric field; Isolation P district and the substrate N district groove formation orthogonal rake structure that is corroded, withstand voltage can reaching more than the 1000V so just is difficult to obtain the withstand voltage of symmetry.

Glass passivation process need to adopt manually or the electrophoresis coated glass, and this one deck material degree of purity is difficult to control, and the silicon controlled electric leakage obviously increases in the situation of introducing outside contamination; Controllable silicon often is operated under the adverse circumstances of high temperature, and the vicious circle that large leakage current causes the controllable silicon heating-increase-heating that heats up-leak electricity appears in meeting in high temperature environment.

Summary of the invention

The present invention relates to a kind of plane controllable silicon manufacture method; the present invention utilizes potential dividing ring, cut-off ring, plane passivation technology; the PN junction that P type base and N substrate form no longer adds glass passivation protection by fluting; and protected by the passivation layer on plane, help to solve the deficiency in the existing controllable silicon product processes process.

Technical program of the present invention lies in:

A kind of plane controllable silicon manufacture method is characterized in that: carries out as follows,

Step 1, choose suitable N-type silicon materials sheet, according to the withstand voltage demand of different product, select different resistivity; Thickness is chosen 200 ~ 260um according to the difference of wafer size;

Step 2, in the substrate slice thermal oxidation process, growth one deck 2.0um above oxide layer;

Step 3, carve the positive and negative isolation pattern with double face photoetching machine, and remove unwanted oxide layer with chemical corrosion liquid;

Step 4, in the isolation channel that erodes away deposition one deck p type impurity source, then carry out long-time High temperature diffusion more than 1250 ℃, final diffusion is finished the P type of positive and negative to wearing;

Step 5, in wafer frontside with photoetching, method for implanting, form P type potential dividing ring, the dividing potential drop structure of rings depends on different withstand voltage and die-size requirements, injection condition generally is 1% of base implantation dosage;

The method of step 6, usefulness photoetching, injection forms the positive and negative base region structure;

Step 7, process diffusion furnace High temperature diffusion form the dark base region structure in positive and negative, form simultaneously silicon dioxide layer protection PN junction;

Step 8, form the emitter region figure with the method for photoetching, wet etching, if note adopting dual surface lithography, form the emitter region at the positive and negative of wafer, can obtain bidirectional triode thyristor; If just form the emitter region in the front, then obtain one-way SCR;

Step 9, leave the controllable silicon K utmost point, the G utmost point in wafer frontside with photoetching, caustic solution, remove simultaneously back side oxide layer and form the A utmost point;

Step 10, positive deposition aluminium lamination;

Step 11, employing aluminium anti-carve method, remove positive aluminium lamination except the K utmost point, the G utmost point;

Step 12, positive PN junction structure with CVD mode deposit one deck passivation protection layer protection surface;

Step 13, backside deposition layer of metal finally form 4 layers of SCR structure of PNPN to form the A utmost point.

The invention has the advantages that: production of the present invention plane controllable silicon, can be on existing integrated circuit production line Production line, and needn't adjust any equipment, technique; Because fluting and the glass passivation process of cancellation, cancellation personnel's manual working can be used automation equipment production instead, enhances productivity the unsteadiness that the reduction personnel produce; The product of producing can obtain leakage current withstand voltage above 1000V and less than 1uA.

Description of drawings

Fig. 1 is the controllable silicon cross sectional representation of traditional mesa technique.

Fig. 2 is the controllable silicon glassivation schematic diagram of traditional mesa technique.

Fig. 3 is the controllable silicon cross-sectional view of planar technique provided by the invention.

Fig. 4 is potential dividing ring structure and the Electric Field Distribution schematic diagram of the embodiment of the invention.

Fig. 5 is the status architecture schematic diagram of embodiment of the invention step 4.

Fig. 6 is the status architecture schematic diagram of embodiment of the invention step 7.

Fig. 7 is the status architecture schematic diagram of embodiment of the invention step 13.

Fig. 8 is the present invention and traditional controllable silicon electric leakage comparison diagram.

Embodiment

For above-mentioned feature and advantage of the present invention can be become apparent, embodiment cited below particularly, and cooperation accompanying drawing are described in detail below.

The present invention relates to a kind of plane controllable silicon manufacture method, carry out as follows,

Step 1, choose suitable N-type silicon materials sheet, according to the withstand voltage demand of different product, select different resistivity; Thickness is chosen 200 ~ 260um according to the difference of wafer size.

Step 2, in the substrate slice thermal oxidation process, growth one deck 2.0um above oxide layer

Step 3, carve the positive and negative isolation pattern with double face photoetching machine, and remove unwanted oxide layer with chemical corrosion liquid.

Step 4, in the isolation channel that erodes away deposition one deck p type impurity source, then carry out long-time high temperature (more than 1250 ℃) diffusion, final diffusion is finished the P type of positive and negative to wearing.See Fig. 5

Step 5, in wafer frontside with photoetching, method for implanting, form P type potential dividing ring, the dividing potential drop structure of rings depends on different withstand voltage and die-size requirements.Injection condition generally is 1% of base implantation dosage.

The method of step 6, usefulness photoetching, injection forms the positive and negative base region structure.

Step 7, process diffusion furnace High temperature diffusion form the dark base region structure in positive and negative.Form simultaneously silicon dioxide layer protection PN junction.See Fig. 6.

The method of step 8, usefulness photoetching, wet etching forms the emitter region figure.If note adopting dual surface lithography, the positive and negative formation emitter region at wafer can obtain bidirectional triode thyristor; If just form the emitter region in the front, then obtain one-way SCR.

Step 9, leave the controllable silicon K utmost point, the G utmost point in wafer frontside with photoetching, caustic solution.Remove simultaneously back side oxide layer and form the A utmost point.

Step 10, positive deposition aluminium lamination.

Step 11, employing aluminium anti-carve method, remove positive aluminium lamination except the K utmost point, the G utmost point.

Step 12, positive PN junction structure with CVD mode deposit one deck passivation protection layer protection surface.

Step 13, backside deposition layer of metal finally form 4 layers of SCR structure of PNPN to form the A utmost point.See Fig. 7.

Its specific embodiment one is:

Step 1, choose suitable N-type silicon materials sheet, according to the withstand voltage demand of different product, select different resistivity; Thickness is chosen 220um according to the difference of wafer size; Also available 240um is as the data of choosing of embodiment two;

Step 2, in the substrate slice thermal oxidation process, growth one deck 3.0um oxide layer;

Step 3, carve the positive and negative isolation pattern with double face photoetching machine, and remove unwanted oxide layer with chemical corrosion liquid;

Step 4, in the isolation channel that erodes away deposition one deck p type impurity source, then carry out long-time about 1350 ℃ High temperature diffusion, final diffusion is finished the P type of positive and negative to wearing;

Step 5, in wafer frontside with photoetching, method for implanting, form P type potential dividing ring, the dividing potential drop structure of rings depends on different withstand voltage and die-size requirements, injection condition generally is 1% of base implantation dosage;

The method of step 6, usefulness photoetching, injection forms the positive and negative base region structure;

Step 7, process diffusion furnace High temperature diffusion form the dark base region structure in positive and negative, form simultaneously silicon dioxide layer protection PN junction;

Step 8, form the emitter region figure with the method for photoetching, wet etching, if note adopting dual surface lithography, form the emitter region at the positive and negative of wafer, can obtain bidirectional triode thyristor; If just form the emitter region in the front, then obtain one-way SCR;

Step 9, leave the controllable silicon K utmost point, the G utmost point in wafer frontside with photoetching, caustic solution, remove simultaneously back side oxide layer and form the A utmost point;

Step 10, positive deposition aluminium lamination;

Step 11, employing aluminium anti-carve method, remove positive aluminium lamination except the K utmost point, the G utmost point;

Step 12, positive PN junction structure with CVD mode deposit one deck passivation protection layer protection surface;

Step 13, backside deposition layer of metal finally form 4 layers of SCR structure of PNPN to form the A utmost point.

The present invention utilizes potential dividing ring, cut-off ring, plane passivation technology, and the PN junction that P type base and N substrate form no longer adds glass passivation protection by fluting, and is protected by the passivation layer on plane.Relatively and the table top grooving processes, main improvement has:

Adopt plane potential dividing ring, cut-off ring technique, chip surface was smooth after all technological processes were finished, and was convenient to large-scale production, with the identical (see figure 3) of existing semiconductor integrated technique.The potential dividing ring structure is seen Fig. 4.

Increase gradually when being added in the main voltage of tying, also gradually toward external expansion, the part voltage of increase will drop on the potential dividing ring depletion region of main knot, because potential dividing ring increases the radius of curvature of main knot depletion region significantly, therefore can improve withstand voltage.According to the simulation software simulation, can design different potential dividing ring structures and be easy to obtain different withstand voltage.

Adopt the grooving processes of cancelling after the planar technique, the chip surface consistency of thickness is not easy to deform, fragmentation.

Adopt silicon dioxide and other deactivation matters protection PN junction surface technology, eliminate the operation inconvenience of the glass passivation process of table top, can also reduce the PN junction leakage current.

Plane produced according to the invention controllable silicon, can be on existing integrated circuit production line Production line, and needn't adjust any equipment, technique; Because fluting and the glass passivation process of cancellation, cancellation personnel's manual working can be used automation equipment production instead, enhances productivity the unsteadiness that the reduction personnel produce.

On the other hand, according to preamble, the controllable silicon of table top grooving processes production is negative bevel for the PN junction that VDRM bears withstand voltage point, and surface field is too strong, so VDRM is difficult to reach more than the 1000V; The controllable silicon that the present invention produces does not destroy the PN junction face, and VDRM is withstand voltage to be born by potential dividing ring, according to the voltage request of different product, can design different structures.The withstand voltage difference of following table display plane structure and traditional mesa structure.

The plane controllable silicon that the present invention produces adopts silicon dioxide and other deactivation matters protection PN junction, and relatively and the glass protection of table top, the leakage current of product is obviously little than mesa technique.Experiment test is obvious especially in high temperature difference.The leakage current that Fig. 8 demonstrates under the different temperatures compares.

Above-mentioned only is preferred embodiment of the present invention, and all equalizations of doing according to the present patent application claim change and modify, and all should belong to covering scope of the present invention.

Claims (1)

1. plane controllable silicon manufacture method is characterized in that: carries out as follows,

Step 1, choose suitable N-type silicon materials sheet, according to the withstand voltage demand of different product, select different resistivity; Thickness is chosen 200 ~ 260um according to the difference of wafer size;

Step 2, in the substrate slice thermal oxidation process, growth one deck 2.0um above oxide layer;

Step 3, carve the positive and negative isolation pattern with double face photoetching machine, and remove unwanted oxide layer with chemical corrosion liquid;

Step 4, in the isolation channel that erodes away deposition one deck p type impurity source, then carry out long-time High temperature diffusion more than 1250 ℃, final diffusion is finished the P type of positive and negative to wearing;

Step 5, in wafer frontside with photoetching, method for implanting, form P type potential dividing ring, the dividing potential drop structure of rings depends on different withstand voltage and die-size requirements, injection condition generally is 1% of base implantation dosage;

The method of step 6, usefulness photoetching, injection forms the positive and negative base region structure;

Step 7, process diffusion furnace High temperature diffusion form the dark base region structure in positive and negative, form simultaneously silicon dioxide layer protection PN junction;

Step 8, form the emitter region figure with the method for photoetching, wet etching, if note adopting dual surface lithography, form the emitter region at the positive and negative of wafer, can obtain bidirectional triode thyristor; If just form the emitter region in the front, then obtain one-way SCR;

Step 9, leave the controllable silicon K utmost point, the G utmost point in wafer frontside with photoetching, caustic solution, remove simultaneously back side oxide layer and form the A utmost point;

Step 10, positive deposition aluminium lamination;

Step 11, employing aluminium anti-carve method, remove positive aluminium lamination except the K utmost point, the G utmost point;

Step 12, positive PN junction structure with CVD mode deposit one deck passivation protection layer protection surface;

Step 13, backside deposition layer of metal finally form 4 layers of SCR structure of PNPN to form the A utmost point.

Images