CN102969228A - Polycrystalline silicon resistor structure and manufacturing method thereof - Google Patents
Polycrystalline silicon resistor structure and manufacturing method thereof Download PDFInfo
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- CN102969228A CN102969228A CN2012105075768A CN201210507576A CN102969228A CN 102969228 A CN102969228 A CN 102969228A CN 2012105075768 A CN2012105075768 A CN 2012105075768A CN 201210507576 A CN201210507576 A CN 201210507576A CN 102969228 A CN102969228 A CN 102969228A
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Abstract
The invention provides a polycrystalline silicon resistor structure and a manufacturing method thereof. The manufacturing method of the polycrystalline silicon resistor structure comprises the following steps of: step 1, forming an isolation region in a silicon wafer; step 2, forming a first polycrystalline silicon layer and a side wall thereof on the isolation region; step 3, forming an isolation matter at the top of the first polycrystalline silicon layer, wherein the isolation matter does not cover the tops of the two ends of the first polycrystalline silicon layer; step 4, forming a second polycrystalline silicon layer on the isolation matter, wherein the second polycrystalline silicon layer does not cover the tops of the two ends of the first polycrystalline silicon layer; and step 5, carrying out ion injection by taking the second polycrystalline silicon layer as a mask so as to form metal silicides on the surfaces of the exposed two ends of the first polycrystalline silicon layer and not form the metal silicide on the surface of the unexposed part of the first polycrystalline silicon layer.
Description
Technical field
The present invention relates to field of semiconductor manufacture, more particularly, the present invention relates to a kind of polyresistor structure and manufacture method thereof.
Background technology
In the semiconductor circuit chip design, use polysilicon resistance that can be a large amount of.Traditional N-type or the P type polycrystalline resistor of the many employings of general circuit design personnel; but these resistance all need silicide barrier layer (salicide block layer in manufacture process; SAB) as an extra mask with for the protection of silicon chip surface; under its protection; silicon chip not with other Ti; the metal of Co and so on forms the metal silicide of not expecting, namely needs to increase by one lithography step.Specifically, the polysilicon that the polysilicon that N-type as polyresistor of the prior art is mixed or P type mix is by on logic polysilicon (itself being undoped), carry out N-type Implantation (the normally boron of high concentration (B) Implantation) or P type Implantation (the normally phosphorus of high concentration (P) Implantation) and form, they all need the silicide trapping layer as light shield.Yet the introducing of silicide trapping layer has increased the complexity of technique, and has increased manufacturing cost.
The storage polysilicon resistance that proposes in the improvement project of prior art does not need silicide barrier layer, has reduced manufacturing cost.But this polysilicon resistance is N-shaped resistance, and temperature coefficient is larger; This polysilicon is that doping content is higher in addition, so resistance value is less, is unfavorable for reducing circuit area.
Chinese patent application CN 102214560A has proposed a kind of scheme of utilizing storage polysilicon MPOL to form polyresistor, but the minimum widith of storage polysilicon MPOL can not be done very littlely, limited thus the resistance size of made polyresistor, when the polyresistor of the larger resistance of needs, need very long storage polysilicon strip to realize large resistance, therefore be unfavorable for saving chip area.
Therefore, hope can propose a kind of polyresistor surface that can prevent and form the simplification polyresistor structure fabrication scheme that metal silicide increases storage polysilicon resistance rate thus in the situation of not using silicide barrier layer.
Summary of the invention
Technical problem to be solved by this invention is for having defects in the prior art, providing a kind of polyresistor surface that can prevent in the situation of not using silicide barrier layer to form polyresistor structure making process and corresponding polyresistor structure that metal silicide increases the simplification of polysilicon resistance rate thus.
In order to realize above-mentioned technical purpose, according to a first aspect of the invention, provide a kind of polyresistor structure making process, it comprises: first step is used for forming isolated area at silicon chip; Second step is used for the sidewall at isolated area formation the first polysilicon layer and the first polysilicon layer; Third step is used for forming spacer at the top of the first polysilicon layer, and wherein spacer does not cover the top at the two ends of the first polysilicon layer; The 4th step is used for forming the second polysilicon layer at spacer, and wherein the second polysilicon layer does not cover the top at the two ends of the first polysilicon layer; The 5th step is used for carrying out take the second polysilicon layer as mask Implantation, in order to form metal silicide on the surface at the two ends of the exposure of the first polysilicon layer, and makes the surface of the unexposed part of the first polysilicon layer not form metal silicide.
Preferably, described the first polysilicon layer source electrode line polysilicon layer that is memory transistor cell; Its sidewall is to utilize the production stage of the sidewall structure that is used for isolation floating boom and source electrode line in the memory production process produced.
Preferably, described the second polysilicon layer is that processing step is positioned at and defines the layer that can be used to the barrier metal Formation of silicide of its shape by light shield after the first polysilicon layer.
Preferably, described the second polysilicon layer gate polysilicon layer that is the memory mos transistor unit.
Preferably, described the second polysilicon layer word line polysilicon layer that is memory.
Preferably, the Width of described resistor is deducted the width decision of both sides resistor sidewall by the overall width of the figure of definition floating boom light shield; The length direction of described resistor is determined by the length of the first polysilicon layer that does not come out in the metallization process process that the second polysilicon layer covers.
According to a second aspect of the invention, a kind of polyresistor structure is provided, has it is characterized in that comprising: the first polysilicon layer and sidewall, the spacer that forms at the top of the first polysilicon layer and the second polysilicon layer that forms at spacer that are arranged in isolated area in the silicon chip, form in isolated area; Wherein, spacer does not cover the top at the two ends of the first polysilicon layer, and the second polysilicon layer does not cover the top at the two ends of the first polysilicon layer; Wherein, the surface at the two ends of the exposure of the first polysilicon layer is formed with metal silicide, and makes the surface of the unexposed part of the first polysilicon layer not be formed with metal silicide.
Preferably, described the second polysilicon layer gate polysilicon layer that is the memory mos transistor unit or the word line polysilicon layer of memory.
Preferably, described the first polysilicon layer source electrode line polysilicon layer that is memory transistor cell.
Preferably, the Width of described resistor is deducted the width decision of both sides resistor sidewall by the overall width of the figure of definition floating boom light shield; The length direction of described resistor is determined by the length of the first polysilicon layer that does not come out in the metallization process process that the second polysilicon layer covers.
Thus, in the present invention, the second polysilicon layer has played protects the first following polysilicon layer not form the effect of metal silicide, has played thus the function identical with the silicide trapping layer; So the present invention advantageously by utilizing the second polysilicon layer as the mask of non-silicide structural, has avoided the use of silicide trapping layer.So that technique becomes simply, and reduced process costs, shortened the manufacturing cycle.And each step of the present invention can be incorporated in each step of memory circuitry manufacturing, need not to increase new step.In addition, compare with the scheme of utilizing storage polysilicon (word line polysilicon layer) to form polyresistor in the prior art, the minimum widith of the first polysilicon layer can be done little more much than the minimum widith of storage polysilicon, so be conducive to improve resistivity, saves device area.
Description of drawings
By reference to the accompanying drawings, and by with reference to following detailed description, will more easily to the present invention more complete understanding be arranged and more easily understand its advantage of following and feature, wherein:
Fig. 1 schematically shows the flow chart according to the polyresistor structure making process of first embodiment of the invention.
Fig. 2 schematically shows the regional location graph of a relation of overlooking according to the polyresistor structure of second embodiment of the invention.
Fig. 3 schematically shows the sectional view according to the polyresistor structure of second embodiment of the invention.
Need to prove that accompanying drawing is used for explanation the present invention, and unrestricted the present invention.Notice that the accompanying drawing of expression structure may not be to draw in proportion.And in the accompanying drawing, identical or similar element indicates identical or similar label.
Embodiment
In order to make content of the present invention more clear and understandable, below in conjunction with specific embodiments and the drawings content of the present invention is described in detail.
The＜the first embodiment 〉
Fig. 3 schematically shows the flow chart according to the polyresistor structure making process of first embodiment of the invention.Fig. 1 and Fig. 2 show corresponding polyresistor structure, and wherein Fig. 1 schematically shows the position relationship of subregion.
In conjunction with Fig. 1, Fig. 2 and shown in Figure 3, comprise according to the polyresistor structure making process of first embodiment of the invention:
First step S1: form isolated area 11 in silicon chip (out not shown), for example isolated area 11 is isolated areas of shallow channel isolation area or other type;
Second step S2: the sidewall 13 (media of the first polysilicon layer 2 both sides) that forms the first polysilicon layer 2 and the first polysilicon layer 2 in isolated area 11, preferably, described the first polysilicon layer 2 is to utilize the production stage of the polysilicon layer that is used for source electrode line in the memory production process produced; Wherein, the first polysilicon layer 2 has formed the active component of polyresistor structure.
Third step S3: spacer 12 is formed on the top at the first polysilicon layer 2, and wherein spacer 12 does not cover the top at the two ends of the first polysilicon layer 2;
The 4th step S4: form the second polysilicon layer 3 at spacer 12, wherein the second polysilicon layer 3 does not cover the top at the two ends of the first polysilicon layer 2; Second polysilicon layer 3 at end positions place that for example, can be by etching away the first polysilicon layer 2 is not so that the second polysilicon layer 3 covers the top at the two ends of the first polysilicon layer 2.
Preferably, the sidewall of the first polysilicon layer 2 is to utilize the production stage of the sidewall structure that is used for isolation floating boom and source electrode line in the memory production process produced.
Preferably, this second polysilicon layer 3 gate polysilicon layer that is the memory mos transistor unit or the word line polysilicon layer (memory poly, MPOL) of memory.
The 5th step S5: be used for carrying out Implantation take the second polysilicon layer 3 as mask, so that at the surface formation metal silicide at the two ends of the exposure of the first polysilicon layer 2, and make the surface of the unexposed part of the first polysilicon layer 2 not form metal silicide; Namely, because spacer 12 and the second polysilicon layer 3 do not cover the top at the two ends of the first polysilicon layer 2, the two ends of the first polysilicon layer 2 expose thus, thereby formed metal silicide on the zone at the two ends of the exposure of the first polysilicon layer 2, be connected 41 and 42 thereby be conducive to form therein with the contact of other function element.
As shown in Figure 2, the resistor of making thus is formed in the first polysilicon layer 2, and the Width of this resistor is deducted the width decision of both sides resistor sidewall by the overall width of the figure of definition floating boom light shield in the manufacture process; The length direction of described resistor is determined by the length of the first polysilicon layer that does not come out in the metallization process process that the second polysilicon layer covers.
So in fact, the second polysilicon layer 3 has played protects the first following polysilicon layer 2 not form the effect of metal silicide, has played thus the function identical with the silicide trapping layer; So the embodiment of the invention advantageously by utilizing the second polysilicon layer 3 as the mask of non-silicide structural, has been avoided the use of silicide trapping layer.So that technique becomes simply, and reduced process costs, shortened the manufacturing cycle.And above-mentioned steps can be incorporated in each step of memory circuitry manufacturing, need not to increase new step.In addition, compare with the scheme of utilizing word line polysilicon layer MPOL to form polyresistor in the prior art, the minimum widith of the first polysilicon layer can be done little more much than the minimum widith of word line polysilicon layer MPOL, so be conducive to improve resistivity, saves device area.
The＜the second embodiment 〉
Fig. 2 schematically shows the part schematic diagram of overlooking according to the polyresistor structure of second embodiment of the invention.Fig. 3 schematically shows the sectional view according to the polyresistor structure of second embodiment of the invention.Specifically, Fig. 3 is the sectional view along the line A-A intercepting of Fig. 2.
As shown in Figures 2 and 3, polyresistor structure according to second embodiment of the invention comprises: (for example be arranged in isolated area 11 in the silicon chip and sidewall 13 thereof, isolated area 11 is isolated areas of shallow channel isolation area or other type), the first polysilicon layer 2 that forms in isolated area 11 (preferably, described the first polysilicon layer 2 is to utilize the production stage of the polysilicon layer that is used for source electrode line in the memory production process produced), the spacer 12 (spacer 12 does not cover the top at the two ends of the first polysilicon layer 2) that forms at the top of the first polysilicon layer 2, the second polysilicon layer 3 (the second polysilicon layer 3 does not cover the top at the two ends of the first polysilicon layer 2) in spacer 12 formation.
Wherein, the surface at the two ends of the exposure of the first polysilicon layer 2 is formed with metal silicide, and makes the surface of the unexposed part of the first polysilicon layer 2 not be formed with metal silicide.
Preferably, this second polysilicon layer 3 gate polysilicon layer that is the memory mos transistor unit or the word line polysilicon layer of memory.
For the ease of understanding, the floating boom zone 5 of memory mos transistor unit has been shown among Fig. 1, can find out more easily thus the relative position situation of regional.
Determined by the width that the overall width of the figure of definition floating boom light shield deducts both sides resistor sidewall according to the Width of the resistor of the polyresistor structure of second embodiment of the invention; The length direction of described resistor is determined by the length of the first polysilicon layer that does not come out in the metallization process process that the second polysilicon layer covers.
In addition, need to prove, unless stated otherwise or point out, otherwise the term in the specification " first ", " second ", " the 3rd " etc. describe each assembly of only being used for distinguishing specification, element, step etc., rather than are used for logical relation between each assembly of expression, element, the step or ordinal relation etc.
Be understandable that although the present invention with the preferred embodiment disclosure as above, yet above-described embodiment is not to limit the present invention.For any those of ordinary skill in the art, do not breaking away from the technical solution of the present invention scope situation, all can utilize the technology contents of above-mentioned announcement that technical solution of the present invention is made many possible changes and modification, or be revised as the equivalent embodiment of equivalent variations.Therefore, every content that does not break away from technical solution of the present invention according to any simple modification, equivalent variations and the modification that technical spirit of the present invention is done above embodiment, all still belongs in the scope of technical solution of the present invention protection.
Claims (10)
1. polyresistor structure making process is characterized in that comprising:
First step is used for forming isolated area at silicon chip;
Second step is used for the sidewall at isolated area formation the first polysilicon layer and the first polysilicon layer;
Third step is used for forming spacer at the top of the first polysilicon layer, and wherein spacer does not cover the top at the two ends of the first polysilicon layer;
The 4th step is used for forming the second polysilicon layer at spacer, and wherein the second polysilicon layer does not cover the top at the two ends of the first polysilicon layer;
The 5th step is used for carrying out take the second polysilicon layer as mask Implantation, in order to form metal silicide on the surface at the two ends of the exposure of the first polysilicon layer, and makes the surface of the unexposed part of the first polysilicon layer not form metal silicide.
2. polyresistor structure making process according to claim 1 is characterized in that, the source electrode line polysilicon layer that described the first polysilicon layer is memory transistor cell; Its sidewall is to utilize the production stage of the sidewall structure that is used for isolation floating boom and source electrode line in the memory production process produced.
3. polyresistor structure making process according to claim 1 is characterized in that, described the second polysilicon layer is that processing step is positioned at and defines the layer that can be used to the barrier metal Formation of silicide of its shape by light shield after the first polysilicon layer.
4. polyresistor structure making process according to claim 1 and 2 is characterized in that, described the second polysilicon layer is the gate polysilicon layer of memory mos transistor unit.
5. polyresistor structure making process according to claim 1 and 2 is characterized in that, the word line polysilicon layer that described the second polysilicon layer is memory.
6. one of according to claim 1-5 described polyresistor structure making process is characterized in that, the Width of described resistor is determined by the width that the overall width of the figure of definition floating boom light shield deducts both sides resistor sidewall; The length direction of described resistor is determined by the length of the first polysilicon layer that does not come out in the metallization process process that the second polysilicon layer covers.
7. polyresistor structure is characterized in that comprising: the first polysilicon layer and sidewall, the spacer that forms at the top of the first polysilicon layer and the second polysilicon layer that forms at spacer that are arranged in isolated area in the silicon chip, form in isolated area;
Wherein, spacer does not cover the top at the two ends of the first polysilicon layer, and the second polysilicon layer does not cover the top at the two ends of the first polysilicon layer;
Wherein, the surface at the two ends of the exposure of the first polysilicon layer is formed with metal silicide, and makes the surface of the unexposed part of the first polysilicon layer not be formed with metal silicide.
8. polyresistor structure according to claim 7 is characterized in that, the word line polysilicon layer of the gate polysilicon layer that described the second polysilicon layer is the memory mos transistor unit or memory.
9. polyresistor structure according to claim 7 is characterized in that, the source electrode line polysilicon layer that described the first polysilicon layer is memory transistor cell.
10. one of according to claim 7-9 described polyresistor structure is characterized in that, the Width of described resistor is determined by the width that the overall width of the figure of definition floating boom light shield deducts both sides resistor sidewall; The length direction of described resistor is determined by the length of the first polysilicon layer that does not come out in the metallization process process that the second polysilicon layer covers.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201210507576.8A CN102969228B (en) | 2012-11-30 | 2012-11-30 | Polysilicon resistor structure and its manufacture method |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201210507576.8A CN102969228B (en) | 2012-11-30 | 2012-11-30 | Polysilicon resistor structure and its manufacture method |
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| CN102969228A true CN102969228A (en) | 2013-03-13 |
| CN102969228B CN102969228B (en) | 2017-09-19 |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112928209A (en) * | 2021-01-22 | 2021-06-08 | 上海华虹宏力半导体制造有限公司 | Preparation method of polysilicon resistor |
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| US20110204481A1 (en) * | 2010-02-24 | 2011-08-25 | Oki Semiconductor Co., Ltd. | Semiconductor device and semiconductor device fabrication |
| CN102214560A (en) * | 2011-05-27 | 2011-10-12 | 上海宏力半导体制造有限公司 | Resistor structure and manufacturing method thereof |
| CN102347281A (en) * | 2011-10-28 | 2012-02-08 | 上海宏力半导体制造有限公司 | Split-gate flash memory unit and forming method thereof |
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| CN1610015A (en) * | 2003-10-24 | 2005-04-27 | 上海宏力半导体制造有限公司 | Semiconductor resistance element and producing method thereof |
| US20090152679A1 (en) * | 2007-12-18 | 2009-06-18 | Seiko Instruments Inc. | Semiconductor device |
| US20100308436A1 (en) * | 2009-06-08 | 2010-12-09 | Panasonic Corporation | Semiconductor device and manufacturing method thereof |
| US20110204481A1 (en) * | 2010-02-24 | 2011-08-25 | Oki Semiconductor Co., Ltd. | Semiconductor device and semiconductor device fabrication |
| CN102214560A (en) * | 2011-05-27 | 2011-10-12 | 上海宏力半导体制造有限公司 | Resistor structure and manufacturing method thereof |
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| CN112928209A (en) * | 2021-01-22 | 2021-06-08 | 上海华虹宏力半导体制造有限公司 | Preparation method of polysilicon resistor |
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