CN104518024A - Metal oxide semiconductor component and manufacturing method thereof - Google Patents
Metal oxide semiconductor component and manufacturing method thereof Download PDFInfo
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- CN104518024A CN104518024A CN201310463948.6A CN201310463948A CN104518024A CN 104518024 A CN104518024 A CN 104518024A CN 201310463948 A CN201310463948 A CN 201310463948A CN 104518024 A CN104518024 A CN 104518024A
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 28
- 239000004065 semiconductor Substances 0.000 title claims abstract description 26
- 229910044991 metal oxide Inorganic materials 0.000 title claims abstract description 25
- 150000004706 metal oxides Chemical class 0.000 title claims abstract description 25
- 239000000758 substrate Substances 0.000 claims abstract description 47
- 238000000034 method Methods 0.000 claims description 30
- 239000012535 impurity Substances 0.000 claims description 15
- 238000005468 ion implantation Methods 0.000 claims description 10
- 239000007943 implant Substances 0.000 claims description 7
- 125000006850 spacer group Chemical group 0.000 abstract 2
- 230000003647 oxidation Effects 0.000 description 3
- 238000007254 oxidation reaction Methods 0.000 description 3
- 229920002120 photoresistant polymer Polymers 0.000 description 3
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 229910052796 boron Inorganic materials 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 238000005496 tempering Methods 0.000 description 2
- 230000003466 anti-cipated effect Effects 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 238000000609 electron-beam lithography Methods 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 230000000873 masking effect Effects 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000005036 potential barrier Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0843—Source or drain regions of field-effect devices
- H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
The invention provides an MOS (metal oxide semiconductor) component and a manufacturing method thereof. The MOS component is formed on a substrate having an upper surface and comprises an isolated area, a well area, a gate, a light-doped source, a light-doped drain, a source and a drain; the isolated area is used for defining an operating area; the gate comprises a dielectric layer, a stacking layer and a spacer layer; the stacking layer divides the operating area into a first side and a second side; the light-doped source of a first conductivity type is formed in the substrate below the upper surface of the first side, in top view, at least part of the light-doped source overlaps with the stacking layer; the source is of second conductivity type, and part of the source overlaps with the spacer layer close to the first side. The light-doped source and the source are of different conductivity types, thus the problem of threshold voltage roll-off is improved.
Description
Technical field
The present invention relates to a kind of metal-oxide semiconductor (MOS) (metal oxide semiconductor, MOS) element and manufacture method thereof; Refer to a kind of metal oxide semiconductor device and manufacture method thereof of the light dope source electrode utilizing conductivity type contrary with source electrode especially, to improve critical voltage downslide (threshold voltage roll-off) phenomenon of MOS element.
Background technology
Figure 1A and 1B shows cross-sectional schematic and the schematic top plan view of a kind of existing metal-oxide semiconductor (MOS) (metal oxidesemiconductor, MOS) element 100 respectively.As referring to figs. la and 1b, MOS element 100 is formed in substrate 11, comprises: wellblock 12, isolated district 13, grid 14, lightly doped drain 15, source electrode 16, with drain electrode 17.Wherein, isolated district 13 defining operation district 13a, active region main when operating as MOS element 100.Grid 14 comprise dielectric layer 14a, stack layer 14b, with wall 14c.The conductivity type of wellblock 12 is N-type, and lightly doped drain 15, source electrode 16 are P type with the conductivity type of drain electrode 17.Conductivity type is that the impurity of P type is generally boron (bororn) atom or the molecule containing boron.In substrate 11, the p type impurity of lightly doped drain 15, after hot processing procedure, can diffuse to below stack layer 14b; And source electrode 16 and the p type impurity in drain electrode 17 are after hot processing procedure, can diffuse to below wall 14c, anticipate as shown in Figure 1A.When MOS element 100 operates, because drain electrode causes potential barrier decline (drain inducedbarrier lowering, DIBL), and produce critical voltage downslide (threshold voltage roll-off) phenomenon, make the characteristic of MOS element 100 unstable, reduce the performance of element.
In view of this, the present invention, namely for the improvement of above-mentioned prior art, proposes a kind of MOS element and manufacture method thereof, can relax DIBL, improves critical voltage downslide (threshold voltage roll-off) phenomenon of MOS element.
Summary of the invention
The object of the invention is to overcome the deficiencies in the prior art and defect, a kind of metal oxide semiconductor device and manufacture method thereof are proposed, to relax DIBL, improve critical voltage downslide (threshold voltage roll-off) phenomenon of MOS element.
For reaching above-mentioned purpose, just wherein a viewpoint is sayed, the invention provides a kind of metal-oxide semiconductor (MOS) (metal oxide semiconductor, MOS) element, be formed in a substrate, this substrate has a upper surface, and this MOS element comprises: an isolated district, be formed on this upper surface, to define an operating space; One wellblock, has the first conductivity type, is formed in this substrate under this upper surface; One grid, is formed on this upper surface, looks it by vertical view, and this grid is arranged in this operating space, and this grid comprises: a dielectric layer, is formed on this upper surface, and is connected with this upper surface; One stack layer, is formed on this dielectric layer; And a wall, be formed on sidewall this upper surface outer of this stack layer; Wherein, this operating space is divided into the first side and the second side by this stack layer; One light dope source electrode, has the first conductivity type, is formed in this substrate under this upper surface of this first side, and looks it by vertical view, and this light dope source electrode is overlapping with this stack layer at least partly; One lightly doped drain, has the second conductivity type, is formed in this substrate under this upper surface of this second side; One source pole, has the second conductivity type, is formed in this substrate under this upper surface of this first side, and looks it by vertical view, and this source electrode of part is overlapping with this wall near this first side; And one drains, and has the second conductivity type, is formed in this substrate under this upper surface of this second side.
For reaching above-mentioned purpose, saying with regard to another viewpoint, the invention provides a kind of metal-oxide semiconductor (MOS) (metal oxide semiconductor, MOS) manufacturing method, comprise: a substrate is provided, and this substrate having a upper surface; Form an isolated district on this upper surface, to define an operating space; Formed in this substrate under this upper surface of a wellblock, there is the first conductivity type; Form a dielectric layer on this upper surface, and be connected with this upper surface; Form a pile to be stacked on this dielectric layer, and this operating space is divided into the first side and the second side by this stack layer; Formed in a light dope source electrode this substrate under this upper surface of this first side, and look it by vertical view, this light dope source electrode is overlapping with this stack layer at least partly, and wherein this lightly-doped source has the first conductivity type; Formed in a lightly doped drain this substrate under this upper surface of this second side, there is the second conductivity type; Form a wall on sidewall this upper surface outer of this stack layer; Formed in one source pole this substrate under this upper surface of this first side, have the second conductivity type, and look it by vertical view, this source electrode of part is overlapping with this wall near this first side; And formed in this substrate drained under this upper surface of this second side, there is the second conductivity type.
One is preferably implemented in kenel wherein, and this source electrode looks it by vertical view, connect with this stack layer or part this source electrode overlapping with this stack layer.
One is preferably implemented in kenel wherein, and this lightly doped drain looks it by vertical view, and this lightly doped drain is overlapping with this this wall near this second side at least partly.
One is preferably implemented in kenel wherein, and this drain electrode looks it by vertical view, connect with this this wall near this second side, connect with this stack layer or part this drain electrode overlapping with this stack layer.
One is preferably implemented in kenel wherein, and the forming step of this source electrode comprises: a self-aligned ion implantation manufacture process step, with this stack layer or this grid for shielding, and with ion implantation manufacture process, by the second conductive-type impurity, with the form of speeding-up ion, implant in this substrate; And a hot fabrication steps, to exceed the high temperature of 650 degree Celsius, tempering (anneal) process is carried out to this source electrode, to make this second conductive-type impurity, diffuse to below this wall of this first side.
Accompanying drawing explanation
Figure 1A-1B shows a kind of existing MOS element 100;
Fig. 2 A-2B shows first embodiment of the present invention;
Fig. 3,4,5 show respectively of the present invention second and third, four embodiments;
Fig. 6 illustrates to show and utilizes prior art and utilize the critical voltage (threshold voltage) of MOS element of the present invention and the indicatrix of conducting resistance (ON resistance);
Fig. 7 A-7J shows the 5th embodiment of the present invention.
Symbol description in figure
11,21 substrates
12,22 wellblocks
13,23 isolated districts
13a, 23a operating space
14,24 grids
14a, 24a dielectric layer
14b, 24b stack layer
14c, 24c wall
15,25b, 25c lightly doped drain
25a light dope source electrode
16,26 source electrodes
17,27 drain electrodes
21a upper surface
100,200,300,400,500 MOS elements
Embodiment
Fig. 2 A-2B shows first embodiment of the present invention.Fig. 2 A and 2B shows cross-sectional schematic according to metal-oxide semiconductor (MOS) of the present invention (metal oxide semiconductor, MOS) element 200 and schematic top plan view respectively.As shown in Fig. 2 A and 2B, MOS element 200 is formed in substrate 21, and substrate 21 has upper surface 21a (anticipating as indicated by the dashed line in fig. 2).MOS element 200 comprise wellblock 22, isolated district 23, grid 24, light dope source electrode 25a, lightly doped drain 25b, source electrode 26, with drain electrode 27.Grid 24 comprise dielectric layer 24a, stack layer 24b, with wall 24c.Wherein, substrate 21 is for example and without limitation to P-type silicon substrate, can also be other semiconductor substrate.Under wellblock 22 is formed at upper surface 21a.Isolated district 23 is formed on upper surface 21a, with defining operation district 23a.Operating space 23a is arranged in wellblock 22, active region main when operating as MOS element 200, and its scope is anticipated as shown in figs. 2 a and 2b.And the conductivity type of wellblock 22, light dope source electrode 25a, be for example and without limitation to P type; And under lightly doped drain 25b, source electrode 26 and drain electrode 27 be formed at upper surface 21a, its conductivity type is for example and without limitation to N-type.Grid 24 is formed on upper surface 21a, between source electrode 26 and drain electrode 27.Wherein, operating space 23a is divided into the first side and the second side by stack layer 24b, as arrow thick in Fig. 2 B illustrated.Dielectric layer 24a is formed on upper surface 21a, and is connected with upper surface 21a.Stack layer 24B is formed on this dielectric layer, comprises conductive material, and in order to the electrical contact as grid 24, the self-aligned that also can be used as when forming light dope source electrode 25a and lightly doped drain 25b shields.Wall 24c is formed on the outer upper surface 21a of sidewall of stack layer 24b, and the sidewall of coated stack layer 24b, comprises insulating material, and the self-aligned that also can be used as when forming source electrode 26 and drain electrode 27 shields.Light dope source electrode 25a is formed in the substrate 21 under the upper surface 21a of the first side, and looks it by vertical view 2B figure, and at least part of light dope source electrode 25a is overlapping with stack layer 24b, and such as, in the present embodiment, light dope source electrode 25a is completely overlapping with stack layer 24b.Lightly doped drain 25b is formed in the substrate 21 under the upper surface 21a of the second side.Source electrode 26 is formed in the substrate 21 under the upper surface 21a of the first side, and looks it by vertical view Fig. 2 B, and part source electrode 26 is overlapping with the wall 24c near the first side.Drain electrode 27 is formed in the substrate 21 under the upper surface 21a of the second side.Source electrode 27 looks it by vertical view (such as 2B schemes), is connected (as shown in Figure 2 B), part source electrode 27 can also be arranged overlapping with stack layer 24b such as but not limited to stack layer 24b.
The present invention and the main difference of prior art are, the conductivity type of light dope source electrode 25a is contrary with source electrode 26, to suppress the critical voltage downslide phenomenon produced because of DIBL.At the element of identical critical voltage, can the shorter element in selector channel according to the present invention, conducting resistance can be reduced, increase the speed of element operation.
Fig. 3 shows second embodiment of the present invention.Fig. 3 display is according to the schematic top plan view of MOS element 300 of the present invention.The present embodiment is intended to illustrate according to the present invention, and source electrode 26a looks it by vertical view Fig. 3, and part source electrode 26a is overlapping with stack layer 24b.
Fig. 4 shows the 3rd embodiment of the present invention.Fig. 4 display is according to the schematic top plan view of MOS element 400 of the present invention.As shown in Figure 4, in MOS element 400, lightly doped drain 25c looks it by vertical view Fig. 4, such as can be completely overlapping with the wall 24c near the second side, and the 27a that drains then can be connected with the wall 24c near the second side.
Fig. 5 shows the 4th embodiment of the present invention.Fig. 5 display is according to the schematic top plan view of MOS element 500 of the present invention.As shown in Figure 5, in MOS element 500, source electrode 26a looks it with drain electrode 27b by vertical view Fig. 5, and part source electrode 26a and the 27b that partly drains is all overlapping with stack layer 24b.
Fig. 6 illustrates to show and utilizes prior art and utilize the critical voltage (threshold voltage) of MOS element of the present invention and the indicatrix of conducting resistance (ON resistance).Wherein, the curve that connects for triangular nodes of the indicatrix of prior art MOS element; And according to the curve that the indicatrix of MOS element of the present invention connects for square node.First see critical voltage, the critical voltage of prior art MOS element has obvious critical voltage downslide phenomenon when passage length reduces, MOS element according to the present invention then significantly improves this kind of critical voltage downslide phenomenon.From conducting resistance, identical critical voltage element, according to the present invention, can select compared to the shorter MOS element of prior art passage length, its conducting resistance is lower, anticipates as shown in phantom in FIG..Therefore, according to the present invention, the size required for element is less, the speed of element operation, and this is all the present invention and is better than prior art part.
Fig. 7 A-7J shows the 5th embodiment of the present invention.The present embodiment illustrates the manufacture method of first embodiment MOS element 200 of the present invention.For convenience of description, in Fig. 7 A-7J, by a left side, right contrast shows schematic top plan view and the cross-sectional schematic of MOS element 200.As shown in figures 7 a and 7b, first provide such as but not limited to substrate 21, its have upper surface 21a (as dotted line in Fig. 7 B illustrated).Then, such as but not limited to forming isolated district 23 with oxidation process, it is such as shallow trench isolation (shallow trench isolation, STI) structure as shown in Figure 7 B, it can also be zone oxidation (local oxidation of silicon, LOCOS) structure.On upper surface 21a, form isolated district 23, anticipate as shown in figures 7 a and 7b with defining operation district 23a.
Then, as shown in Fig. 7 C and 7D, such as but not limited to forming photoresist layer with micro-photographing process for shielding (not shown), to define p type wells district 22, and with ion implantation manufacture process, by N-type impurity, with the form of speeding-up ion, as dotted line arrow in Fig. 7 D illustrated, implant in the region of definition, and form N-type wellblock 22 under upper surface 21a.
Then, as shown in Fig. 7 E and 7F, form dielectric layer 24 on upper surface 21a, and be connected with upper surface 21a; Form stack layer 24b again on dielectric layer 24, and operating space 23a is divided into the first side and the second side by stack layer 24b.Then, as shown in Fig. 7 G and 7H, such as but not limited to forming photoresist layer (not shown) and stack layer 24b for shielding with micro-photographing process respectively, define light dope source electrode 25a and lightly doped drain 25b respectively, and respectively with ion implantation manufacture process, respectively by N-type impurity and p type impurity, with the form of speeding-up ion, as dotted line arrow in Fig. 7 H illustrated, implant respectively in the region that defines in the first side and the second side, and form N-type light dope source electrode 25a and P type lightly doped drain 25b under upper surface 21a.Wherein, look it by vertical view Fig. 7 G, at least part of light dope source electrode 25a is overlapping with stack layer 24b.
Then, as shown in Fig. 7 I and 7J, wall 24c is formed on the outer upper surface 21a of sidewall of stack layer 24b.Then, photoresist layer (not shown) and grid 24 is formed for shield such as but not limited to micro-photographing process, definition source electrode 26 and drain electrode 27, and with ion implantation manufacture process, by p type impurity, with the form of speeding-up ion, as dotted line arrow in Fig. 7 J illustrated, implant in the region of definition, and form P type source electrode 26 with drain electrode 27 under upper surface 21a, wherein, grid 24 is between source electrode 26 and drain electrode 27.And source electrode 26 does not overlap each other each other with drain electrode 27, and look it by vertical view Fig. 7 I, part source electrode 26 is overlapping with the wall 24c near the first side.
It should be noted that, wherein forming the step of source electrode 26 such as but not limited to comprising: foregoing self-aligned ion implantation manufacture process step, is shielding with stack layer 24b or grid 24, and with ion implantation manufacture process, by p type impurity, with the form of speeding-up ion, implant in substrate 21; With very hot fabrication steps, to exceed the high temperature of 650 degree Celsius, tempering (anneal) process is carried out to source electrode 26, to make p type impurity, diffuse to below the wall 24c of the first side.
Below for preferred embodiment, the present invention is described, just the above, be only and make those skilled in the art be easy to understand content of the present invention, be not used for limiting interest field of the present invention.Under same spirit of the present invention, those skilled in the art can think and various equivalence change.Such as, not affecting under the main characteristic of element, other fabrication steps or structure can be added, as critical voltage adjustment district etc.; And for example, micro-shadow technology is not limited to masking techniques, also can comprise e-beam lithography; For another example, conductivity type P type and N-type can be exchanged, and only needing other region also to exchange pole accordingly can.Scope of the present invention should contain above-mentioned and other all equivalence change.
Claims (10)
1. a metal oxide semiconductor device, be formed in a substrate, this substrate has a upper surface, it is characterized in that, this metal oxide semiconductor device comprises:
One isolated district, is formed on this upper surface, to define an operating space;
One wellblock, has the first conductivity type, is formed in this substrate under this upper surface;
One grid, is formed on this upper surface, looks it by vertical view, and this grid is arranged in this operating space, and this grid comprises:
One dielectric layer, is formed on this upper surface, and is connected with this upper surface;
One stack layer, is formed on this dielectric layer; And
One wall, is formed on sidewall this upper surface outer of this stack layer;
Wherein, this operating space is divided into the first side and the second side by this stack layer;
One light dope source electrode, has the first conductivity type, is formed in this substrate under this upper surface of this first side, and looks it by vertical view, and this light dope source electrode is overlapping with this stack layer at least partly;
One lightly doped drain, has the second conductivity type, is formed in this substrate under this upper surface of this second side;
One source pole, has the second conductivity type, is formed in this substrate under this upper surface of this first side, and looks it by vertical view, and this source electrode of part is overlapping with this wall near this first side; And
One drain electrode, has the second conductivity type, is formed in this substrate under this upper surface of this second side.
2. metal oxide semiconductor device as claimed in claim 1, wherein, this source electrode looks it by vertical view, connects or partly this source electrode is overlapping with this stack layer with this stack layer.
3. metal oxide semiconductor device as claimed in claim 1, wherein, this lightly doped drain looks it by vertical view, and this lightly doped drain is overlapping with this this wall near this second side at least partly.
4. metal oxide semiconductor device as claimed in claim 1, wherein, this drain electrode looks it by vertical view, connects, to connect with this stack layer or partly this drain electrode is overlapping with this stack layer with this this wall near this second side.
5. metal oxide semiconductor device as claimed in claim 1, wherein, the forming step of this source electrode comprises:
One self-aligned ion implantation manufacture process step, with this stack layer or this grid for shielding, and with ion implantation manufacture process, by the second conductive-type impurity, with the form of speeding-up ion, implants in this substrate; And
One hot fabrication steps, to exceed the high temperature of 650 degree Celsius, carries out temper to this source electrode, to make this second conductive-type impurity, diffuses to below this wall of this first side.
6. a metal oxide semiconductor device manufacture method, is characterized in that, comprises:
There is provided a substrate, and this substrate has a upper surface;
Form an isolated district on this upper surface, to define an operating space;
Formed in this substrate under this upper surface of a wellblock, there is the first conductivity type;
Form a dielectric layer on this upper surface, and be connected with this upper surface;
Form a pile to be stacked on this dielectric layer, and this operating space is divided into the first side and the second side by this stack layer;
Formed in a light dope source electrode this substrate under this upper surface of this first side, and look it by vertical view, this light dope source electrode is overlapping with this stack layer at least partly, and wherein this lightly-doped source has the first conductivity type;
Formed in a lightly doped drain this substrate under this upper surface of this second side, there is the second conductivity type;
Form a wall on sidewall this upper surface outer of this stack layer;
Formed in one source pole this substrate under this upper surface of this first side, have the second conductivity type, and look it by vertical view, this source electrode of part is overlapping with this wall near this first side; And
Formed in this substrate drained under this upper surface of this second side, there is the second conductivity type.
7. metal oxide semiconductor device manufacture method as claimed in claim 6, wherein, this source electrode looks it by vertical view, connects or partly this source electrode is overlapping with this stack layer with this stack layer.
8. metal oxide semiconductor device manufacture method as claimed in claim 6, wherein, this lightly doped drain looks it by vertical view, and this lightly doped drain is overlapping with this this wall near this second side at least partly.
9. metal oxide semiconductor device manufacture method as claimed in claim 6, wherein, this drain electrode looks it by vertical view, connects, to connect with this stack layer or partly this drain electrode is overlapping with this stack layer with this this wall near this second side.
10. metal oxide semiconductor device manufacture method as claimed in claim 6, wherein, the step forming this source electrode comprises:
With this stack layer or this grid for shielding, and with ion implantation manufacture process, by the second conductive-type impurity, with the form of speeding-up ion, implant in this substrate; And
To exceed the high temperature of 650 degree Celsius, temper is carried out to this source electrode, to make this second conductive-type impurity, diffuse to below this wall of this first side.
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| CN110660852A (en) * | 2018-06-29 | 2020-01-07 | 立锜科技股份有限公司 | Metal oxide semiconductor element and manufacturing method thereof |
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| CN108074922A (en) * | 2016-11-14 | 2018-05-25 | 创王光电股份有限公司 | Semiconductor element |
| CN108074922B (en) * | 2016-11-14 | 2020-07-03 | 创王光电股份有限公司 | Semiconductor device with a plurality of semiconductor chips |
| CN110660852A (en) * | 2018-06-29 | 2020-01-07 | 立锜科技股份有限公司 | Metal oxide semiconductor element and manufacturing method thereof |
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