US20140124856A1 - Semiconductor device and fabricating method thereof - Google Patents
Semiconductor device and fabricating method thereof Download PDFInfo
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- US20140124856A1 US20140124856A1 US13/670,818 US201213670818A US2014124856A1 US 20140124856 A1 US20140124856 A1 US 20140124856A1 US 201213670818 A US201213670818 A US 201213670818A US 2014124856 A1 US2014124856 A1 US 2014124856A1
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 93
- 238000000034 method Methods 0.000 title claims abstract description 33
- 239000000758 substrate Substances 0.000 claims abstract description 55
- 210000000746 body region Anatomy 0.000 claims description 13
- 239000010410 layer Substances 0.000 description 50
- 238000009792 diffusion process Methods 0.000 description 5
- 238000005468 ion implantation Methods 0.000 description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 4
- 239000010703 silicon Substances 0.000 description 4
- 230000005669 field effect Effects 0.000 description 3
- 239000011229 interlayer Substances 0.000 description 3
- 238000002955 isolation Methods 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 239000012212 insulator Substances 0.000 description 2
- 238000001465 metallisation Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0843—Source or drain regions of field-effect devices
- H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/063—Reduced surface field [RESURF] pn-junction structures
- H01L29/0634—Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66659—Lateral single gate silicon transistors with asymmetry in the channel direction, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
- H01L29/7835—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1025—Channel region of field-effect devices
- H01L29/1029—Channel region of field-effect devices of field-effect transistors
- H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
- H01L29/1041—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with a non-uniform doping structure in the channel region surface
- H01L29/1045—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with a non-uniform doping structure in the channel region surface the doping structure being parallel to the channel length, e.g. DMOS like
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
- H01L29/42368—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity the thickness being non-uniform
Definitions
- the present invention relates to a semiconductor device, and in particular, to a semiconductor device having a super junction structure and a method for manufacturing the same.
- VDMOSFETs vertical double-diffused metal-oxide-semiconductor field effect transistors
- LDMOSFETs laterally diffused metal-oxide-semiconductor field effect transistors
- FIG. 1 is a cross section of a conventional n-type LDMOSFET.
- the n-type LDMOSFET 10 comprises a p-type semiconductor substrate 100 and a p-type epitaxial layer 102 thereon.
- a gate structure 116 and a field oxide layer 114 are on the p-type epitaxial layer 102 .
- a p-type body region 106 and an n-type drift region 104 are respectively in the p-type epitaxial layer 102 on both sides of the gate structure 116 , wherein the n-type drift region 104 further extends into the underlying p-type semiconductor substrate 100 .
- a p-type contact region 108 and an adjacent n-type contact region 110 are in the body region 106 and an n-type contact region 112 (or referred to as a drain region) is in the drift region 104 .
- a source electrode 117 is electrically connected to the p-type contact region 108 and the n-type contact region 110 .
- a drain electrode 119 is electrically connected to the n-type contact region 112 .
- a gate electrode 121 is electrically connected to the gate structure 116 .
- the doping concentration of the drift region 104 has to be reduced and/or the length of the field oxide layer 114 underlying the gate structure 116 has to be increased.
- the withstand voltage is increased by the described ways, the on-resistance (Ron) or the size of the transistor 10 is also increased.
- An exemplary embodiment of a semiconductor device includes a semiconductor substrate of a first conductivity type and an epitaxial structure of the first conductivity type disposed thereon.
- a well region of a second conductivity type is formed in the epitaxial structure and the semiconductor substrate.
- a drain region and a source region are respectively formed in the epitaxial structure inside and outside of the well region.
- At least one set of the first and second heavily doped regions is formed in the well region between the drain region and the source region, wherein the first and second heavily doped regions of the first and second conductivity types, respectively, are stacked vertically from bottom to top and have a doping concentration which is larger than that of the well region.
- a gate structure is disposed on the epitaxial structure.
- An exemplary embodiment of a method for fabricating a semiconductor device comprises providing a semiconductor substrate of a first conductivity type.
- An epitaxial structure of the first conductivity type is formed on the semiconductor substrate.
- a well region of a second conductivity type is formed in the epitaxial structure and the semiconductor substrate.
- At least one set of the first and second heavily doped regions is formed in the well region, wherein the first and second heavily doped regions of the first and second conductivity types, respectively, are stacked vertically from bottom to top and have a doping concentration which is larger than that of the well region.
- a drain region and a source region are respectively formed in the epitaxial structure inside and outside of the well region, such that the set of the first and second heavily doped regions is in the well region between the drain region and the source region.
- a gate structure is formed on the epitaxial structure.
- FIG. 1 is a cross section of a conventional n-type LDMOSFET.
- FIGS. 2A to 2D are cross sections of an exemplary embodiment of a method for fabricating a semiconductor device according to the invention.
- FIGS. 3A to 3B are cross sections of another exemplary embodiment of a method for fabricating a semiconductor device according to the invention.
- FIG. 2D illustrates a cross section of an exemplary embodiment of a semiconductor device 20 according to the invention.
- the semiconductor device 20 may be a laterally diffused metal-oxide-semiconductor field effect transistor (LDMOSFET) having super junction structures.
- the semiconductor device 20 comprises a semiconductor substrate 200 , such as, a silicon substrate, silicon on insulator (SOI) substrate or other suitable semiconductor substrate, of a first conductivity type.
- SOI silicon on insulator
- An epitaxial structure 210 of the first conductivity type is formed on the semiconductor substrate 200 .
- the epitaxial structure 210 is composed of a single epitaxial layer.
- a well region 204 , a source region 218 , a drain region 220 and a body region 212 are formed in the epitaxial structure 210 .
- the well region 204 of a second conductivity type opposite to the first conductivity type extends into the semiconductor substrate 200 from the epitaxial structure 210 , such that the well region 204 is formed in the epitaxial structure 210 and the semiconductor substrate 200 .
- the well region 204 corresponds to an active region A (which is defined by a portion of the isolation structure, such as the field oxide layer 214 ) of the semiconductor substrate 200 to serve as a drift region of the LDMOSFET.
- the source region 218 comprises a doped region 218 a of the second conductivity type and a doped region 218 b of the first conductivity type.
- the source region 218 is formed in the epitaxial structure 210 outside of the well region 204 , such as an epitaxial layer 202 , and corresponds to the active region A.
- the body region 212 of the first conductivity type is formed in the epitaxial structure 210 outside of the well region 204 , such that the source region 218 is in the body region 212 .
- the drain region 220 is formed of the doped region of the second conductivity type only.
- the drain region 220 is formed in the well region 204 of the epitaxial structure 210 and corresponds to the active region A.
- At least one set of the first heavily doped region 201 and second heavily doped region 203 is formed in the well region 204 between the drain region 220 and the source region 218 , wherein the first heavily doped region 201 and the second heavily doped region 203 are stacked vertically from bottom to top and the first heavily doped region 201 is electrically floating.
- the first and second heavily doped regions 201 and 203 are respectively of the first and second conductivity types and have a doping concentration which is larger than that of the well region 204 to form a super junction structure in the well region 204 of the epitaxial structure 210 .
- the first conductivity type is p-type and the second conductivity type is n-type.
- the first conductivity type is n-type and the second conductivity type is p-type.
- At least one set of the first and second heavily doped regions 201 and 203 may be formed in the well region 204 of the epitaxial layer 202 (i.e., the epitaxial structure 210 ) and/or the semiconductor substrate 200 .
- the semiconductor device 20 may comprise two sets of first and second heavily doped regions 201 and 203 respectively formed in the well region 204 corresponding to the epitaxial layer 202 and corresponding to the semiconductor substrate 200 . As shown in FIG. 2D , such two sets of first and second heavily doped regions 201 and 203 substantially align to each other vertically and two super junction structures are formed in the epitaxial layer 202 and the semiconductor substrate 200 .
- a gate structure 216 is disposed on the epitaxial structure 210 and between the source region 218 and the drain region 220 .
- the gate structure 216 typically comprises a gate (e.g., a polysilicon gate), a gate dielectric layer underlying the gate and a field oxide layer 214 underlying the gate dielectric layer.
- the semiconductor device 20 further comprises an interlayer dielectric (ILD) layer 226 and a plurality of interconnect structures 221 , 223 and 225 therein.
- ILD interlayer dielectric
- the interconnect structure 221 is electrically connected to the source region 218 to serve as a source electrode
- the interconnect structure 223 is electrically connected to the gate structure 216 to serve as a gate electrode
- the interconnect structure 225 is electrically connected to the drain region 220 to serve as a drain electrode.
- FIG. 3B a cross section of another exemplary embodiment of a semiconductor device 30 according to the invention is shown. Elements in FIG. 3B that are the same as those in FIG. 2D are labeled with the same reference numbers as in FIG. 2D and are not described again for brevity.
- the structure of the semiconductor device 30 is similar to that of the semiconductor device 20 (as shown in FIG. 2D ). The difference is that the epitaxial structure 210 in the semiconductor device 30 comprises a plurality of vertically stacked epitaxial layers 202 . It is realized that the number of epitaxial layers 202 used is determined by the design demands and is not limited to the embodiment in FIG. 3B (i.e., the epitaxial layers 202 may be more than three layers).
- the well region 204 extends into the underlying semiconductor substrate 200 from the epitaxial structure 210 .
- the source region 218 , the drain region 220 and the body region 212 are formed in the uppermost epitaxial layer 202 of the epitaxial structure 210 .
- the semiconductor device 30 comprises at least one set of the first and second heavily doped regions 201 and 203 formed in the well region 204 corresponding to the semiconductor substrate 200 or in the well region 204 corresponding to one of the epitaxial layers 202 . In another embodiment, the semiconductor device 30 comprises a plurality of sets of first and second heavily doped regions 201 and 203 formed in the well region 204 corresponding to each epitaxial layer 202 and the semiconductor substrate 200 .
- the number of sets of first and second heavily doped regions 201 and 203 may be less than or equal to the number of epitaxial layers 202 , such that none of the first and second heavily doped regions 201 and 203 is in the well region 204 corresponding to some of the epitaxial layers 202 and/or the semiconductor substrate 200 .
- the heavily doped region of the first conductivity type and electrically floating in the super junction structure may help in the formation of a depletion region in the well region 204 (i.e., the drift region) thereby improving the withstand voltage of the LDMOSFET in the semiconductor device 20 or 30 .
- the heavily doped region of the second conductivity type in the super junction structure may provide an additional current path in the well region 204 (i.e., the drift region) to reduce the on-resistance between the source region and the drain region.
- FIGS. 2A to 2D are cross sections of an exemplary embodiment of a method for fabricating a semiconductor device 20 according to the invention.
- a semiconductor substrate 200 such as a silicon substrate, a silicon on insulator (SOI) substrate or other suitable semiconductor substrates, of a first conductivity type is provided.
- a well region 204 is formed in a predetermined region (i.e., an active region A) of the semiconductor substrate 200 sequentially by a doping process (e.g., ion implantation), and a thermal diffusion process.
- a doping process e.g., ion implantation
- an epitaxial structure 210 of the first conductivity type is formed on the semiconductor substrate 200 .
- the epitaxial structure 210 is composed of a single layer.
- the epitaxial structure 210 is composed of an epitaxial layer 202 .
- the doping process e.g., ion implantation
- the thermal diffusion process are sequentially performed in the epitaxial structure 210 corresponding to the active region A, such that the well region 204 in the semiconductor substrate 200 extends into the epitaxial structure 210 , wherein the well region 204 of a second conductivity type different from the first conductivity type is configured to serve as a drift region of a subsequently formed LDMOSFET.
- the well region 204 may be formed by other fabricating methods.
- U.S. Pat. No. 7,682,955 disclosing a method for forming a deep well of a power device, is incorporated herein as reference.
- At least one set of the first and second heavily doped regions 201 and 203 is formed in the well region 204 , wherein the first and second heavily doped regions 201 and 203 are stacked vertically from bottom to top.
- the first and second heavily doped regions 201 and 203 are respectively of the first and second conductivity types and have a doping concentration which is larger than that of the well region 204 to form a super junction structure in the well region 204 of the epitaxial structure 210 .
- one set of the first and second heavily doped regions 201 and 203 is formed in the well region 204 of the epitaxial layer 202 by a doping process, such as ion implantation.
- one set of the first and second heavily doped regions 201 and 203 is formed in the well region 204 of the semiconductor substrate 200 before forming the epitaxial layer 202 .
- one set of the first and second heavily doped regions 201 and 203 is formed in the well region 204 of the semiconductor substrate 200 before forming the epitaxial layer 202 .
- another set of the first and second heavily doped regions 201 and 203 is formed in the well region 204 of the epitaxial layer 202 after forming the epitaxial layer 202 and a well region 204 therein, as shown in FIG. 2A .
- These two sets of first and second heavily doped regions 201 and 203 substantially and vertically align to each other to form two super junction structures in the epitaxial layer 202 and the semiconductor substrate 200 .
- the first and second heavily doped regions 201 and 203 are between a drain region 220 and a source region 218 (as shown in FIG. 2C ) that are subsequently formed, wherein the first heavily doped region 201 is electrically floating.
- the first conductivity type is p-type and the second conductivity type is n-type.
- the first conductivity type is n-type and the second conductivity type is p-type.
- a plurality of isolation structures such as a field oxide layer 214 may be formed on the epitaxial structure 210 by the conventional MOS process, wherein the active region A is defined by a portion of the field oxide layer 214 and a drain region D to be formed in the well region 204 is defined by the rest of the field oxide layer 214 .
- a gate structure 216 is formed on the epitaxial structure 210 to define a source region S to be formed in the active region A outside of the well region 204 , as shown in FIG. 2B .
- a body region 212 of the first conductivity type is optionally formed in the epitaxial structure 210 outside of the well region 204 sequentially by a doping process (e.g., ion implantation), and a thermal diffusion process, such that the subsequently formed source region 218 is in the body region 212 .
- a doped region 218 a of the second conductivity type is then formed in the source region S to be formed (as shown in FIG. 2 B) and another doped region (i.e., the drain region 220 ) of the second conductivity type is formed in the drain region D to be formed (as shown in FIG. 2B ) by a doping process (e.g., ion implantation).
- a doped region 218 b of the first conductivity type is formed in the source region S to be formed (as shown in FIG. 2B ) and adjacent to the doped region 218 a, such that the doped region 218 b and the doped region 218 a form a source region 218 , as shown in FIG. 2C .
- the doped region 218 b may be formed before forming the doped region 218 a and the drain region 220 .
- the doped region 218 , the gate structure 216 , the drain region 220 and the well region 204 having the super junction structures form an LDMOSFET.
- an interlayer dielectric layer 226 and a plurality of interconnect structures 221 , 223 and 225 therein are formed on an epitaxial layer 202 by the conventional metallization process.
- the interconnect structure 221 is electrically connected to the source region 218 to serve as a source electrode
- the interconnect structure 223 is electrically connected to the gate structure 216 to serve as a gate electrode
- the interconnect structure 225 is electrically connected to the drain region 220 to serve as a drain electrode.
- FIGS. 3A to 3B are cross sections of another exemplary embodiment of a method for fabricating a semiconductor device 30 according to the invention. Elements in FIGS. 3A to 3B that are the same as those in FIGS. 2A to 2D are labeled with the same reference numbers as in FIGS. 2A to 2D and are not described again for brevity.
- a semiconductor substrate 200 is provided.
- a well region 204 is formed in an active region A of the semiconductor substrate 200 sequentially by a doping process and a thermal diffusion process.
- an epitaxial structure 210 of the first conductivity type is formed on the semiconductor substrate 200 .
- the epitaxial structure 210 comprises multiple layers.
- the epitaxial structure 210 comprises a plurality of epitaxial layers 202 stacked vertically.
- the plurality of epitaxial layers 202 may be formed by an epitaxial growth process. It is noted that before forming the next epitaxial layer 202 , a doping process and a thermal diffusion process are performed in the former epitaxial layer 202 , such that the well region 204 in the semiconductor substrate 200 extends into the epitaxial structure 210 to serve as a drift region of the LDMOSFET subsequently formed.
- At least one set of the first and second heavily doped regions 201 and 203 is formed in the well region 204 .
- one set of the first and second heavily doped regions 201 and 203 is formed in the well region 204 of the corresponding epitaxial layer 202 .
- one set of the first and second heavily doped regions 201 and 203 may be formed in the well region 204 corresponding to the semiconductor substrate 200 before forming the epitaxial structure 210 .
- one set of the first and second heavily doped regions 201 and 203 may be formed in the well region 204 corresponding to the semiconductor substrate 200 before forming the epitaxial structure 210 .
- another set of the first and second heavily doped regions 201 and 203 may be formed in the corresponding well region 204 of each epitaxial layer 202 , after forming each epitaxial layer 202 and the corresponding well region 204 therein, as shown in FIG. 3A .
- the plurality of sets of first and second heavily doped regions 201 and 203 substantially align to each other vertically and a plurality of super junction structures are formed in the epitaxial structure 210 and the semiconductor substrate 200 .
- a field oxide layer 214 and a gate structure 216 may be formed on the epitaxial structure 210 and a body region 212 , a source region 218 and a drain region 220 may be formed on the uppermost epitaxial layer 202 by the conventional MOS process.
- an interlayer dielectric (ILD) layer 226 and a plurality of interconnect structures 221 , 223 and 225 therein may be formed on the epitaxial structure 210 by the conventional metallization process.
- ILD interlayer dielectric
- the heavily doped region of the first conductivity type and electrically floating in the super junction structure may form a depletion region in the drift region, so that the withstand voltage of the LDMOSFET in the semiconductor device is improved.
- the heavily doped region of the second conductivity type in the super junction structure may provide an additional current path in the drift region, so that the on-resistance of the LDMOSFET is reduced.
- the number of super junction structures stacked vertically in the drift region may be controlled to further improve the withstand voltage of the LDMOSFET while preventing the on-resistance of the LDMOSFET from increasing.
Abstract
Description
- 1. Field of the Invention
- The present invention relates to a semiconductor device, and in particular, to a semiconductor device having a super junction structure and a method for manufacturing the same.
- 2. Description of the Related Art
- Semiconductor devices, such as high voltage elements, are typically divided into: vertical double-diffused metal-oxide-semiconductor field effect transistors (VDMOSFETs) and laterally diffused metal-oxide-semiconductor field effect transistors (LDMOSFETs). In order to increase the withstand voltage of the described high voltage elements, the doping concentration of the deep well region (or referred to as the drift region) is reduced, the depth of the drift region is increased, or the length of the isolation structure (or referred to as the field oxide layer) underlying the gate is increased.
-
FIG. 1 is a cross section of a conventional n-type LDMOSFET. The n-type LDMOSFET 10 comprises a p-type semiconductor substrate 100 and a p-typeepitaxial layer 102 thereon. Agate structure 116 and afield oxide layer 114 are on the p-typeepitaxial layer 102. Moreover, a p-type body region 106 and an n-type drift region 104 are respectively in the p-typeepitaxial layer 102 on both sides of thegate structure 116, wherein the n-type drift region 104 further extends into the underlying p-type semiconductor substrate 100. A p-type contact region 108 and an adjacent n-type contact region 110 (or both referred to as a source region) are in thebody region 106 and an n-type contact region 112 (or referred to as a drain region) is in thedrift region 104. Moreover, asource electrode 117 is electrically connected to the p-type contact region 108 and the n-type contact region 110. Adrain electrode 119 is electrically connected to the n-type contact region 112. Agate electrode 121 is electrically connected to thegate structure 116. - As mentioned above, in order to improve the withstand voltage of the
transistor 10, the doping concentration of thedrift region 104 has to be reduced and/or the length of thefield oxide layer 114 underlying thegate structure 116 has to be increased. However, when the withstand voltage is increased by the described ways, the on-resistance (Ron) or the size of thetransistor 10 is also increased. - Thus, there exists a need in the art for development of a semiconductor device, capable of increasing the withstand voltage while preventing the on-resistance from increasing.
- A detailed description is given in the following embodiments with reference to the accompanying drawings. Semiconductor devices and methods for fabricating the same are provided.
- An exemplary embodiment of a semiconductor device includes a semiconductor substrate of a first conductivity type and an epitaxial structure of the first conductivity type disposed thereon. A well region of a second conductivity type is formed in the epitaxial structure and the semiconductor substrate. A drain region and a source region are respectively formed in the epitaxial structure inside and outside of the well region. At least one set of the first and second heavily doped regions is formed in the well region between the drain region and the source region, wherein the first and second heavily doped regions of the first and second conductivity types, respectively, are stacked vertically from bottom to top and have a doping concentration which is larger than that of the well region. A gate structure is disposed on the epitaxial structure.
- An exemplary embodiment of a method for fabricating a semiconductor device comprises providing a semiconductor substrate of a first conductivity type. An epitaxial structure of the first conductivity type is formed on the semiconductor substrate. A well region of a second conductivity type is formed in the epitaxial structure and the semiconductor substrate. At least one set of the first and second heavily doped regions is formed in the well region, wherein the first and second heavily doped regions of the first and second conductivity types, respectively, are stacked vertically from bottom to top and have a doping concentration which is larger than that of the well region. A drain region and a source region are respectively formed in the epitaxial structure inside and outside of the well region, such that the set of the first and second heavily doped regions is in the well region between the drain region and the source region. A gate structure is formed on the epitaxial structure.
- A detailed description is given in the following embodiments with reference to the accompanying drawings.
- The invention can be more fully understood by reading the subsequent detailed description and examples with references made to the accompanying drawings, wherein:
-
FIG. 1 is a cross section of a conventional n-type LDMOSFET. -
FIGS. 2A to 2D are cross sections of an exemplary embodiment of a method for fabricating a semiconductor device according to the invention. -
FIGS. 3A to 3B are cross sections of another exemplary embodiment of a method for fabricating a semiconductor device according to the invention. - The following description is of a mode for carrying out the invention. This description is made for the purpose of illustrating the general principles of the invention and should not be taken in a limiting sense. The scope of the invention is best determined by reference to the appended claims.
-
FIG. 2D illustrates a cross section of an exemplary embodiment of asemiconductor device 20 according to the invention. In the embodiment, thesemiconductor device 20 may be a laterally diffused metal-oxide-semiconductor field effect transistor (LDMOSFET) having super junction structures. Moreover, thesemiconductor device 20 comprises asemiconductor substrate 200, such as, a silicon substrate, silicon on insulator (SOI) substrate or other suitable semiconductor substrate, of a first conductivity type. - An
epitaxial structure 210 of the first conductivity type is formed on thesemiconductor substrate 200. In the embodiment, theepitaxial structure 210 is composed of a single epitaxial layer. Awell region 204, asource region 218, adrain region 220 and abody region 212 are formed in theepitaxial structure 210. For example, thewell region 204 of a second conductivity type opposite to the first conductivity type extends into thesemiconductor substrate 200 from theepitaxial structure 210, such that thewell region 204 is formed in theepitaxial structure 210 and thesemiconductor substrate 200. Moreover, thewell region 204 corresponds to an active region A (which is defined by a portion of the isolation structure, such as the field oxide layer 214) of thesemiconductor substrate 200 to serve as a drift region of the LDMOSFET. - The
source region 218 comprises adoped region 218 a of the second conductivity type and adoped region 218 b of the first conductivity type. Thesource region 218 is formed in theepitaxial structure 210 outside of thewell region 204, such as anepitaxial layer 202, and corresponds to the active region A. Moreover, thebody region 212 of the first conductivity type is formed in theepitaxial structure 210 outside of thewell region 204, such that thesource region 218 is in thebody region 212. Thedrain region 220 is formed of the doped region of the second conductivity type only. Thedrain region 220 is formed in thewell region 204 of theepitaxial structure 210 and corresponds to the active region A. - At least one set of the first heavily doped
region 201 and second heavily dopedregion 203 is formed in thewell region 204 between thedrain region 220 and thesource region 218, wherein the first heavily dopedregion 201 and the second heavily dopedregion 203 are stacked vertically from bottom to top and the first heavily dopedregion 201 is electrically floating. The first and second heavily dopedregions well region 204 to form a super junction structure in thewell region 204 of theepitaxial structure 210. In the embodiment, the first conductivity type is p-type and the second conductivity type is n-type. Alternatively, the first conductivity type is n-type and the second conductivity type is p-type. - In the embodiment, at least one set of the first and second heavily doped
regions well region 204 of the epitaxial layer 202 (i.e., the epitaxial structure 210) and/or thesemiconductor substrate 200. For example, thesemiconductor device 20 may comprise two sets of first and second heavily dopedregions well region 204 corresponding to theepitaxial layer 202 and corresponding to thesemiconductor substrate 200. As shown inFIG. 2D , such two sets of first and second heavily dopedregions epitaxial layer 202 and thesemiconductor substrate 200. - A
gate structure 216 is disposed on theepitaxial structure 210 and between thesource region 218 and thedrain region 220. Thegate structure 216 typically comprises a gate (e.g., a polysilicon gate), a gate dielectric layer underlying the gate and afield oxide layer 214 underlying the gate dielectric layer. - The
semiconductor device 20 further comprises an interlayer dielectric (ILD)layer 226 and a plurality ofinterconnect structures interconnect structure 221 is electrically connected to thesource region 218 to serve as a source electrode, theinterconnect structure 223 is electrically connected to thegate structure 216 to serve as a gate electrode and theinterconnect structure 225 is electrically connected to thedrain region 220 to serve as a drain electrode. - Referring to
FIG. 3B , a cross section of another exemplary embodiment of asemiconductor device 30 according to the invention is shown. Elements inFIG. 3B that are the same as those inFIG. 2D are labeled with the same reference numbers as inFIG. 2D and are not described again for brevity. In the embodiment, the structure of thesemiconductor device 30 is similar to that of the semiconductor device 20 (as shown inFIG. 2D ). The difference is that theepitaxial structure 210 in thesemiconductor device 30 comprises a plurality of vertically stacked epitaxial layers 202. It is realized that the number ofepitaxial layers 202 used is determined by the design demands and is not limited to the embodiment inFIG. 3B (i.e., theepitaxial layers 202 may be more than three layers). In the embodiment, thewell region 204 extends into theunderlying semiconductor substrate 200 from theepitaxial structure 210. Moreover, thesource region 218, thedrain region 220 and thebody region 212 are formed in theuppermost epitaxial layer 202 of theepitaxial structure 210. - In one embodiment, the
semiconductor device 30 comprises at least one set of the first and second heavily dopedregions well region 204 corresponding to thesemiconductor substrate 200 or in thewell region 204 corresponding to one of the epitaxial layers 202. In another embodiment, thesemiconductor device 30 comprises a plurality of sets of first and second heavily dopedregions well region 204 corresponding to eachepitaxial layer 202 and thesemiconductor substrate 200. It is realized that the number of sets of first and second heavily dopedregions epitaxial layers 202, such that none of the first and second heavily dopedregions well region 204 corresponding to some of theepitaxial layers 202 and/or thesemiconductor substrate 200. Compared with the embodiment inFIG. 2D , there may be more super junction structures in the embodiment inFIG. 3B . - In the foregoing embodiment, the heavily doped region of the first conductivity type and electrically floating in the super junction structure may help in the formation of a depletion region in the well region 204 (i.e., the drift region) thereby improving the withstand voltage of the LDMOSFET in the
semiconductor device -
FIGS. 2A to 2D are cross sections of an exemplary embodiment of a method for fabricating asemiconductor device 20 according to the invention. Referring toFIG. 2A , asemiconductor substrate 200, such as a silicon substrate, a silicon on insulator (SOI) substrate or other suitable semiconductor substrates, of a first conductivity type is provided. Next, awell region 204 is formed in a predetermined region (i.e., an active region A) of thesemiconductor substrate 200 sequentially by a doping process (e.g., ion implantation), and a thermal diffusion process. - Afterwards, an
epitaxial structure 210 of the first conductivity type is formed on thesemiconductor substrate 200. In the embodiment, theepitaxial structure 210 is composed of a single layer. For example, theepitaxial structure 210 is composed of anepitaxial layer 202. After forming the epitaxial layer 202 (i.e., the epitaxial structure 210) by an epitaxial growth process, the doping process (e.g., ion implantation), and the thermal diffusion process are sequentially performed in theepitaxial structure 210 corresponding to the active region A, such that thewell region 204 in thesemiconductor substrate 200 extends into theepitaxial structure 210, wherein thewell region 204 of a second conductivity type different from the first conductivity type is configured to serve as a drift region of a subsequently formed LDMOSFET. In other embodiments, thewell region 204 may be formed by other fabricating methods. For example, U.S. Pat. No. 7,682,955, disclosing a method for forming a deep well of a power device, is incorporated herein as reference. - In the embodiment, at least one set of the first and second heavily doped
regions well region 204, wherein the first and second heavily dopedregions regions well region 204 to form a super junction structure in thewell region 204 of theepitaxial structure 210. For example, after forming thewell region 204 in the epitaxial structure 210 (i.e., the epitaxial layer 202), one set of the first and second heavily dopedregions well region 204 of theepitaxial layer 202 by a doping process, such as ion implantation. - In another embodiment, one set of the first and second heavily doped
regions well region 204 of thesemiconductor substrate 200 before forming theepitaxial layer 202. In yet another embodiment, one set of the first and second heavily dopedregions well region 204 of thesemiconductor substrate 200 before forming theepitaxial layer 202. Next, another set of the first and second heavily dopedregions well region 204 of theepitaxial layer 202 after forming theepitaxial layer 202 and awell region 204 therein, as shown inFIG. 2A . These two sets of first and second heavily dopedregions epitaxial layer 202 and thesemiconductor substrate 200. - In the foregoing embodiment, the first and second heavily doped
regions drain region 220 and a source region 218 (as shown inFIG. 2C ) that are subsequently formed, wherein the first heavily dopedregion 201 is electrically floating. In the embodiment, the first conductivity type is p-type and the second conductivity type is n-type. Alternatively, the first conductivity type is n-type and the second conductivity type is p-type. - Referring to
FIGS. 2B and 2C , a plurality of isolation structures, such as afield oxide layer 214, may be formed on theepitaxial structure 210 by the conventional MOS process, wherein the active region A is defined by a portion of thefield oxide layer 214 and a drain region D to be formed in thewell region 204 is defined by the rest of thefield oxide layer 214. Afterwards, agate structure 216 is formed on theepitaxial structure 210 to define a source region S to be formed in the active region A outside of thewell region 204, as shown inFIG. 2B . - Next, a
body region 212 of the first conductivity type is optionally formed in theepitaxial structure 210 outside of thewell region 204 sequentially by a doping process (e.g., ion implantation), and a thermal diffusion process, such that the subsequently formedsource region 218 is in thebody region 212. A dopedregion 218 a of the second conductivity type is then formed in the source region S to be formed (as shown in FIG. 2B) and another doped region (i.e., the drain region 220) of the second conductivity type is formed in the drain region D to be formed (as shown inFIG. 2B ) by a doping process (e.g., ion implantation). Afterwards, a dopedregion 218 b of the first conductivity type is formed in the source region S to be formed (as shown inFIG. 2B ) and adjacent to the dopedregion 218 a, such that the dopedregion 218 b and the dopedregion 218 a form asource region 218, as shown inFIG. 2C . - In other embodiments, the doped
region 218 b may be formed before forming the dopedregion 218 a and thedrain region 220. In the embodiment, the dopedregion 218, thegate structure 216, thedrain region 220 and thewell region 204 having the super junction structures form an LDMOSFET. - Referring to
FIG. 2D , aninterlayer dielectric layer 226 and a plurality ofinterconnect structures epitaxial layer 202 by the conventional metallization process. Theinterconnect structure 221 is electrically connected to thesource region 218 to serve as a source electrode, theinterconnect structure 223 is electrically connected to thegate structure 216 to serve as a gate electrode and theinterconnect structure 225 is electrically connected to thedrain region 220 to serve as a drain electrode. As a result, the fabrication of thesemiconductor device 20 is completed. -
FIGS. 3A to 3B are cross sections of another exemplary embodiment of a method for fabricating asemiconductor device 30 according to the invention. Elements inFIGS. 3A to 3B that are the same as those inFIGS. 2A to 2D are labeled with the same reference numbers as inFIGS. 2A to 2D and are not described again for brevity. Referring toFIG. 3A , asemiconductor substrate 200 is provided. Next, awell region 204 is formed in an active region A of thesemiconductor substrate 200 sequentially by a doping process and a thermal diffusion process. - Afterwards, an
epitaxial structure 210 of the first conductivity type is formed on thesemiconductor substrate 200. In the embodiment, theepitaxial structure 210 comprises multiple layers. For example, theepitaxial structure 210 comprises a plurality ofepitaxial layers 202 stacked vertically. The plurality ofepitaxial layers 202 may be formed by an epitaxial growth process. It is noted that before forming thenext epitaxial layer 202, a doping process and a thermal diffusion process are performed in theformer epitaxial layer 202, such that thewell region 204 in thesemiconductor substrate 200 extends into theepitaxial structure 210 to serve as a drift region of the LDMOSFET subsequently formed. - In the embodiment, at least one set of the first and second heavily doped
regions well region 204. For example, after forming thecorresponding well region 204 in one of theepitaxial layers 202 of theepitaxial structure 210, one set of the first and second heavily dopedregions well region 204 of the correspondingepitaxial layer 202. - In another embodiment, one set of the first and second heavily doped
regions well region 204 corresponding to thesemiconductor substrate 200 before forming theepitaxial structure 210. In yet another embodiment, one set of the first and second heavily dopedregions well region 204 corresponding to thesemiconductor substrate 200 before forming theepitaxial structure 210. Next, another set of the first and second heavily dopedregions corresponding well region 204 of eachepitaxial layer 202, after forming eachepitaxial layer 202 and thecorresponding well region 204 therein, as shown inFIG. 3A . The plurality of sets of first and second heavily dopedregions epitaxial structure 210 and thesemiconductor substrate 200. - Referring to
FIG. 3B , afield oxide layer 214 and agate structure 216 may be formed on theepitaxial structure 210 and abody region 212, asource region 218 and adrain region 220 may be formed on theuppermost epitaxial layer 202 by the conventional MOS process. Afterwards, an interlayer dielectric (ILD)layer 226 and a plurality ofinterconnect structures epitaxial structure 210 by the conventional metallization process. As a result, fabrication of thesemiconductor device 30 is completed. - According to the foregoing embodiments, the heavily doped region of the first conductivity type and electrically floating in the super junction structure may form a depletion region in the drift region, so that the withstand voltage of the LDMOSFET in the semiconductor device is improved. Moreover, the heavily doped region of the second conductivity type in the super junction structure may provide an additional current path in the drift region, so that the on-resistance of the LDMOSFET is reduced. Additionally, according to the foregoing embodiments, the number of super junction structures stacked vertically in the drift region may be controlled to further improve the withstand voltage of the LDMOSFET while preventing the on-resistance of the LDMOSFET from increasing.
- While the invention has been described by way of example and in terms of the preferred embodiments, it is to be understood that the invention is not limited to the disclosed embodiments. To the contrary, it is intended to cover various modifications and similar arrangements (as would be apparent to those skilled in the art). Therefore, the scope of the appended claims should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements.
Claims (18)
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US20150137229A1 (en) * | 2013-11-15 | 2015-05-21 | Vanguard International Semiconductor Corporation | Semiconductor device and method for fabricating the same |
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US9263574B1 (en) * | 2014-11-07 | 2016-02-16 | Vanguard International Semiconductor Corporation | Semiconductor device and method for fabricating the same |
CN105161538A (en) * | 2015-08-07 | 2015-12-16 | 电子科技大学 | Transverse high-pressure device and manufacturing method thereof |
CN105070754A (en) * | 2015-08-07 | 2015-11-18 | 电子科技大学 | Lateral high-voltage device and manufacturing method thereof |
US9929283B1 (en) | 2017-03-06 | 2018-03-27 | Vanguard International Semiconductor Corporation | Junction field effect transistor (JFET) with first and second top layer of opposite conductivity type for high driving current and low pinch-off voltage |
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US11355580B2 (en) * | 2019-10-18 | 2022-06-07 | Semiconductor Components Industries, Llc | Lateral DMOS device with step-profiled RESURF and drift structures |
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