JP2013206960A - Semiconductor device and semiconductor device manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a transistor which can prevent decrease in on-state current while reducing leakage current.SOLUTION: A semiconductor device comprises: a first conductivity type substrate 10; a gate insulation film 20 provided on the substrate 10; a gate electrode 22 provided on the gate insulation film 20; source/drain regions 36 which are the second conductivity type opposite to the first conductive type, are positioned on both sides of the gate electrode 22, and have ends overlapping the gate electrode 22; and a counter region 32 which is formed by introduction of a first conductivity type impurity into the substrate 10, and is positioned on the drain region, and in which an end on the gate electrode 22 side is positioned inside the drain region.

Description

  The present invention relates to a semiconductor device and a method for manufacturing the semiconductor device, and particularly to a semiconductor device having a transistor and a method for manufacturing the semiconductor device.

  In order to improve the reliability of the transistor, for example, it is required to reduce leakage current. In Patent Document 1, the peak of the electric field generated between the gate electrode and the drain region is located at a certain depth from the substrate surface by separating the semiconductor region constituting the drain region and the gate insulating film. . This describes that leakage current flowing through the gate insulating film can be reduced.

For example, Patent Documents 2 to 6 disclose techniques for improving the reliability of transistors.
The techniques described in Patent Documents 2 and 3 relate to a technique for relaxing a drain electric field by forming an LDD (Lightly Doped Drain) region, and controlling the impurity concentration distribution in the LDD region.
Patent Document 4 describes forming a halo region in order to suppress deterioration of short channel characteristics. Specifically, it is described that low-concentration halo regions are formed above and below the source / drain extension regions. Further, Patent Documents 5 and 6 also disclose techniques related to a transistor having a pocket injection region.

JP-A-3-30370 JP 2000-307113 A Japanese Patent Laid-Open No. 10-12870 Japanese Patent Laid-Open No. 2007-235099 JP 2000-208766 A JP-A-5-267331

As a leakage current of a transistor, for example, a gate-induced drain leakage current (GIDL (Gate Induced Drain Leakage)) can be given. GIDL is a leakage current flowing between the drain region and the substrate, and is generated due to the electric field in the gate overlap region being strengthened by the gate voltage. Note that the gate overlap region refers to a region of the drain region that overlaps with the gate electrode.
The reduction of GIDL is realized, for example, by separating a channel and a drain region formed under the gate electrode. However, when the channel and the drain region are separated from each other, a parasitic resistance is generated between the drain region and the channel. That is, the on-state current of the transistor is reduced.
Therefore, it is required to prevent a decrease in on-current while reducing leakage current.

According to the present invention, a first conductivity type substrate;
A first gate insulating film provided on the substrate;
A first gate electrode provided on the first gate insulating film;
A first source region and a first drain region that are located on both sides of the first gate electrode, have end portions overlapping the first gate electrode, and have a second conductivity type opposite to the first conductivity type; ,
Formed by introducing the first conductivity type impurity into the substrate, located above the first drain region, and an end on the first gate electrode side located inside the first drain region Counter area,
A semiconductor device is provided.

  According to the present invention, a step of forming a gate insulating film on a first conductivity type substrate; a step of forming a gate electrode on the gate insulating film; and A first doping step of introducing an impurity of a second conductivity type opposite to the first conductivity type; and using the gate electrode as a mask, the impurity of the first conductivity type is applied to the substrate in a direction perpendicular to the substrate plane. There is provided a method for manufacturing a semiconductor device, comprising: a second doping step introduced shallower than the first doping step; and a step of performing a heat treatment on the substrate.

  Further, according to the present invention, a step of forming a gate insulating film on the first conductivity type semiconductor substrate, a step of forming a gate electrode on the gate insulating film, and the substrate using the gate electrode as a mask. A fourth doping step of introducing an impurity of the first conductivity type; a step of forming a gate sidewall film on a side surface of the gate electrode; and the first electrode on the substrate using the gate electrode and the gate sidewall film as a mask. Provided is a method for manufacturing a semiconductor device, comprising: a fifth doping step of introducing an impurity of a second conductivity type opposite to the conductivity type deeper than the fourth doping step; and a step of performing a heat treatment on the substrate. Is done.

  According to the present invention, it is possible to provide a transistor capable of preventing a decrease in on-current while reducing leakage current.

1 is a cross-sectional view showing a semiconductor device according to a first embodiment. FIG. 2 is a cross-sectional view showing a DRAM region and a logic region of the semiconductor device shown in FIG. 1. FIG. 3 is a cross-sectional view showing a method for manufacturing the semiconductor device shown in FIG. 1. FIG. 3 is a cross-sectional view showing a method for manufacturing the semiconductor device shown in FIG. 1. FIG. 3 is a cross-sectional view showing a method for manufacturing the semiconductor device shown in FIG. 1. FIG. 3 is a cross-sectional view showing a method for manufacturing the semiconductor device shown in FIG. 1. FIG. 3 is a cross-sectional view showing a method for manufacturing the semiconductor device shown in FIG. 1. FIG. 3 is a cross-sectional view showing a method for manufacturing the semiconductor device shown in FIG. 1. It is sectional drawing which shows the semiconductor device which concerns on 2nd Embodiment. It is sectional drawing which shows the manufacturing method of the semiconductor device shown in FIG. It is sectional drawing which shows the manufacturing method of the semiconductor device shown in FIG. 2 is a graph showing an impurity concentration distribution in the semiconductor device shown in FIG. 1. 2 is a graph showing an impurity concentration distribution in the semiconductor device shown in FIG. 1. It is an energy band figure for demonstrating the effect of 1st Embodiment. It is a schematic diagram for demonstrating the effect of 1st Embodiment. It is a graph for demonstrating the effect of 1st Embodiment.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In all the drawings, the same reference numerals are given to the same components, and the description will be omitted as appropriate.

FIG. 1 is a cross-sectional view showing a semiconductor device 300 according to the first embodiment. As shown in FIG. 1, the semiconductor device 300 according to the present embodiment includes a substrate 10, a gate insulating film 20, a gate electrode 22, a source / drain region 36, and a counter region 32.
As will be described later, the semiconductor device 300 according to the present embodiment is, for example, an embedded DRAM in which a DRAM is embedded in a logic circuit.

The substrate 10 has a P-type conductivity type. The gate insulating film 20 is provided on the substrate 10. The gate electrode 22 is provided on the gate insulating film 20. The source / drain regions 36 are located on both sides of the gate electrode 22 and end portions thereof overlap the gate electrode 22. The source / drain region 36 has N-type conductivity. The counter region 32 is formed by introducing P-type impurities into the substrate 10. The counter region 32 is located above the drain region, and the end on the gate electrode 22 side is located inside the drain region. Note that the conductivity type of each component included in the semiconductor device 300 may be opposite to that shown in the present embodiment.
Hereinafter, the configuration of the semiconductor device 300 according to the present embodiment will be described in detail.

In the semiconductor device 300 according to the present embodiment, the substrate 10 is, for example, a silicon substrate. The substrate 10 has, for example, a P-type conductivity type.
As shown in FIG. 1, an element isolation region 12 is provided on the substrate 10. A portion of the substrate 10 surrounded by the element isolation region 12 is an element formation region.

As shown in FIG. 1, a gate insulating film 20 is provided on the substrate 10. In the present embodiment, the gate insulating film 20 is made of, for example, SiO ₂ or the like. A gate electrode 22 is provided on the gate insulating film 20. The gate electrode 22 is made of, for example, polysilicon.
Further, the gate electrode 22 may be a metal or a metal nitride provided on the high-k metal insulating film. In this case, the gate insulating film 20 is made of, for example, HfO ₂ , ZrO ₂ , HfSiO, ZrSiO, or the like. The gate electrode 22 is composed of, for example, a film made of Ti, Ta, W, TiN, or TaN, or a laminated film thereof. Further, the gate electrode 22 may be constituted by a film in which these films made of metal or metal nitride and a polysilicon film are laminated.

As shown in FIG. 1, for example, offset spacers 24 are provided on the side surfaces of the gate electrode 22 and the gate insulating film 20. The offset spacer 24 is formed by etching back the insulating film deposited on the substrate 10 and the gate electrode 22 by anisotropic etching. The offset spacer 24 is made of an insulating film such as a silicon oxide film.
A gate sidewall film 26 is provided on the side surfaces of the gate electrode 22 and the gate insulating film 20 via an offset spacer 24. The gate sidewall film 26 is formed, for example, by etching back an insulating film deposited on the substrate 10 and the gate electrode 22 by anisotropic etching. The gate sidewall film 26 is made of an insulating film such as a silicon oxide film.

As shown in FIG. 1, the substrate 10 is provided with source / drain regions 36. The source / drain regions 36 are located on both sides of the gate electrode 22. The source / drain region 36 includes a low concentration impurity region 30 and a high concentration impurity region 34. As shown in FIG. 1, for example, when a plurality of gate electrodes 22 are provided on an element formation region, the source / drain regions 30 may be shared by two adjacent gate electrodes 22. In the present embodiment, the source / drain region 36 has, for example, an N-type conductivity type.
Note that the drain refers to an electrode biased to a voltage higher than that of the source in circuit operation in the N-type transistor. In this embodiment, in a DRAM cell transistor, an electrode connected to a bit line is defined as a source, and an electrode connected to a capacitor (storage node) is defined as a drain. This is because the junction leakage current in a state where the positive charge is accumulated in the capacitor (storage node) and is highly biased (during holding) is a problem to be solved in the present embodiment. Note that when positive charges are accumulated in the capacitor (storage node) (during a write operation), the electrode connected to the bit line operates as a drain and the electrode connected to the capacitor (storage node) operates as a source.

An end portion of the low concentration impurity region 30 overlaps the gate electrode 22. The low concentration impurity region 30 constitutes, for example, an LDD (Light Doped Drain) region. A channel region is formed between ends of the low-concentration impurity regions 30 of the source region and the drain region located on the gate electrode 22 side. For this reason, the low-concentration impurity region 30 comes into contact with the channel region.
In the present embodiment, the low-concentration impurity region 30 has, for example, an N-type conductivity type. The N-type impurity concentration in the low-concentration impurity region 30 is, for example, 1E17 cm ⁻³ or more and 1E19 cm ⁻³ or less.

The end of the high concentration impurity region 34 on the gate electrode 22 side is positioned inside a counter region 32 described later. The high concentration impurity region 34 is provided, for example, inside the low concentration impurity region 30. The high-concentration impurity region 34 is located on the surface portion of the substrate 10 in order to be connected to a bit contact plug 60 and a capacitor contact plug 62 described later.
In the present embodiment, the high concentration impurity region 34 has, for example, an N-type conductivity type. In the present embodiment, the high concentration impurity region 34 has an N-type impurity concentration higher than that of the low concentration impurity region 30. The N-type impurity concentration in the high concentration impurity region 34 is, for example, 1E18 cm ⁻³ or more and 1E21 cm ⁻³ or less.

As shown in FIG. 1, the substrate 10 is provided with a counter region 32. The counter region 32 is located above the low concentration impurity region 30. The end of the counter region 32 on the gate electrode 22 side is located inside the low concentration impurity region 30. That is, the counter region 32 is not in contact with the channel region provided under the gate electrode 22. Note that the end of the counter region 32 on the gate electrode 22 side may overlap the gate electrode 22.
The counter region 32 is formed around the high concentration impurity region 34. A part of the counter region 32 is located between the channel region formed under the gate electrode 22 and the high concentration impurity region 34.
In the present embodiment, the counter region 32 is formed by introducing a P-type impurity into the substrate 10. The counter region 32 may be provided only in one of the source / drain regions 36 that functions as a drain region.
The P-type impurity concentration in the counter region 32 is, for example, 1E17 cm ⁻³ or more and 1E19 cm ⁻³ or less. The N-type impurity concentration in the counter region 32 is, for example, 1E17 cm ⁻³ or more and 1E19 cm ⁻³ or less.

12 and 13 are graphs showing impurity concentration distributions in the semiconductor device shown in FIG. 12 and 13 show the distribution of the impurity concentration in the AA ′ cross section of the substrate shown in FIG.
In the present embodiment, as shown in FIG. 12, in the counter region 32, the P-type impurity concentration is lower than the N-type impurity concentration, for example. That is, in the counter region 32, the donor concentration is higher than the acceptor concentration. In this case, as a result of compensation between the donor and the acceptor in the counter region 32, the counter region 32 becomes an N-type impurity region having a donor concentration lower than that in the low-concentration impurity region 30.

In the present embodiment, as shown in FIG. 13, the P-type impurity concentration may be higher than the N-type impurity concentration in at least a part of the counter region 32. That is, in at least a part of the counter region 32, the acceptor concentration is higher than the donor concentration. In this case, as a result of compensation between the donor and the acceptor in the counter region 32, at least a part of the counter region 32 becomes a P-type impurity region.
In the present embodiment, the counter region 32 refers to a region located, for example, inside the low-concentration impurity region 30 and having a P-type impurity concentration higher than the P-type impurity concentration in the substrate 10.

FIG. 2 is a cross-sectional view showing DRAM region 1 and logic region 2 of semiconductor device 300 shown in FIG. As shown in FIG. 2, the semiconductor device 300 includes a DRAM region 1 having DRAM cells and a logic region 2 having logic circuits.
The DRAM region 1 includes the cell transistor 40 including the gate insulating film 20, the gate electrode 22, the offset spacer 24, the gate sidewall film 26, the low concentration impurity region 30, the counter region 32, and the high concentration impurity region 34 described above. In the present embodiment, the DRAM region 1 may have a P-type transistor in addition to the cell transistor 40 which is an N-type transistor.

  In the DRAM region 1, an interlayer insulating film 80 is provided on the substrate 10 so as to cover the gate electrode 22. In the interlayer insulating film 80, the capacitor element 50 and the bit line 70 are provided. The bit line 70 is connected to one of the source / drain regions 36 that functions as a source region via a bit contact plug 60 provided in the interlayer insulating film 80. In this case, the bit contact plug 60 is connected to the high concentration impurity region 34 constituting the source region. A silicide layer 38 may be provided in a connection portion of the high concentration impurity region 34 with the bit contact plug 60.

  In the present embodiment, the capacitive element 50 is, for example, a DRAM. The capacitive element 50 and the cell transistor 40 constitute a DRAM cell. In the present embodiment, the DRAM region 1 may be provided with a control circuit for controlling reading and writing of the DRAM cell.

The capacitive element 50 includes a lower electrode 52, an upper electrode 56, and a capacitive insulating film 54. The lower electrode 52 is connected to one of the source / drain regions 36 that functions as a drain region via a capacitor contact plug 62 provided in the interlayer insulating film 80. In this case, the capacitor contact plug 62 is connected to the high concentration impurity region 34 constituting the drain region. In the high concentration impurity region 34, a silicide layer 38 may be provided at a connection portion with the capacitor contact plug 62.
A capacitive insulating film 54 is provided on the lower electrode 52. An upper electrode 56 is provided on the capacitor insulating film 54.

  In the DRAM region 1, an interlayer insulating film 82 is provided on the interlayer insulating film 80 where the capacitor element 50 is provided. For example, a wiring 72 is formed in the interlayer insulating film 82.

As shown in FIG. 2, the logic region 2 includes a substrate 110 and a transistor 140 provided on the substrate 110. The substrate 110 is made of, for example, a P-type silicon substrate common to the substrate 10. The substrate 110 has an impurity concentration different from that of the substrate 10, for example.
An element isolation region 112 is provided on the substrate 110. A part of the substrate 110 surrounded by the element isolation region 112 is an element formation region. In the present embodiment, the transistors 140 provided in each element formation region are isolated from each other by the element isolation region 112.

As shown in FIG. 2, a gate insulating film 120 is provided on the substrate 110. In the present embodiment, the gate insulating film 120 is made of, for example, SiO ₂ or the like. A gate electrode 122 is provided on the gate insulating film 120. The gate electrode 122 is made of, for example, polysilicon.
On the side surfaces of the gate electrode 122 and the gate insulating film 120, for example, an offset spacer 124 is provided. The offset spacer 124 is formed, for example, by etching back a silicon oxide film or the like deposited on the substrate 110 and the gate electrode 122 by anisotropic etching.
A gate sidewall film 126 is provided on the side surfaces of the gate electrode 122 and the gate insulating film 120 with an offset spacer 124 interposed therebetween. The gate sidewall film 126 is formed, for example, by etching back a silicon oxide film or the like deposited on the substrate 110 or the gate electrode 122 by anisotropic etching.

  As shown in FIG. 2, the substrate 110 is provided with source / drain regions 136. The source / drain regions 136 are located on both sides of the gate electrode 122. The source / drain region 136 includes a low concentration impurity region 130 and a high concentration impurity region 134. In the present embodiment, the source / drain region 136 has, for example, an N-type conductivity type.

An end portion of the low-concentration impurity region 130 overlaps with the gate electrode 122. In the present embodiment, the low-concentration impurity region 130 has, for example, an N-type conductivity type.
The high concentration impurity region 134 has an end on the gate electrode 122 side located inside the low concentration impurity region 130. Further, the high concentration impurity region 134 is located on the surface portion of the substrate 110 in order to be connected to a contact plug 160 described later. In the present embodiment, the high concentration impurity region 134 has, for example, an N-type conductivity type. In the present embodiment, the high concentration impurity region 134 has an N-type impurity concentration higher than that of the low concentration impurity region 130.

  As shown in FIG. 2, the substrate 110 is provided with a halo region 132 that covers the end of the source / drain region 130 on the gate electrode 122 side. In the present embodiment, the halo region 132 has, for example, a P-type conductivity type.

  In the logic region 2, an interlayer insulating film 180 is provided on the substrate 110 so as to cover the gate electrode 122. A wiring 170 is formed inside the interlayer insulating film 180. The wiring 170 is connected to the source / drain region 136 through a contact plug 160 provided in the interlayer insulating film 180. In this case, the contact plug 160 is connected to the high concentration impurity region 134 constituting the source / drain region 136. A silicide layer 138 may be provided in a portion connected to the contact plug 160 in the high concentration impurity region 134.

  In addition, the structure in this embodiment can be observed by, for example, electron beam holography observation of a cross section, or scanning-type spreading resistance microscope (SSRM (Scanning Spreading Resistance Microscope)) observation.

Next, a method for manufacturing the semiconductor device 300 according to the present embodiment will be described. 3 to 8 are sectional views showing a method for manufacturing the semiconductor device 300 shown in FIG.
First, an element formation region surrounded by an element isolation region 12 is formed on the substrate 10 constituting the DRAM region 1. Next, a gate electrode 22 is formed on the substrate 10 via a gate insulating film 20. Next, an oxide film is deposited on the substrate 10 and the gate electrode 22. This oxide film is etched back by anisotropic etching to form an offset spacer 24.
Also in the logic region 2, an element formation region surrounded by the element isolation region 112 is formed on the substrate 110. Next, the gate electrode 122 is formed over the substrate 110 with the gate insulating film 120 interposed therebetween. Next, an oxide film is deposited on the substrate 110 and the gate electrode 122. This oxide film is etched back by anisotropic etching to form an offset spacer 124.
Note that the gate insulating film 20 and the gate insulating film 120, the gate electrode 22 and the gate electrode 122, and the offset spacer 24 and the offset spacer 124 may be formed in the same process or may be formed in different processes.
Thereby, the structure shown in FIG. 3 is obtained.

Next, as shown in FIG. 4, in the DRAM region 1, N-type impurities are ion-implanted into the substrate 10 using the gate electrode 22 and the offset spacer 24 as a mask. Thereby, an N-type impurity implantation region 90 is formed. The ion implantation conditions at this time are, for example, phosphorus ions (P +), acceleration energy of 5 keV to 20 keV, and dose of 1E12 cm ^{−2 to} 1E14 cm ⁻² .
Also in the logic region 2, N-type impurities are ion-implanted into the substrate 10 using the gate electrode 122 and the offset spacer 124 as a mask. Thereby, an N-type impurity implantation region 190 is formed. Next, P-type impurities are obliquely ion implanted into the substrate 10 using the gate electrode 122 and the offset spacer 124 as a mask. Thereby, a P-type impurity implantation region 192 is formed. At this time, the P-type impurity implantation region 192 is formed so as to cover the N-type impurity implantation region 190.

Next, as shown in FIG. 5, in the DRAM region 1, P-type impurities are ion-implanted into the substrate 10 using the gate electrode 22 and the offset spacer 24 as a mask. Thereby, a P-type impurity implantation region 92 is formed. The ion implantation conditions at this time include, for example, boron ions (B +), acceleration energy of 0.5 keV to 3 keV, and dose of 1E12 cm ^{−2 to} 2E14 cm ⁻² .
The ion implantation is performed in a direction perpendicular to the plane of the substrate 10. In addition, the introduction depth of the P-type impurity in the ion implantation is shallower than the introduction depth of the N-type impurity in the ion implantation for forming the N-type impurity implantation region 90. For this reason, the P-type impurity implantation region 92 is provided inside the N-type impurity implantation region 90.

Next, as shown in FIG. 6, an oxide film is deposited on the substrate 10 and the gate electrode 22 in the DRAM region 1. This oxide film is etched back by anisotropic etching to form a gate sidewall film 26.
In the DRAM region 1, an oxide film is deposited on the substrate 110 and the gate electrode 122. This oxide film is etched back by anisotropic etching to form a gate sidewall film 126.
The gate sidewall film 26 and the gate sidewall film 126 may be formed by the same process or may be formed by separate processes.

Next, as shown in FIG. 7, in the DRAM region 1, N-type impurities are ion-implanted into the substrate 10 using the gate electrode 22, the offset spacer 24 and the gate sidewall film 26 as a mask. Thereby, a high concentration N-type impurity implantation region 94 is formed. The ion implantation conditions at this time are, for example, that the ion species is phosphorus ion (P +), the acceleration energy is 5 keV or more and 20 keV or less, and the dose is 1E14 cm ⁻² or more and 1E16 cm ⁻² or less.
The introduction depth of the N-type impurity in the ion implantation is deeper than the introduction depth of the P-type impurity in the ion implantation for forming the P-type impurity implantation region 92.
In the logic region 2, P-type impurities are ion-implanted into the substrate 110 using the gate electrode 122, the offset spacer 124 and the gate sidewall film 126 as a mask. Thereby, a high concentration N-type impurity implantation region 194 is formed.

Next, heat treatment is performed on the substrate 10 and the substrate 110.
By performing heat treatment on the substrate 10, the impurities in the N-type impurity implantation region 90, the P-type impurity implantation region 92, and the high-concentration N-type impurity implantation region 94 are activated and diffused. As a result, the low concentration impurity region 30, the counter region 32, and the high concentration impurity region 34 are formed in the substrate 10.
Further, by performing heat treatment on the substrate 110, the impurities in the N-type impurity implantation region 190, the P-type impurity implantation region 192, and the high-concentration N-type impurity implantation region 194 are activated and diffused. As a result, a low concentration impurity region 130, a halo region 132, and a high concentration impurity region 134 are formed. At this time, the halo region 132 having the P-type conductivity type suppresses the lateral expansion of the N-type impurity constituting the low-concentration impurity region 130. Thus, the short channel effect can be reduced in the transistor 140.
Thereby, the structure shown in FIG. 8 is obtained.

  Next, a silicide layer 38 is formed on the high concentration impurity region 34 in the DRAM region 1. Next, the bit contact plug 60, the capacitor contact plug 62, and the bit line 70 connected to the bit contact plug 60 are formed. The bit contact plug 60, the capacitor contact plug 62, and the bit line 70 are provided in an interlayer insulating film 80 formed on the substrate 10 and the gate electrode 22. Next, the lower electrode 52, the capacitor insulating film 54, and the upper electrode 56 are sequentially stacked in the concave portion formed in the interlayer insulating film 80. Thereby, the capacitive element 50 is formed on the interlayer insulating film 80. Next, an interlayer insulating film 82 is formed on the interlayer insulating film 80. Next, a wiring 72 is formed inside the interlayer insulating film 82. Thereby, the DRAM region 1 shown in FIG. 2 is obtained.

  In the logic region 2, a silicide layer 138 is formed on the high concentration impurity region 134. Next, an interlayer insulating film 180 is formed over the substrate 110 and the gate electrode 122. Next, a contact plug 160 is formed in the interlayer insulating film 180. Next, a wiring 170 connected to the contact plug 160 is formed inside the interlayer insulating film 180. Thereby, the logic region 2 shown in FIG. 2 is obtained.

Next, the effect of this embodiment will be described.
FIG. 14 is an energy band diagram for explaining the effect of the present embodiment. FIG. 15 is a schematic diagram for explaining the effect of the present embodiment. FIG. 16 is a graph for explaining the effect of the present embodiment.
As illustrated in FIG. 14, the drain leakage current occurs through electron-hole recombination levels formed in the depletion layer. At this time, the activation energy of the leakage current is determined according to the energy level of the recombination level. The smaller this activation energy, the easier it is for electrons and holes to recombine. That is, a leak current is likely to occur.
As the electric field of the depletion layer increases, this activation energy decreases. That is, the stronger the electric field of the depletion layer, the easier it is for electrons and holes to recombine, and the leakage current increases.

FIG. 15 shows a change in the electric field strength of the depletion layer formed around the drain when the dose amount when channel ions are implanted into the substrate is changed. In the example shown in FIG. 15, boron is implanted as channel ions. FIG. 15 shows an N-type transistor.
FIG. 15A shows the electric field strength of the depletion layer when the dose amount of channel ions is small. As shown in FIG. 15A, when the dose amount of channel ions is low, the electric field strength of the depletion layer generated in the gate overlap region by the gate voltage is increased. In this case, GIDL is generated between the drain region and the substrate.
FIG. 15B shows the electric field strength of the depletion layer when the channel ion dose is large. As shown in FIG. 15B, when the channel ion dose is high, the electric field strength of the depletion layer generated in the gate overlap region is reduced. This is due to the introduction of P-type impurity ions to repel N-type impurities in the drain. On the other hand, the electric field strength of the depletion layer of the PN junction formed by the drain region and the channel is increased. This increases the reverse junction leakage current of the PN junction.
Thus, if the dose amount of channel ions is too large or too small, the activation energy of the leakage current is reduced.

  FIG. 16 shows experimental results showing the relationship between the leakage current and the channel ion dose. From the experimental results shown in FIG. 16, it can be seen that the activation energy of the leakage current is reduced when the dose of channel ions is small and large.

The reduction of GIDL can be realized by separating the channel and the drain region formed under the gate electrode. For example, by introducing an impurity having a conductivity type opposite to that of the drain region into the gate overlap region to form a halo region, the drain region and the channel can be separated. Further, the channel and the drain region can be separated by offsetting the gate electrode and the drain region.
However, when the drain region and the channel are separated from each other, a parasitic resistance is generated between the drain region and the channel. That is, the on-state current of the transistor is reduced.

According to the present embodiment, the drain region whose end portion overlaps the gate electrode 22 and the counter region 32 that is located above the drain region and whose end portion on the gate electrode 22 side is located inside the drain region are provided. ing.
By forming the counter region 32, the electric field strength in the gate overlap region can be reduced. For this reason, the leakage current resulting from GIDL can be reduced. Further, the drain region is in contact with a channel formed under the gate electrode. For this reason, it is possible to prevent a decrease in on-current.

  Moreover, according to this embodiment, it is not necessary to increase the dose amount of channel ions in order to reduce GIDL. That is, it is possible to suppress an increase in the electric field strength of the PN junction formed between the drain region and the channel. Accordingly, an increase in reverse junction leakage current can be suppressed in the PN junction formed between the drain region and the channel.

FIG. 9 is a cross-sectional view showing a semiconductor device 302 according to the second embodiment, and corresponds to FIG. 1 in the first embodiment. 10 and 11 are cross-sectional views showing a method for manufacturing the semiconductor device 302 shown in FIG.
The semiconductor device 302 according to the present embodiment is the same as the semiconductor device 300 according to the first embodiment except for the method of forming the drain region and the counter region.

  A method for manufacturing the semiconductor device 302 according to the present embodiment will be described with reference to FIGS. 9 to 11 show only a method for manufacturing the cell transistor 40 in the DRAM region 1. The logic region 2 can be manufactured in the same manner as in the first embodiment.

  First, as shown in FIG. 10A, an element isolation region 12 is formed on a substrate 10. Next, the gate insulating film 20 and the gate electrode 22 are formed on the substrate 10. Next, offset spacers 24 are formed on the side surfaces of the gate electrode 22 and the gate insulating film 20. About these processes, it can carry out similarly to 1st Embodiment.

Next, as shown in FIG. 10B, P-type impurities are ion-implanted into the substrate 10 using the gate electrode 22 and the offset spacer 24 as a mask. Thereby, a P-type impurity implantation region 292 is formed. The ion implantation is performed in a direction perpendicular to the plane of the substrate 10. The ion implantation conditions at this time include, for example, boron ions (B +), acceleration energy of 0.5 keV to 3 keV, and dose of 1E12 cm ^{−2 to} 2E14 cm ⁻² .

Next, as illustrated in FIG. 11A, a gate sidewall film 226 is formed on the side surfaces of the gate electrode 22 and the gate insulating film 20 via an offset spacer 24.
Note that the width of the gate sidewall film 226 in the present embodiment is preferably thinner than the width of the gate sidewall film 26 in the first embodiment. Thereby, the low concentration impurity region 30 and the high concentration impurity region 34 to be described later can have a desired shape and positional relationship.

Next, as shown in FIG. 11B, N-type impurities are ion-implanted into the substrate 10 using the gate electrode 22, the offset spacer 24, and the gate sidewall film 226 as a mask. Thereby, a high concentration N-type impurity implantation region 290 is formed. The ion implantation conditions at this time are, for example, that the ion species is phosphorus ion (P +), the acceleration energy is 5 keV or more and 20 keV or less, and the dose is 1E14 cm ⁻² or more and 1E16 cm ⁻² or less.
The introduction depth of the N-type impurity in the ion implantation is deeper than the introduction depth of the P-type impurity in the ion implantation for forming the P-type impurity implantation region 292.

  Next, heat treatment is performed on the substrate 10. By performing heat treatment on the substrate 10, the impurities in the high-concentration N-type impurity implantation region 290 and the P-type impurity implantation region 292 are activated and diffused. Thereby, the low concentration impurity region 30, the counter region 32, and the high concentration impurity region 34 are formed.

Also in this embodiment, the same effect as that of the first embodiment can be obtained.
Further, according to the present embodiment, it is not necessary to introduce N-type impurities into the substrate 10 before the step of forming the P-type impurity implantation region 292. Therefore, the number of manufacturing steps can be reduced as compared with the first embodiment. Thereby, the manufacturing method of the semiconductor device excellent in low cost is realizable.

  As mentioned above, although embodiment of this invention was described with reference to drawings, these are the illustrations of this invention, Various structures other than the above are also employable.

1 DRAM region 2 Logic region 10 Substrate 12 Element isolation region 20 Gate insulating film 22 Gate electrode 24 Offset spacer 26 Gate sidewall film 30 Low concentration impurity region 32 Counter region 34 High concentration impurity region 36 Source / drain region 38 Silicide layer 40 Cell transistor 50 capacitive element 52 lower electrode 54 capacitive insulating film 56 upper electrode 60 bit contact plug 62 capacitive contact plug 70 bit line 72 wiring 80 interlayer insulating film 82 interlayer insulating film 90 N-type impurity implantation region 92 P-type impurity implantation region 94 high concentration N Type impurity implantation region 110 substrate 112 element isolation region 120 gate insulating film 122 gate electrode 124 offset spacer 126 gate sidewall film 130 low concentration impurity region 132 halo region 134 high concentration impurity region 136 source / drain N region 138 Silicide layer 140 Transistor 160 Contact plug 170 Wiring 180 Interlayer insulating film 190 N type impurity implantation region 192 P type impurity implantation region 194 High concentration N type impurity implantation region 226 Gate sidewall film 290 High concentration N type impurity implantation region 292 P Type impurity implantation region 300 Semiconductor device 302 Semiconductor device

Claims (12)

A first conductivity type substrate;
A first gate insulating film provided on the substrate;
A first gate electrode provided on the first gate insulating film;
A first source region and a first drain region that are located on both sides of the first gate electrode, have end portions overlapping the first gate electrode, and have a second conductivity type opposite to the first conductivity type; ,
Formed by introducing the first conductivity type impurity into the substrate, located above the first drain region, and an end on the first gate electrode side located inside the first drain region Counter area,
A semiconductor device comprising: The semiconductor device according to claim 1,
In the counter region, the first conductivity type impurity concentration is 1E17 cm ⁻³ or more and 1E19 cm ⁻³ or less, and the second conductivity type impurity concentration is 1E17 cm ⁻³ or more and 1E19 cm ⁻³ or less. The semiconductor device according to claim 1 or 2,
In the counter region, the first conductivity type impurity concentration is lower than the second conductivity type impurity concentration in the semiconductor device. The semiconductor device according to claim 1 or 2,
In the counter region, the first conductivity type impurity concentration is higher than the second conductivity type impurity concentration. 5. The semiconductor device according to claim 1, wherein:
The semiconductor device wherein the first conductivity type impurity concentration in the counter region is higher than the first conductivity type impurity concentration in the substrate. The semiconductor device according to any one of claims 1 to 5,
The first drain region has a higher impurity concentration of the second conductivity type than other regions in the first drain region, and the gate electrode side end portion is located inside the counter region. A semiconductor device. The semiconductor device according to claim 1,
A semiconductor device comprising a capacitive element connected to the first drain region. The semiconductor device according to claim 7,
A semiconductor device comprising a logic region having a logic circuit, which is a region different from a region where the capacitor element is provided over the substrate. The semiconductor device according to claim 8,
The logic area is
A second gate insulating film provided on the substrate;
A second gate electrode provided on the second gate insulating film;
A second source region and a second drain region of the second conductivity type located on both sides of the second gate electrode;
A semiconductor device. Forming a gate insulating film on a first conductivity type substrate;
Forming a gate electrode on the gate insulating film;
A first doping step of introducing an impurity of a second conductivity type opposite to the first conductivity type into the substrate using the gate electrode as a mask;
A second doping step of introducing the first conductivity type impurity into the substrate in a direction perpendicular to the substrate plane shallower than the first doping step, using the gate electrode as a mask;
Performing a heat treatment on the substrate;
A method for manufacturing a semiconductor device comprising: In the manufacturing method of the semiconductor device according to claim 10,
After the second doping step and before the step of performing heat treatment on the substrate,
Forming a gate sidewall film on a side surface of the gate electrode;
A third doping step for introducing the second conductivity type impurity into the substrate deeper than the second doping step using the gate electrode and the gate sidewall film as a mask;
A method for manufacturing a semiconductor device comprising: Forming a gate insulating film on a first conductivity type substrate;
Forming a gate electrode on the gate insulating film;
A fourth doping step of introducing the first conductivity type impurity into the substrate using the gate electrode as a mask;
Forming a gate sidewall film on a side surface of the gate electrode;
A fifth doping step of introducing an impurity of a second conductivity type opposite to the first conductivity type into the substrate deeper than the fourth doping step using the gate electrode and the gate sidewall film as a mask;
Performing a heat treatment on the substrate;
A method for manufacturing a semiconductor device comprising:

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