CN102969228B - Polysilicon resistor structure and its manufacture method - Google Patents
Polysilicon resistor structure and its manufacture method Download PDFInfo
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- CN102969228B CN102969228B CN201210507576.8A CN201210507576A CN102969228B CN 102969228 B CN102969228 B CN 102969228B CN 201210507576 A CN201210507576 A CN 201210507576A CN 102969228 B CN102969228 B CN 102969228B
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Abstract
The invention provides a kind of polysilicon resistor structure and its manufacture method.A kind of polysilicon resistor structure manufacture method includes：First step, for forming isolated area in silicon chip；Second step, for forming the first polysilicon layer and its side wall in isolated area；Third step, for forming spacer at the top of the first polysilicon layer, wherein spacer does not cover the top at the two ends of the first polysilicon layer；Four steps, for forming the second polysilicon layer on the spacers, wherein the second polysilicon layer does not cover the top at the two ends of the first polysilicon layer；5th step, for carrying out ion implanting by mask of the second polysilicon layer, to form metal silicide on the surface at the two ends of the exposure of the first polysilicon layer, and makes the surface of the unexposed part of the first polysilicon layer not form metal silicide.
Description
Technical field
The present invention relates to field of semiconductor manufacture, it is more particularly related to a kind of polysilicon resistor structure and
Its manufacture method.
Background technology
, can substantial amounts of use polysilicon resistance in semiconductor circuit chip design.Being used general circuit design personnel more
Traditional N-type or p-type polycrystalline resistor, but these resistance are required for silicide barrier layer (salicide in the fabrication process
Block layer, SAB) as an extra mask for protection silicon chip surface, under its protection, silicon chip not with it is other
Ti, Co etc metal form undesirable metal silicide, that is, need to increase by one of lithography step.Specifically, existing skill
The polysilicon of polysilicon or the p-type doping of the n-type doping as polyresistor in art is by logic polysilicon
On (being undoped in itself), N-type ion implanting (being typically boron (B) ion implanting of high concentration) or p-type ion implanting are carried out
Phosphorus (P) ion implanting of high concentration (be typically) and formed, they are required for silicide stop layer as light shield.However, silication
The introducing of thing trapping layer increases the complexity of technique, and increases manufacturing cost.
The storage polysilicon resistance proposed in the improvement project of prior art does not need silicide barrier layer, reduces system
Cause this.But, the polysilicon resistance is n-type resistance, and temperature coefficient is larger；In addition the polysilicon is that doping concentration is higher, because
This resistance value is smaller, is unfavorable for reducing circuit area.
Chinese patent application CN 102214560A propose a kind of utilize and store polysilicon MPOL formation polyresistors
Scheme, but storage polysilicon MPOL minimum widith can not be made very small, and thus limit made polysilicon resistance
The resistance size of device, when needing the polyresistor of larger resistance, it is necessary to which very long storage polysilicon strip realizes big electricity
Resistance, therefore be unfavorable for saving chip area.
Accordingly, it is desirable to be able to propose that one kind can prevent polyresistor in the case of without using silicide barrier layer
Surface forms the simplification polysilicon resistor structure fabrication scheme that thus metal silicide increases storage polysilicon resistance rate.
The content of the invention
The technical problems to be solved by the invention are can be not there is provided one kind for there is drawbacks described above in the prior art
Prevent polyresistor surface from forming metal silicide and thus increasing polysilicon resistance in the case of using silicide barrier layer
The polysilicon resistor structure manufacture method and corresponding polysilicon resistor structure of the simplification of rate.
In order to realize above-mentioned technical purpose, there is provided a kind of polysilicon resistor structure according to the first aspect of the invention
Manufacture method, it includes：First step, for forming isolated area in silicon chip；Second step, for forming in isolated area
The side wall of one polysilicon layer and the first polysilicon layer；Third step, for forming spacer at the top of the first polysilicon layer,
Wherein spacer does not cover the top at the two ends of the first polysilicon layer；Four steps, for forming the second polycrystalline on the spacers
Silicon layer, wherein the second polysilicon layer does not cover the top at the two ends of the first polysilicon layer；5th step, for the second polysilicon
Layer carries out ion implanting for mask, to form metal silicide on the surface at the two ends of the exposure of the first polysilicon layer, and
The surface of the unexposed part of the first polysilicon layer is set not form metal silicide.
Preferably, first polysilicon layer is the source electrode line polysilicon layer of memory transistor cell；Its side wall is profit
Manufactured with the production stage for the sidewall structure for being used to isolate floating boom and source electrode line in memory production process.
Preferably, second polysilicon layer is that processing step defines its shape after the first polysilicon layer by light shield
The layer that can be used to the formation of barrier metal silicide of shape.
Preferably, second polysilicon layer is the gate polysilicon layer of memory mos transistor unit.
Preferably, second polysilicon layer is the word line polysilicon layer of memory.
Preferably, the width of the resistor subtracts both sides resistor by the overall width of the figure of definition floating boom light shield
The width of side wall is determined；The length direction of the resistor by the second polysilicon layer cover during metallization process it is not sudden and violent
The length of the first polysilicon layer exposed is determined.
There is provided a kind of polysilicon resistor structure according to the second aspect of the invention, it is characterised in that including：It is arranged in
Isolated area in silicon chip, the first polysilicon layer formed in isolated area and its side wall, formed at the top of the first polysilicon layer
Spacer and the second polysilicon layer for being formed on the spacers；Wherein, spacer does not cover the two ends of the first polysilicon layer
Top, the second polysilicon layer do not cover the top at the two ends of the first polysilicon layer；Wherein, the two of the exposure of the first polysilicon layer
The surface at end is formed with metal silicide, and the surface of the unexposed part of the first polysilicon layer is formed without metallic silicon
Compound.
Preferably, second polysilicon layer is the gate polysilicon layer or memory of memory mos transistor unit
Word line polysilicon layer.
Preferably, first polysilicon layer is the source electrode line polysilicon layer of memory transistor cell.
Preferably, the width of the resistor subtracts both sides resistor by the overall width of the figure of definition floating boom light shield
The width of side wall is determined；The length direction of the resistor by the second polysilicon layer cover during metallization process it is not sudden and violent
The length of the first polysilicon layer exposed is determined.
Thus, in the present invention, the second polysilicon layer, which is served, protects the first following polysilicon layer not form metallic silicon
The effect of compound, is thus served and silicide stop layer identical function；So, the present invention is advantageous by utilization more than second
Crystal silicon layer as non-silicide structure mask, it is to avoid the use of silicide stop layer.So that technique becomes simple, and drop
Low process costs, shorten the manufacturing cycle.Also, each step of the present invention can be incorporated into each of memory circuitry manufacture
In step, the new step without increasing.In addition, with the prior art using store polysilicon (word line polysilicon layer) formation polycrystalline
The scheme of silicon resistor is compared, and the minimum widith of the first polysilicon layer can be made smaller very than the minimum widith for storing polysilicon
It is many, so being conducive to improving resistivity, save device area.
Brief description of the drawings
With reference to accompanying drawing, and by reference to following detailed description, it will more easily have more complete understanding to the present invention
And its adjoint advantages and features is more easily understood, wherein：
Fig. 1 schematically shows the flow of polysilicon resistor structure manufacture method according to a first embodiment of the present invention
Figure.
Fig. 2 schematically shows the region position of the vertical view of polysilicon resistor structure according to a second embodiment of the present invention
Put graph of a relation.
Fig. 3 schematically shows the sectional view of polysilicon resistor structure according to a second embodiment of the present invention.
It should be noted that accompanying drawing is used to illustrate the present invention, it is not intended to limit the present invention.Note, represent that the accompanying drawing of structure can
It can be not necessarily drawn to scale.Also, in accompanying drawing, same or similar element indicates same or similar label.
Embodiment
In order that present disclosure is more clear and understandable, with reference to specific embodiments and the drawings in the present invention
Appearance is described in detail.
<First embodiment>
Fig. 3 schematically shows the flow of polysilicon resistor structure manufacture method according to a first embodiment of the present invention
Figure.Figures 1 and 2 show that corresponding polysilicon resistor structure, the position that wherein Fig. 1 schematically shows subregion is closed
System.
With reference to shown in Fig. 1, Fig. 2 and Fig. 3, polysilicon resistor structure manufacture method according to a first embodiment of the present invention
Including：
First step S1：Isolated area 11 is formed in silicon chip (not shown to come out), such as isolated area 11 is shallow trench isolation
Area or other types of isolated area；
Second step S2：The side wall 13 (of the first polysilicon layer 2 and the first polysilicon layer 2 is formed in isolated area 11
The medium of the both sides of one polysilicon layer 2), it is preferable that first polysilicon layer 2 is to utilize to be used for source electrode in memory production process
What the production stage of the polysilicon layer of line was manufactured；Wherein, the first polysilicon layer 2 forms the electricity of polysilicon resistor structure
Resistance part point.
Third step S3：Spacer 12 is formed at the top of the first polysilicon layer 2, wherein spacer 12 is not covered more than first
The top at the two ends of crystal silicon layer 2；
Four steps S4：The second polysilicon layer 3 is formed on spacer 12, wherein the second polysilicon layer 3 does not cover first
The top at the two ends of polysilicon layer 2；For example, the second polysilicon at end positions that can be by etching away the first polysilicon layer 2
Layer 3 causes the second polysilicon layer 3 not cover the top at the two ends of the first polysilicon layer 2.
Preferably, the side wall of the first polysilicon layer 2 is to utilize to be used to isolate floating boom and source electrode line in memory production process
The production stage of sidewall structure manufacture.
Preferably, second polysilicon layer 3 is the gate polysilicon layer or memory of memory mos transistor unit
Word line polysilicon layer (memory poly, MPOL).
5th step S5：For being that mask carries out ion implanting with the second polysilicon layer 3, so as in the first polysilicon layer 2
The surface at two ends of exposure form metal silicide, and make the surface not shape of the unexposed part of the first polysilicon layer 2
Into metal silicide；That is, because the polysilicon layer 3 of spacer 12 and second does not cover the top at the two ends of the first polysilicon layer 2,
Thus the two ends exposure of the first polysilicon layer 2, so as to form metallic silicon on the region at the two ends of the exposure of the first polysilicon layer 2
Compound, so as to be conducive to forming the contact portion 41 and 42 with other function element wherein.
As shown in Fig. 2 the resistor formation being thus made is in the first polysilicon layer 2, the width of the resistor by
The overall width of the figure of floating boom light shield subtracts the width decision of both sides resistor side wall defined in manufacturing process；The resistor
The length for the first polysilicon layer not being exposed during metallization process that length direction is covered by the second polysilicon layer
Determine.
So, protect the first following polysilicon layer 2 not form metal silication in fact, the second polysilicon layer 3 is served
The effect of thing, is thus served and silicide stop layer identical function；So, the embodiment of the present invention is advantageous by utilizing
Two polysilicon layers 3 as non-silicide structure mask, it is to avoid the use of silicide stop layer.So that technique becomes simple,
And process costs are reduced, the manufacturing cycle is shortened.Also, above-mentioned steps can be incorporated into each step of memory circuitry manufacture
In rapid, the new step without increasing.In addition, with utilizing word line polysilicon layer MPOL formation polyresistors in the prior art
Scheme is compared, and the minimum widith that the minimum widith of the first polysilicon layer can be made than word line polysilicon layer MPOL is much smaller, institute
To be conducive to improving resistivity, device area is saved.
<Second embodiment>
The part that Fig. 2 schematically shows the vertical view of polysilicon resistor structure according to a second embodiment of the present invention shows
It is intended to.Fig. 3 schematically shows the sectional view of polysilicon resistor structure according to a second embodiment of the present invention.Specifically
Say, Fig. 3 is the sectional view along Fig. 2 line A-A interceptions.
As shown in Figures 2 and 3, polysilicon resistor structure according to a second embodiment of the present invention includes：It is arranged in silicon chip
In isolated area 11 and its side wall 13 (for example, isolated area 11 is shallow channel isolation area or other types of isolated area), every
From the first polysilicon layer 2 formed in area 11, (preferably, first polysilicon layer 2 is to utilize to use in memory production process
Manufactured in the production stage of the polysilicon layer of source electrode line), the first polysilicon layer 2 top formed spacer 12
(spacer 12 does not cover the top at the two ends of the first polysilicon layer 2), the second polysilicon layer 3 (formed on spacer 12
Two polysilicon layers 3 do not cover the top at the two ends of the first polysilicon layer 2).
Wherein, the surface at the two ends of the exposure of the first polysilicon layer 2 is formed with metal silicide, and makes the first polysilicon
The surface of the unexposed part of layer 2 is formed without metal silicide.
Preferably, second polysilicon layer 3 is the gate polysilicon layer or memory of memory mos transistor unit
Word line polysilicon layer.
In order to make it easy to understand, the floating gate region 5 of memory mos transistor unit is shown in Fig. 1, it is possible thereby to more convenient
Find out the relative position situation of regional in ground.
The width of the resistor of polysilicon resistor structure according to a second embodiment of the present invention is by definition floating boom light
The width that the overall width of the figure of cover subtracts both sides resistor side wall is determined；The length direction of the resistor is by the second polysilicon
The length of the first polysilicon layer not being exposed during metallization process of layer covering is determined.
Furthermore, it is necessary to explanation, unless stated otherwise or is pointed out, term " first " otherwise in specification, " the
Two ", the description such as " 3rd " is used only for distinguishing each component, element, step in specification etc., without being intended to indicate that each
Logical relation or ordinal relation between component, element, step etc..
Although it is understood that the present invention is disclosed as above with preferred embodiment, but above-described embodiment and being not used to
Limit the present invention.For any those skilled in the art, without departing from the scope of the technical proposal of the invention,
Many possible variations and modification are all made to technical solution of the present invention using the technology contents of the disclosure above, or are revised as
With the equivalent embodiment of change.Therefore, every content without departing from technical solution of the present invention, the technical spirit pair according to the present invention
Any simple modifications, equivalents, and modifications made for any of the above embodiments, still fall within the scope of technical solution of the present invention protection
It is interior.
Claims (9)
1. a kind of polysilicon resistor structure manufacture method, it is characterised in that including：
First step, for forming isolated area in silicon chip；
Second step, the side wall for forming the first polysilicon layer and the first polysilicon layer in isolated area；
Third step, for forming spacer at the top of the first polysilicon layer, wherein spacer does not cover the first polysilicon layer
Two ends top；
Four steps, for forming the second polysilicon layer on the spacers, wherein the second polysilicon layer does not cover the first polysilicon
The top at the two ends of layer；
5th step, for carrying out ion implanting by mask of the second polysilicon layer, so as in the exposure of the first polysilicon layer
The surface at two ends forms metal silicide, and the surface of the unexposed part of the first polysilicon layer is not formed metal silication
Thing；
Wherein, first polysilicon layer utilizes the production stage system for the polysilicon layer for being used for source electrode line in memory production process
Create, its side wall, which is utilized, is used for the production stage manufacture for isolating the sidewall structure of floating boom and source electrode line in memory production process
Out.
2. polysilicon resistor structure manufacture method according to claim 1, it is characterised in that first polysilicon layer
It is the source electrode line polysilicon layer of memory transistor cell.
3. polysilicon resistor structure manufacture method according to claim 1, it is characterised in that second polysilicon layer
It is that the can be used to barrier metal silicide that by light shield defines its shape of the processing step after the first polysilicon layer is formed
Layer.
4. polysilicon resistor structure manufacture method according to claim 1, it is characterised in that second polysilicon layer
It is the gate polysilicon layer of memory mos transistor unit.
5. polysilicon resistor structure manufacture method according to claim 1, it is characterised in that second polysilicon layer
It is the word line polysilicon layer of memory.
6. the polysilicon resistor structure manufacture method according to one of claim 1-5, it is characterised in that the resistor
The width that the width of structure subtracts both sides resistor side wall by the overall width of the figure of definition floating boom light shield is determined；The electricity
The first polycrystalline not being exposed during metallization process that the length direction of resistance device structure is covered by the second polysilicon layer
The length of silicon layer is determined.
7. a kind of polysilicon resistor structure, it is characterised in that using the polysilicon electricity as described in any one of claim 1~6
Resistance device structure making process is fabricated by, and the polysilicon resistor structure includes：It is arranged in isolated area in silicon chip, in isolation
The first polysilicon layer and its side wall that are formed in area, the spacer formed at the top of the first polysilicon layer and in spacer
Second polysilicon layer of upper formation；
Wherein, spacer does not cover the top at the two ends of the first polysilicon layer, and the second polysilicon layer does not cover the first polysilicon layer
Two ends top；
Wherein, the surface at the two ends of the exposure of the first polysilicon layer is formed with metal silicide, and makes the first polysilicon layer
The surface of unexposed part is formed without metal silicide；
Wherein, first polysilicon layer is the source electrode line polysilicon layer of memory transistor cell.
8. polysilicon resistor structure according to claim 7, it is characterised in that second polysilicon layer is memory
The gate polysilicon layer of MOS transistor unit or the word line polysilicon layer of memory.
9. the polysilicon resistor structure according to one of claim 7-8, it is characterised in that the width of the resistor structure
The width that degree direction subtracts both sides resistor side wall by the overall width of the figure of definition floating boom light shield is determined；The resistor structure
The length of the first polysilicon layer not being exposed during metallization process that is covered by the second polysilicon layer of length direction
Degree is determined.
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| CN201210507576.8A CN102969228B (en) | 2012-11-30 | 2012-11-30 | Polysilicon resistor structure and its manufacture method |
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|---|---|---|---|
| CN201210507576.8A CN102969228B (en) | 2012-11-30 | 2012-11-30 | Polysilicon resistor structure and its manufacture method |
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| CN102969228A CN102969228A (en) | 2013-03-13 |
| CN102969228B true CN102969228B (en) | 2017-09-19 |
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| CN112928209A (en) * | 2021-01-22 | 2021-06-08 | 上海华虹宏力半导体制造有限公司 | Preparation method of polysilicon resistor |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102214560A (en) * | 2011-05-27 | 2011-10-12 | 上海宏力半导体制造有限公司 | Resistor structure and manufacturing method thereof |
| CN102347281A (en) * | 2011-10-28 | 2012-02-08 | 上海宏力半导体制造有限公司 | Split-gate flash memory unit and forming method thereof |
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| CN100372028C (en) * | 2003-10-24 | 2008-02-27 | 上海宏力半导体制造有限公司 | Semiconductor resistance element and producing method thereof |
| JP5008543B2 (en) * | 2007-12-18 | 2012-08-22 | セイコーインスツル株式会社 | Semiconductor device |
| JP2010283310A (en) * | 2009-06-08 | 2010-12-16 | Panasonic Corp | Semiconductor device and manufacturing method thereof |
| JP5568334B2 (en) * | 2010-02-24 | 2014-08-06 | ラピスセミコンダクタ株式会社 | Semiconductor device and manufacturing method thereof |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102214560A (en) * | 2011-05-27 | 2011-10-12 | 上海宏力半导体制造有限公司 | Resistor structure and manufacturing method thereof |
| CN102347281A (en) * | 2011-10-28 | 2012-02-08 | 上海宏力半导体制造有限公司 | Split-gate flash memory unit and forming method thereof |
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