CN101740577A - One time programmable memory unit and operation method thereof - Google Patents
One time programmable memory unit and operation method thereof Download PDFInfo
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- CN101740577A CN101740577A CN200810171814A CN200810171814A CN101740577A CN 101740577 A CN101740577 A CN 101740577A CN 200810171814 A CN200810171814 A CN 200810171814A CN 200810171814 A CN200810171814 A CN 200810171814A CN 101740577 A CN101740577 A CN 101740577A
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Abstract
The invention relates to a one time programmable memory unit and an operation method thereof. The one time programmable memory unit comprises a grid dielectric layer, a grid electrode, a first source electrode/drain electrode, a second source electrode/drain electrode, a first self-aligned metal silicification layer, a capacitance dielectric layer, a second conducting plug and a first conducting plug, wherein the grid electrode is arranged on the grid dielectric layer; the first source electrode/drain electrode and the second source electrode/drain electrode are respectively arranged at two opposite sides below the grid electrode; the first self-aligned metal silicification layer is arranged on the first source electrode/drain electrode; the capacitance dielectric layer is arranged on the second source electrode/drain electrode; the second conducting plug is arranged on the first self-aligned metal silicification layer; the first conducting plug is arranged on the capacitance dielectric layer; and the size of the second conducting plug is different from that of the first conducting plug.
Description
Technical field
The present invention relates to a kind of semiconductor element, particularly relate to a kind of one time programmable memory unit and method of operation thereof.
Background technology
After electric current was turned off, the data that is stored in memory body the inside can disappearance person, and the memory body of this type is called non-volatility memory.In the non-volatility memory, whether can when using computer, be rewritten as standard at any time, can be divided into two big series products again according to the data in the memory body, promptly read-only memory (ReadOnly Memory, ROM) and fast flash memory bank (Flash Memory).
Since the integrated circuit invention, semi-conductor industry is flourish.Chief reason is electronic component, and (for example: size one time programmable memory unit) is more and more little, improves the aggregation density of integrated circuit, makes and can hold more electronic component by the integrated circuit per unit area.
On the other hand, the data that will store along with required by electronic product grows with each passing day, contracts in the face of under this memory body size, and under the situation that the memory body capacity needs to increase, little, the high aggregation density of manufacturing dimension how, the memory cell that can take into account its quality again is the consistent target of industry.
This shows that above-mentioned existing one time programmable memory unit obviously still has inconvenience and defective, and demands urgently further being improved in structure and use.In order to solve the problem of above-mentioned existence, relevant manufacturer there's no one who doesn't or isn't seeks solution painstakingly, but do not see always that for a long time suitable design finished by development, and common product does not have appropriate structure to address the above problem, this obviously is the problem that the anxious desire of relevant dealer solves.Therefore how to found a kind of novel one time programmable memory unit and method of operation thereof, real one of the current important research and development problem that belongs to, also becoming the current industry utmost point needs improved target.
Because the defective that above-mentioned existing one time programmable memory unit exists, the inventor is based on being engaged in this type of product design manufacturing abundant for many years practical experience and professional knowledge, and the utilization of cooperation scientific principle, actively studied innovation, in the hope of founding a kind of novel one time programmable memory unit and method of operation thereof, can improve general existing one time programmable memory unit, make it have more practicality.Through constantly research, design, and, create the present invention who has practical value finally through after studying sample and improvement repeatedly.
Summary of the invention
Main purpose of the present invention is, overcome the defective that existing one time programmable memory unit exists, and provide a kind of one time programmable memory unit of new structure, technical problem to be solved is to make its size by second conductive plunger be different from the size of first conductive plunger and the yield that promotes one time programmable memory unit in manufacturing process, is very suitable for practicality.
Another object of the present invention is to, a kind of method of operation of novel one time programmable memory unit is provided, technical problem to be solved is to make it read one time programmable memory unit effectively, thereby is suitable for practicality more.
A further object of the present invention is, a kind of one time programmable memory unit of new structure is provided, technical problem to be solved is to make its size by peripheral conductive plunger be different from the size of first conductive plunger and the yield that promotes one time programmable memory unit in manufacturing process, thereby is suitable for practicality more.
The object of the invention to solve the technical problems realizes by the following technical solutions.According to a kind of one time programmable memory unit that the present invention proposes, it comprises: a gate dielectric is disposed at one aboveground; One gate electrode is disposed on this gate dielectric; One first source/drain and one second source/drain are disposed in this well, lay respectively at relative two sides of this gate electrode below; One first self-aligned metal silicified layer is disposed on this first source/drain; One capacitance dielectric layer is disposed on this second source/drain; One first conductive plunger is disposed on this first self-aligned metal silicified layer; And one second conductive plunger, be disposed on this capacitance dielectric layer, wherein the size of this first conductive plunger is different from the size of this second conductive plunger.
The object of the invention to solve the technical problems also can be applied to the following technical measures to achieve further.
Aforesaid one time programmable memory unit, wherein said capacitance dielectric layer are to be a resistance protection oxide layer or a self-aligned metal silicified layer barrier layer.
Aforesaid one time programmable memory unit, it is disposed at the central authorities or the edge of semiconductor wafer, and wherein the size of this second conductive plunger in this one time programmable memory unit of the central authorities of this semiconductor crystal wafer is different from the size of this second conductive plunger in this one time programmable memory unit at the edge of this semiconductor crystal wafer.
Aforesaid one time programmable memory unit, it is disposed at the central authorities or the edge of a memory array, and wherein the size of this second conductive plunger in this one time programmable memory unit of the central authorities of this memory array is different from the size of this second conductive plunger in this one time programmable memory unit at the edge of this memory array.
Aforesaid one time programmable memory unit, it more comprises: one first lightly doped drain, be disposed between this first source/drain and this first self-aligned metal silicified layer, wherein the transport properties of this first lightly doped drain is opposite with the transport properties of this first source/drain; And one second lightly doped drain, be disposed between this second source/drain and the capacitance dielectric layer, wherein the transport properties of this second lightly doped drain is opposite with the transport properties of this second source/drain.
Aforesaid one time programmable memory unit, the size of the size of wherein said second conductive plunger and this first conductive plunger is the pattern that is defined on circuit design drawing or the mask.
The object of the invention to solve the technical problems also realizes by the following technical solutions.A kind of method of operation according to the present invention proposes is applicable to aforesaid one time programmable memory unit, and this method of operation comprises: bestow one first current potential to this first conductive plunger; Bestow one second current potential to this second conductive plunger; Bestow one the 3rd current potential to this gate electrode; And bestow one the 4th current potential to this well, wherein the potential difference between the 3rd current potential and the 4th current potential is that the potential difference between this first current potential and this second current potential is to be used to produce electric current in this passage in order to the passage of this gate dielectric below of conducting.
The object of the invention to solve the technical problems also can be applied to the following technical measures to achieve further.
Aforesaid method of operation, when this one time programmable memory unit is to be a N passage one time programmable memory unit, this method of operation more comprises: set this second current potential more than or equal to the 4th current potential; And set the 3rd current potential greater than the 4th current potential.
Aforesaid method of operation, when this one time programmable memory unit is to be a P passage one time programmable memory unit, this method of operation more comprises: set this second current potential and be less than or equal to the 4th current potential; And set the 3rd current potential less than the 4th current potential.
The object of the invention to solve the technical problems realizes in addition more by the following technical solutions.According to a kind of integrated circuit that the present invention proposes, it comprises at least: an one time programmable memory unit, and it comprises: a gate dielectric is disposed at one aboveground; One gate electrode is disposed on this gate dielectric; One first source/drain and one second source/drain are disposed in this well, lay respectively at relative two sides of this gate electrode below; One first self-aligned metal silicified layer is disposed on this first source/drain; One capacitance dielectric layer is disposed on this second source/drain; And one first conductive plunger, be disposed on this capacitance dielectric layer; And a periphery circuit devices, this one time programmable memory unit of electric property coupling, wherein this periphery circuit devices comprises a peripheral conductive plunger at least, and the size of this periphery conductive plunger is different from the size of this first conductive plunger.
The object of the invention to solve the technical problems also can be applied to the following technical measures to achieve further.
Aforesaid integrated circuit, it more comprises: one second conductive plunger, be disposed on this first self-aligned metal silicified layer, wherein the size of this second conductive plunger is different from the size of this first conductive plunger.
By technique scheme, one time programmable memory unit of the present invention and method of operation thereof have following advantage and beneficial effect at least:
1,,, in manufacturing process, can promote the yield of this one time programmable memory unit because the size of second conductive plunger is different from the size of first conductive plunger by one time programmable memory unit of the present invention.
2,, can read one time programmable memory unit effectively by method of operation of the present invention.
3,,, in manufacturing process, can promote the yield of this one-time programmable unit because the size of peripheral conductive plunger is different from the size of first conductive plunger by integrated circuit of the present invention.
In sum, the invention relates to a kind of one time programmable memory unit and method of operation thereof.This one time programmable memory unit, it comprises gate dielectric, gate electrode, first source/drain, second source/drain, the first self-aligned metal silicified layer, capacitance dielectric layer, second conductive plunger and first conductive plunger.This gate electrode is disposed on this gate dielectric.This first source/drain and one second source/drain lay respectively at the relative both sides of this gate electrode below.This first self-aligned metal silicified layer is disposed on this first source/drain.This capacitance dielectric layer is disposed on this second source/drain.This second conductive plunger is disposed on this first self-aligned metal silicified layer.This first conductive plunger is disposed on this capacitance dielectric layer, and wherein the size of this second conductive plunger is different from the size of this first conductive plunger.The present invention has obvious improvement technically, and has tangible good effect, really is a new and innovative, progressive, practical new design.
Above-mentioned explanation only is the general introduction of technical solution of the present invention, for can clearer understanding technological means of the present invention, and can be implemented according to the content of specification, and for above-mentioned and other purposes, feature and advantage of the present invention can be become apparent, below especially exemplified by preferred embodiment, and conjunction with figs., be described in detail as follows.
Description of drawings
Fig. 1 is the vertical view according to a kind of one time programmable memory unit of one embodiment of the invention.
Fig. 2 is the profile along 2-2 hatching among Fig. 1.
Fig. 3 is the vertical view according to the part of a kind of memory array of one embodiment of the invention.
Fig. 4 is the profile along 4-4 hatching in the one time programmable memory unit among Fig. 3 220.
Fig. 5 is the profile according to a kind of one time programmable memory unit of another embodiment of the present invention.
Fig. 6 is the profile according to a kind of one time programmable memory unit of yet another embodiment of the invention.
Fig. 7 is the block diagram according to a kind of integrated circuit of one embodiment of the invention.
100: one time programmable memory unit 110: well
112: gate dielectric 114: gate electrode
117: the second source/drains of 116: the first source/drains
121: the second liners of 120: the first liners
123: the second septs of 122: the first septs
130: the first self-aligned metal silicified layers 132: alter ego is aimed at metal silicified layer
140: 150: the first etch stop layers of capacitance dielectric layer
172: the first conductive plungers of 170: the second conductive plungers
174a: the first conductive plunger 180a, 180b, 180c: first metal wire
184a, 184b, 184c: the 3rd metal wire 200: memory array
210-260: 310: the first lightly doped drains of one time programmable memory unit
311: the second lightly doped drains
Embodiment
Reach technological means and the effect that predetermined goal of the invention is taked for further setting forth the present invention, below in conjunction with accompanying drawing and preferred embodiment, to one time programmable memory unit and its embodiment of method of operation, structure, feature and the effect thereof that foundation the present invention proposes, describe in detail as after.
Relevant aforementioned and other technology contents, characteristics and effect of the present invention can be known to present in the following detailed description that cooperates with reference to graphic preferred embodiment.By the explanation of embodiment, when can being to reach technological means that predetermined purpose takes and effect to get one more deeply and concrete understanding to the present invention, yet appended graphic only provide with reference to the usefulness of explanation, be not to be used for the present invention is limited.For convenience of description, in following embodiment, components identical is represented with identical numbering.Incoherent detail section does not show fully yet, in the hope of graphic succinct.
Please refer to Fig. 1, shown in Figure 2, Fig. 1 is the vertical view that illustrates according to a kind of one time programmable memory unit of one embodiment of the invention, and Fig. 2 is the profile that illustrates along the hatching 2-2 among Fig. 1.One time programmable memory unit 100 can comprise well 110.Among Fig. 2, well 110 is to be formed in the one time programmable memory unit 100 in order to extra isolation to be provided.Well 110 can be the N well, and it forms in substrate by implanting or spreading N type ion (for example: arsenic ion or phosphonium ion).On the contrary, well 110 can be the P well, and it is by implanting or (for example: the boron ion) form spread P type ion in substrate.In addition, substrate can comprise bulk silicon that mixed or unadulterated.Among Fig. 2, one time programmable memory unit 100 also comprises gate dielectric 112 and gate electrode 114.In the present embodiment, form and patterning grid dielectric layer 112 and gate electrode 114 on well 110, wherein gate dielectric 112 is disposed on the well 110, and gate electrode 114 is disposed on the gate dielectric 112.Gate dielectric 112 is the dielectric materials for high-k, similarly is silica, silicon oxynitride, silicon nitride, oxide, nitrogenous oxide and bond or analog material.For example can be aluminium oxide, lanthana, hafnium oxide, zirconia, nitrogen hafnium oxide or its bond about other analog materials.Relative dielectric constant that it should be noted that gate dielectric 112 can be greater than 4.On the other hand, it is good that gate electrode 114 comprises electric conducting material, similarly is polysilicon, other electric conducting materials or its bond of metal (for example: tantalum, titanium, molybdenum, tungsten, platinum, aluminium, hafnium or ruthenium), metal silicide (for example: titanium silicide, cobalt silicide, nickle silicide or tantalum silicide), metal nitride (for example: titanium nitride or tantalum nitride), doping.
Among Fig. 2, one time programmable memory unit 100 also comprises first source/drain 116 and second source/drain 117.On behalf of it, so-called " source/drain " can be source electrode or drain electrode.If first source/drain 116 is as source electrode, then second source/drain 117 is as drain electrode; On the contrary, if first source/drain 116 is as draining, then second source/drain 117 is as source electrode.In the present embodiment, first source/drain 116 and second source/drain 117 are formed in the well 110, and lay respectively at the relative both sides of gate electrode 114 belows.For instance, first source/drain 116 is positioned at the left side of gate electrode 114 belows, and second source/drain 117 is positioned at the right side of gate electrode 114 belows.In an embodiment, implantable P type ion (for example: boron ion or boron difluoride ion) is in N well 110, to form first source/drain 116 and second source/drain 117, then one time programmable memory unit 100 can be considered a kind of P passage Metal-oxide-semicondutor element.On the contrary, implantable N type ion (for example: arsenic ion or phosphonium ion) is in P well 110, and to form first source/drain 116 and second source/drain 117, then one time programmable memory unit 100 can be considered a kind of N passage Metal-oxide-semicondutor element.
Among Fig. 2, one time programmable memory unit 100 also can comprise first liner 120 and second liner 121, and wherein first liner 120 and second liner 121 are the peripheries that are disposed at along gate electrode 114.In addition, one time programmable memory unit 100 also can comprise first sept 122 and second sept 123, and wherein first sept 122 is disposed on first liner 120, and second sept 123 is disposed on second liner 121.First sept 122 and second sept 123 can be dielectric material, similarly are silica, silicon nitride and bond thereof or analog material.
Among Fig. 2, one time programmable memory unit 100 also comprises the first self-aligned metal silicified layer (salicide layer) 130, alter ego is aimed at metal silicified layer 132 and capacitance dielectric layer 140.In the present embodiment, the first self-aligned metal silicified layer 130 is disposed on first source/drain 116.Alter ego is aimed at metal silicified layer 132 and is disposed on a part of gate electrode 114, and alter ego aligning metal silicified layer 132 is also extensible in the top of first liner 120 and first sept 122.Capacitance dielectric layer 140 is disposed on the gate electrode 114 of another part, and capacitance dielectric layer 140 is also configurable in the top of second liner 121 and second sept 123.Another embodiment, capacitance dielectric layer 140 be cover part second source/drain 117 zones only, extend to form near aiming at metal silicified layer 132 by alter ego on second source/drain, 117 zones of second liner 121 and second sept 123.Capacitance dielectric layer 140 can be oxide layer (resistiveprotection oxide layer) or self-aligned metal silicified layer barrier layer (the self-alignedsilicide block layer) of resistance protection.
Among Fig. 2, one time programmable memory unit 100 also can comprise first etch stop layer 150, second etch stop layer 152 and interlayer insulating film (interlayer insulating layer) 160.In the present embodiment, first etch stop layer 150 overlies the first self-aligned metal silicified layer 130 and capacitance dielectric layer 140, second etch stop layer 152 overlies first etch stop layer 150 and aims at metal silicified layer 132 with alter ego, and interlayer insulating film 160 overlies second etch stop layer 152.
Among Fig. 2, one time programmable memory unit 100 also comprises second conductive plunger 170 and first conductive plunger 172.In the present embodiment, 170 extensions of second conductive plunger penetrate interlayer insulating film 160, second etch stop layer 152 and first etch stop layer 150, and second conductive plunger, 170 contacts, the first self-aligned metal silicified layer 130.172 extensions of first conductive plunger penetrate interlayer insulating film 160, second etch stop layer 152 and first etch stop layer 150, and first conductive plunger, 172 hand capacity dielectric layers 140.The size of second conductive plunger 170 is different from first conductive plunger 172 and is of a size of good.The size definable of the size of second conductive plunger 170 and first conductive plunger 172 or be implemented in circuit design drawing or mask on pattern.In semiconductor fabrication process, less conductive plunger means that the speed when etching perforate (opening) is slower.If the size of second conductive plunger 170 equals the size of first conductive plunger 172, then after etching process, when if second conductive plunger 170 just can contact the first self-aligned metal silicified layer 130, then first conductive plunger 172 may pass capacitance dielectric layer 140, and directly contacts second source/drain 117.Thus, in the process to one time programmable memory unit 100 sequencing, capacitance dielectric layer 140 can not produce collapse, makes sequencing fail.For the situation that prevents this class misfortune takes place, first conductive plunger 172 adopts less size, after etching process, during second conductive plunger, 170 contacts, the first self-aligned metal silicified layer 130, first conductive plunger, 172 hand capacity dielectric layers 140 or do not run through capacitance dielectric layer 140 fully, wherein do not run through under the state of capacitance dielectric layer 140 fully at first conductive plunger 172, the thickness of remaining capacitance dielectric layer 140 must be enough to smooth sequencing between first conductive plunger 172 and second source/drain 117.On the other hand, first conductive plunger 172 adopts less size, can not take additional space, can improve the aggregation density of semiconductor element.In other words, the cross-sectional area of first conductive plunger 172 should be less than the cross-sectional area of second conductive plunger 170.
In addition, about above-mentioned etching manufacturing process, in other embodiment, can form first etch stop layer 150 in the one time programmable memory unit 100, and need not to form second etch stop layer 152.
Among Fig. 2, it is configurable on the gate electrode 114 of a part that alter ego is aimed at metal silicified layer 132, and 140 of capacitance dielectric layers are disposed on the gate electrode 114 of another part.On the other hand, should be appreciated that based on the design principle of mnemon and the situation that some are possible, in other embodiment, major part can be covered by the first self-aligned metal silicified layer on first source/drain, fraction is covered by capacitance dielectric layer.On the contrary, major part can be covered by capacitance dielectric layer on first source/drain, and fraction is covered by the first self-aligned metal silicified layer.Without departing from the spirit and scope of the present invention, those skilled in the art are when looking the configuration mode that actual conditions elasticity is selected the capacitance dielectric layer and the first self-aligned metal silicified layer.
In addition, in memory array, it can comprise a plurality of one time programmable memory units 100 and peripheral logic element (peripheral logic device), and wherein the peripheral logic element electrically connects one time programmable memory unit 100.Certainly, the peripheral logic element is also configurable outside memory array.It should be noted that the size of first conductive plunger 172 of one time programmable memory unit 100 is different from the size of the conductive plunger of peripheral logic element.
In addition, in actual applications, one time programmable memory unit 100 is configurable in the central authorities or the edge of memory array.For reliability and the stability that improves manufacturing process, the size of this first conductive plunger 172 in the one time programmable memory unit 100 of the central authorities of memory array can be different from the size of first conductive plunger 172 in the one time programmable memory unit 100 at the edge of memory array.
In addition, in actual applications, one time programmable memory unit 100 is configurable in the central authorities or the edge of semiconductor crystal wafer.For reliability and the stability that improves manufacturing process, the size 172 of first conductive plunger in the one time programmable memory unit 100 of the central authorities of semiconductor crystal wafer is different from the size of first conductive plunger 172 in the one time programmable memory unit 100 at the edge of semiconductor crystal wafer.
Please continue to consult shown in Figure 2,, propose a kind of method of operation that is applicable to one time programmable memory unit 100 according to one embodiment of the invention.In this method of operation, bestow first current potential to the second conductive plunger 170, bestow second current potential to the first conductive plunger 172, bestow the 3rd current potential, and bestow the 4th current potential to well 110 to gate electrode 114.If during sequencing one time programmable memory unit 100, potential difference between the 3rd current potential and the 4th current potential need be enough to the passage of turn-on grid electrode dielectric layer 112 belows, after the passage conducting, the potential difference between second current potential and first current potential need be enough to make capacitance dielectric layer 140 collapses.
On the other hand, one time programmable memory unit 100 can be N passage one time programmable memory unit, and wherein well 110 is the P well, and first source/drain 116 and second source/drain 117 be the doped N-type ion all.If when reading N passage one time programmable memory unit 100, bestow first current potential to the second conductive plunger 170, bestow second current potential to the first conductive plunger 172, bestow the 3rd current potential to gate electrode 114, and bestow the 4th current potential to well 110.Potential difference between the 3rd current potential and the 4th current potential need be enough to the passage of turn-on grid electrode dielectric layer 112 belows, and wherein the 3rd current potential should be greater than the 4th current potential.Potential difference between first current potential and second current potential is to be used to produce electric current in this passage.If set first current potential greater than second current potential, then the current potential of first source/drain 162 is greater than the current potential of second source/drain 117, and electric current flows to second current potential by first current potential; On the contrary, if set first current potential less than second current potential, then the current potential of first source/drain 116 is less than the current potential of second source/drain 117, and electric current flows to first current potential by second current potential.In addition, can set second current potential, prevent that by this face that the connects place between the well 110 and second source/drain 117 from producing forward bias voltage drop more than or equal to the 4th current potential.Certainly, also can set first current potential, prevent that by this face that the connects place between the well 110 and first source/drain 116 from producing forward bias voltage drop more than or equal to the 4th current potential.
In addition, one time programmable memory unit 100 can be P passage one time programmable memory unit, and wherein well 110 is the N well, first source/drain 116 and the second source/drain 117 P type ion that all mixes.If when reading P passage one time programmable memory unit 100, bestow first current potential to the second conductive plunger 170, bestow second current potential to the first conductive plunger 172, bestow the 3rd current potential to gate electrode 114, and bestow the 4th current potential to well 110.Potential difference between the 3rd current potential and the 4th current potential need be enough to the passage of turn-on grid electrode dielectric layer 112 belows, and wherein the 3rd current potential should be less than the 4th current potential.Potential difference between first current potential and second current potential is to be used to produce electric current in this passage.If set first current potential greater than second current potential, then the current potential of first source/drain 1162 is greater than the current potential of second source/drain 117, and electric current flows to second current potential by first current potential; On the contrary, if set first current potential less than second current potential, then the current potential of first source/drain 116 is less than the current potential of second source/drain 117, and electric current flows to first current potential by second current potential.In addition, can set second current potential and be less than or equal to the 4th current potential, prevent that by this face that the connects place between the well 110 and second source/drain 117 from producing forward bias voltage drop.Certainly, also can set first current potential and be less than or equal to the 4th current potential, prevent that by this face that the connects place between the well 110 and first source/drain 116 from producing forward bias voltage drop.It should be noted that and to judge that according to the size of current in the passage of gate dielectric 112 belows whether one time programmable memory unit 100 is by sequencing.If one time programmable memory unit 100 is by sequencing, then the electric current in the passage is bigger; If one time programmable memory unit 100 is not by sequencing, then the electric current in the passage is less.
See also Fig. 3, shown in Figure 4, Fig. 3 is the vertical view that illustrates according to the part of a kind of memory array of one embodiment of the invention, and Fig. 4 is the profile that illustrates along the hatching 4-4 of the one time programmable memory unit among Fig. 3 220.Memory array 200 comprises a plurality of one time programmable memory units, similarly is a plurality of one time programmable memory units 210,220,230,240,250,260 among Fig. 3.Among Fig. 4, one time programmable memory unit 220 is except having added the first metal wire 180a, the second metal wire 182a, the 3rd metal wire 184a and the 3rd conductive plunger 174a, and the one time programmable memory unit 100 with above-mentioned is identical in fact.In the present embodiment, the first metal wire 180a and the second metal wire 182a all are patterned and are formed on the interlayer insulating film 160, and wherein the first metal wire 180a connects first conductive plunger, 172, the second metal wire 182a and connects second conductive plunger 170.The 3rd conductive plunger 174a connects the second metal wire 182a, and the 3rd metal wire 184a connects the 3rd conductive plunger 174a, and wherein the 3rd metal wire 184a is positioned at the top of the second metal wire 182a.In addition, a plurality of one time programmable memory units in the memory array 200, wherein each one time programmable memory unit can be similar or identical with above-mentioned one time programmable memory unit 220, but the arrangement position difference of each one time programmable memory unit in memory array 200.
Among Fig. 3, one time programmable memory unit 210,220,230 all is electrically connected to the first metal wire 180a; Similarly, one time programmable memory unit 240,250,260 all is electrically connected to the first metal wire 180c.In memory array 200, each bar first metal wire all can be perpendicular to each article the 3rd metal wire, and each bar first metal wire all can be parallel to each gate electrode.In the present embodiment, the first metal wire 180a, 180b, 180c also are parallel to gate electrode 114 perpendicular to the 3rd metal wire 184a, 184b, 184c.It should be noted that per two one time programmable memory units can shared same the 3rd conductive plunger, by this, can increase the aggregation density of memory array.In the present embodiment, two one time programmable memory units, 220,250 shared the 3rd conductive plunger 174a; Two one time programmable memory units, 210,240 shared the 3rd conductive plunger 174b; Two one time programmable memory units, 230,260 shared the 3rd conductive plunger 174c.
Please continue to consult Fig. 3, shown in Figure 4,, propose a kind of method of operation that is applicable to memory array 200 according to another embodiment of the present invention.Under this method of operation, each bar first metal wire 180a, 180b, 180c can be used as the one source pole line in memory array 200, and each article the 3rd metal wire 184a, 184b, 184c can be used as a selection wire.
In the present embodiment, if the one time programmable memory unit 220 in the sequencing memory array 200.Then bestow first current potential to the, three metal wire 184a, bestow second current potential to the first metal wire 180a, bestow the gate electrode 114 of the 3rd current potential, and bestow the 4th current potential to well 110 to one time programmable memory unit 220.It should be noted that first current potential can equal the 4th current potential, the potential difference between the 3rd current potential and the 4th current potential need be enough to the passage of turn-on grid electrode dielectric layer 112 belows, and wherein the potential difference between the 3rd current potential and the 4th current potential for example can be about 1.5 volts.After the passage conducting, the potential difference between second current potential and first current potential need be enough to make capacitance dielectric layer 140 collapses, and wherein the potential difference between second current potential and first current potential for example can be about 6 volts.
On the other hand, as if arbitrary one time programmable memory unit, then the 3rd metal wire of this one time programmable memory unit of suspension joint in the not sequencing memory array 200; First metal wire of this one time programmable memory unit of suspension joint, or bestow second current potential to the first metal wire, wherein this second current potential is identical with second current potential that is administered to the first metal wire 180a when the sequencing; Bestow the gate electrode 114 of the 5th current potential to one time programmable memory unit 220, wherein this 5th current potential is different from the 3rd current potential of the gate electrode 114 that is imparted to one time programmable memory unit 220 when sequencing; And bestow with the 4th identical when sequencing current potential to well.For instance, above-mentioned the 3rd current potential and the potential difference between the 4th current potential for example can be about 1.5 volts, and the potential difference between the 5th current potential and the 4th current potential for example can be about 0 volt.
In addition, as if the one time programmable memory unit 220 that reads in the memory array 200.Then bestow first current potential to the, three metal wire 184a, bestow second current potential to the first metal wire 180a, bestow the gate electrode 114 of the 3rd current potential, and bestow the 4th current potential to well 110 to one time programmable memory unit 220.It should be noted that the potential difference between the 3rd current potential and the 4th current potential need be enough to the passage of turn-on grid electrode dielectric layer 112 belows, wherein the potential difference between the 3rd current potential and the 4th current potential for example can be about 1.5 volts.Potential difference system between first current potential and second current potential is used to produce electric current in this passage, and wherein the potential difference between first current potential and second current potential for example can be about 1.5 volts.
Furthermore, one time programmable memory unit 220 can be N passage one time programmable memory unit, and wherein well 110 is the P well, and first source/drain 116 and second source/drain 117 be the doped N-type ion all.If when reading N passage one time programmable memory unit 100, bestow first current potential to the, three metal wire 184a, bestow second current potential to the first metal wire 180a, bestow the gate electrode 114 of the 3rd current potential, and bestow the 4th current potential to well 110 to one time programmable memory unit 220.It should be noted that the potential difference between the 3rd current potential and the 4th current potential need be enough to the passage of turn-on grid electrode dielectric layer 112 belows, wherein the 3rd current potential should be greater than the 4th current potential.Potential difference system between first current potential and second current potential is used to produce electric current in this passage.If set first current potential greater than second current potential, then the current potential of first source/drain 1162 is greater than the current potential of second source/drain 117, and electric current flows to second current potential by first current potential; On the contrary, if set first current potential less than second current potential, then the current potential of first source/drain 116 is less than the current potential of second source/drain 117, and electric current flows to first current potential by second current potential.In addition, can set second current potential, prevent that by this face that the connects place between the well 110 and second source/drain 117 from producing forward bias voltage drop more than or equal to the 4th current potential.Certainly, also can set first current potential, prevent that by this face that the connects place between the well 110 and first source/drain 116 from producing forward bias voltage drop more than or equal to the 4th current potential.
On the other hand, one time programmable memory unit 100 can be P passage one time programmable memory unit, and wherein well 110 is the N well, first source/drain 116 and the second source/drain 117 P type ion that all mixes.If when reading P passage one time programmable memory unit 100, bestow first current potential to the, three metal wire 184a, bestow second current potential to the first metal wire 180a, bestow the gate electrode 114 of the 3rd current potential, and bestow the 4th current potential to well 110 to one time programmable memory unit 220.It should be noted that the potential difference between the 3rd current potential and the 4th current potential need be enough to the passage of turn-on grid electrode dielectric layer 112 belows, wherein the 3rd current potential should be less than the 4th current potential.Potential difference between first current potential and second current potential is to be used to produce electric current in this passage.If set first current potential greater than second current potential, then the current potential of first source/drain 1162 is greater than the current potential of second source/drain 117, and electric current flows to second current potential by first current potential; On the contrary, if set first current potential less than second current potential, then the current potential of first source/drain 116 is less than the current potential of second source/drain 117, and electric current flows to first current potential by second current potential.In addition, can set second current potential and be less than or equal to the 4th current potential, prevent that by this face that the connects place between the well 110 and second source/drain 117 from producing forward bias voltage drop.Certainly, also can set first current potential and be less than or equal to the 4th current potential, prevent that by this face that the connects place between the well 110 and first source/drain 116 from producing forward bias voltage drop.
In addition, if do not read arbitrary one time programmable memory unit in the memory array 200, then the 3rd metal wire of this one time programmable memory unit of suspension joint; First metal wire of this one time programmable memory unit of suspension joint, or bestow second current potential to the first metal wire, wherein this second current potential is identical with second current potential that is administered to the first metal wire 180a when reading; Bestow the gate electrode 114 of the 5th current potential to one time programmable memory unit 220, wherein this 5th current potential is different from the 3rd current potential of the gate electrode 114 that is imparted to one time programmable memory unit 220 when reading; And bestow with the 4th identical when reading current potential to well.For instance, above-mentioned the 3rd current potential and the potential difference between the 4th current potential for example can be about 1.5 volts, and the potential difference between the 5th current potential and the 4th current potential for example can be about 0 volt.
See also shown in Figure 5ly, it is the profile that illustrates according to a kind of one time programmable memory unit of another embodiment of the present invention.Comparison diagram 2, Fig. 5, among Fig. 5, one time programmable memory unit 300 adds first lightly doped drain (lightly-doped drain between the first self-aligned metal silicified layer 130 and first source/drain 116, LDD) 310, and between the capacitance dielectric layer 140 and second source/drain 117, add second lightly doped drain 311, in addition, one time programmable memory unit 300 is just the same with the one time programmable memory unit 100 among Fig. 2 in fact.In manufacture process, first lightly doped drain 310 and second lightly doped drain, 311 implantable N type ions or P type ion.In addition, carrying out the annealing manufacturing process, similarly is that (rapid thermal anneal, RTA) manufacturing process can be used to activate the ion of being implanted in first lightly doped drain 310 and second lightly doped drain 311 in short annealing.Among Fig. 3, first lightly doped drain 310 is disposed on first source/drain 116, and the first self-aligned metal silicified layer 130 is disposed on first lightly doped drain 310.Second lightly doped drain 311 is disposed on second source/drain 117, and capacitance dielectric layer 140 is disposed on second lightly doped drain 311.Transport properties that it should be noted that first lightly doped drain 310 can be opposite with the transport properties of first source/drain 116; The transport properties of second lightly doped drain 311 can be opposite with the transport properties of second source/drain 117.By this, the combination of first lightly doped drain 310 and first source/drain 116 can have the characteristic of diode; The combination of second lightly doped drain 311 and second source/drain 117 can have the characteristic of diode.In actual applications, this equivalent diode can prevent backward current.
See also shown in Figure 6ly, it is the profile that illustrates according to a kind of one time programmable memory unit of yet another embodiment of the invention.Comparison diagram 2, Fig. 6, among Fig. 6, one time programmable memory unit 400 has lacked second conductive plunger 170, and in addition, one time programmable memory unit 300 is just the same with the one time programmable memory unit 100 among Fig. 2 in fact.
In practical application, can adopt diffusion (diffusion) mechanism of first source/drain 116, replace second conductive plunger 170 originally; In other words, in Fig. 2, being electrically connected to first source/drain 116 by second conductive plunger 170, and in Fig. 6, then is to be used as conductor by first source/drain 116 itself, and the external world directly bestows voltage and is electrically connected on first source/drain 116.The diffusion region of adopting first source/drain 116 is when the conduction body, the cellar area that can dwindle one time programmable memory unit 100 on the one hand is (because lacked second conductive plunger, 170 zones, can reduce the width of the diffusion region of first source/drain 116), come again to reduce because second conductive plunger 170 causes yield problem (as loose contact etc.).
See also shown in Figure 7ly, it is the block diagram that illustrates according to a kind of integrated circuit of one embodiment of the invention.Among Fig. 7, integrated circuit 500 comprises one time programmable memory unit 600 and peripheral circuit device 700 at least.In the present embodiment, one time programmable memory unit 600 and periphery circuit devices 700 electric property couplings.One time programmable memory unit 600 can be above-mentioned one time programmable memory unit 100,300,400.Periphery circuit devices 700 comprises peripheral conductive plunger 710.It should be noted that the size of peripheral conductive plunger 710 is different from the size of the first above-mentioned conductive plunger 172.Owing under these two kinds of different blocks different conductive plunger sizes is arranged, therefore, can design one time programmable memory unit 100 make be different from general conductive plunger 710 size (generally speaking, wafer manufacturer only provides fixing conductive plunger size usually), so, can make performance and yield optimization at one time programmable memory unit 100, and need not be subject to fixing conductive plunger, its objective is to have the highest yield output.
Generally speaking, the size of the peripheral conductive plunger 710 of periphery circuit devices 700 is the design rules (design rule) of following integrated circuit.Peripheral unit 700 can comprise at least electronic switch, logic input/output unit and passive device one of them.
The above, it only is preferred embodiment of the present invention, be not that the present invention is done any pro forma restriction, though the present invention discloses as above with preferred embodiment, yet be not in order to limit the present invention, any those skilled in the art, in not breaking away from the technical solution of the present invention scope, when the technology contents that can utilize above-mentioned announcement is made a little change or is modified to the equivalent embodiment of equivalent variations, in every case be the content that does not break away from technical solution of the present invention, according to technical spirit of the present invention to any simple modification that above embodiment did, equivalent variations and modification all still belong in the scope of technical solution of the present invention.
Claims (11)
1. one time programmable memory unit is characterized in that it comprises:
One gate dielectric is disposed at one aboveground;
One gate electrode is disposed on this gate dielectric;
One first source/drain and one second source/drain are disposed in this well, lay respectively at relative two sides of this gate electrode below;
One first self-aligned metal silicified layer is disposed on this first source/drain;
One capacitance dielectric layer is disposed on this second source/drain;
One first conductive plunger is disposed on this first self-aligned metal silicified layer; And
One second conductive plunger is disposed on this capacitance dielectric layer, and wherein the size of this first conductive plunger is different from the size of this second conductive plunger.
2. one time programmable memory unit according to claim 1 is characterized in that wherein said capacitance dielectric layer is to be a resistance protection oxide layer or a self-aligned metal silicified layer barrier layer.
3. one time programmable memory unit according to claim 1, it is characterized in that, it is disposed at the central authorities or the edge of semiconductor wafer, and wherein the size of this second conductive plunger in this one time programmable memory unit of the central authorities of this semiconductor crystal wafer is different from the size of this second conductive plunger in this one time programmable memory unit at the edge of this semiconductor crystal wafer.
4. one time programmable memory unit according to claim 1, it is characterized in that, it is disposed at the central authorities or the edge of a memory array, and wherein the size of this second conductive plunger in this one time programmable memory unit of the central authorities of this memory array is different from the size of this second conductive plunger in this one time programmable memory unit at the edge of this memory array.
5. one time programmable memory unit according to claim 1 is characterized in that it more comprises:
One first lightly doped drain is disposed between this first source/drain and this first self-aligned metal silicified layer, and wherein the transport properties of this first lightly doped drain is opposite with the transport properties of this first source/drain; And
One second lightly doped drain is disposed between this second source/drain and the capacitance dielectric layer, and wherein the transport properties of this second lightly doped drain is opposite with the transport properties of this second source/drain.
6. one time programmable memory unit according to claim 1 is characterized in that the size of wherein said second conductive plunger and the size of this first conductive plunger are the patterns that is defined on circuit design drawing or the mask.
7. a method of operation is applicable to one time programmable memory unit as claimed in claim 1, it is characterized in that this method of operation comprises:
Bestow one first current potential to this first conductive plunger;
Bestow one second current potential to this second conductive plunger;
Bestow one the 3rd current potential to this gate electrode; And
Bestow one the 4th current potential to this well, wherein the potential difference between the 3rd current potential and the 4th current potential is that the potential difference between this first current potential and this second current potential is to be used to produce electric current in this passage in order to the passage of this gate dielectric below of conducting.
8. method of operation according to claim 7 is characterized in that, when this one time programmable memory unit is to be a N passage one time programmable memory unit, this method of operation more comprises:
Set this second current potential more than or equal to the 4th current potential; And
Set the 3rd current potential greater than the 4th current potential.
9. method of operation according to claim 7 is characterized in that, when this one time programmable memory unit is to be a P passage one time programmable memory unit, this method of operation more comprises:
Set this second current potential and be less than or equal to the 4th current potential; And
Set the 3rd current potential less than the 4th current potential.
10. integrated circuit is characterized in that it comprises at least:
One one time programmable memory unit, it comprises:
One gate dielectric is disposed at one aboveground;
One gate electrode is disposed on this gate dielectric;
One first source/drain and one second source/drain are disposed in this well, lay respectively at relative two sides of this gate electrode below;
One first self-aligned metal silicified layer is disposed on this first source/drain;
One capacitance dielectric layer is disposed on this second source/drain; And
One first conductive plunger is disposed on this capacitance dielectric layer; And
One periphery circuit devices, this one time programmable memory unit of electric property coupling, wherein this periphery circuit devices comprises a peripheral conductive plunger at least, and the size of this periphery conductive plunger is different from the size of this first conductive plunger.
11. integrated circuit according to claim 10 is characterized in that it more comprises:
One second conductive plunger is disposed on this first self-aligned metal silicified layer, and wherein the size of this second conductive plunger is different from the size of this first conductive plunger.
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| CN200810171814A CN101740577A (en) | 2008-11-12 | 2008-11-12 | One time programmable memory unit and operation method thereof |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN102522408A (en) * | 2011-12-22 | 2012-06-27 | 上海宏力半导体制造有限公司 | One-time programmable memory and manufacturing method |
| CN106972052A (en) * | 2015-12-31 | 2017-07-21 | 台湾积体电路制造股份有限公司 | Semiconductor structure and its manufacture method |
| CN108735760A (en) * | 2017-04-25 | 2018-11-02 | 三星电子株式会社 | three-dimensional semiconductor memory device |
| CN111430329A (en) * | 2020-04-23 | 2020-07-17 | 合肥晶合集成电路有限公司 | Capacitive semiconductor element |
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2008
- 2008-11-12 CN CN200810171814A patent/CN101740577A/en active Pending
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN102522408A (en) * | 2011-12-22 | 2012-06-27 | 上海宏力半导体制造有限公司 | One-time programmable memory and manufacturing method |
| CN102522408B (en) * | 2011-12-22 | 2016-06-08 | 上海华虹宏力半导体制造有限公司 | Disposable programmable memory and manufacture method |
| CN106972052A (en) * | 2015-12-31 | 2017-07-21 | 台湾积体电路制造股份有限公司 | Semiconductor structure and its manufacture method |
| US20180337240A1 (en) * | 2015-12-31 | 2018-11-22 | Taiwan Semiconductor Manufacturing Company Ltd. | Semiconductor structure and associated fabricating method |
| US10964789B2 (en) | 2015-12-31 | 2021-03-30 | Taiwan Semiconductor Manufacturing Company Ltd. | Method of fabricating a semiconductor structure having at least one recess |
| US11855158B2 (en) | 2015-12-31 | 2023-12-26 | Taiwan Semiconductor Manufacturing Company Ltd. | Semiconductor device structure having a gate structure and overlying dielectric layer |
| CN108735760A (en) * | 2017-04-25 | 2018-11-02 | 三星电子株式会社 | three-dimensional semiconductor memory device |
| CN108735760B (en) * | 2017-04-25 | 2023-10-13 | 三星电子株式会社 | Three-dimensional semiconductor memory device |
| CN111430329A (en) * | 2020-04-23 | 2020-07-17 | 合肥晶合集成电路有限公司 | Capacitive semiconductor element |
| CN111430329B (en) * | 2020-04-23 | 2021-07-27 | 合肥晶合集成电路股份有限公司 | Capacitive semiconductor element |
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