CN103296004B - A kind of antifuse element and manufacture method thereof - Google Patents
A kind of antifuse element and manufacture method thereof Download PDFInfo
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- CN103296004B CN103296004B CN201210041696.3A CN201210041696A CN103296004B CN 103296004 B CN103296004 B CN 103296004B CN 201210041696 A CN201210041696 A CN 201210041696A CN 103296004 B CN103296004 B CN 103296004B
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Abstract
The present invention provides a kind of antifuse element and manufacture method thereof, and described antifuse element includes: be formed at the grid structure in Semiconductor substrate, and described grid structure includes the gate dielectric and the gate material layers that stack gradually from bottom to top; It is formed at the bag-shaped injection region of the n-type lightly doped drain region in the described Semiconductor substrate that the both sides of described grid structure expose and doped indium. Described Semiconductor substrate and gate material layers respectively constitute two terminal electrodes of described antifuse element. By adjusting the size that the Implantation Energy of described doped indium can control the breakdown voltage of described gate dielectric.
Description
Technical field
The present invention relates to semiconductor fabrication process, in particular to a kind of antifuse element and manufacture method thereof.
Background technology
Antifuse is a kind of element conventional in semiconductor device, and it is widely used in programmable integrated circuit (IC). In specific PLD (PLD), for instance structured application-specific integrated circuits (ASIC), antifuse is used for constituting logic circuit therein, and creates the customizable method for designing from standard IC design. In programmable read only memory, every bit lines comprises fuse and antifuse, is programmed operation by triggering one in fuse and antifuse, and described programming is permanent and irreversible.
The original state of antifuse is non-conduction and has very big impedance, and when the voltage putting on it exceedes certain level, it creates the current path of a permanent conduction. In the semiconductor device, a kind of typical structure of antifuse is to configure a thin barrier layer between the electrode that two metallic conductors are constituted, the material on described barrier layer is generally non-conduction non-crystalline silicon, when a sufficiently large voltage puts on antifuse, described amorphous silicon is polysilicon, and constitutes the alloy body having Low ESR and can turning on together with described metallic conductor; The another kind of typical structure of antifuse is the alloy body that tungsten, titanium and silicon are constituted.
But, above two antifuse all contains metal level, when a bigger electric current flows through described metal level, very easily produces ELECTROMIGRATION PHENOMENON, make antifuse can not generation effect under predetermined duty, thus affecting its reliability.
It is, therefore, desirable to provide a kind of antifuse element and manufacture method thereof, to solve the problems referred to above.
Summary of the invention
For the deficiencies in the prior art, the present invention provides the manufacture method of a kind of antifuse element, including: providing Semiconductor substrate, be formed with grid structure on the semiconductor substrate, described grid structure includes the gate dielectric and the gate material layers that stack gradually from bottom to top; The described Semiconductor substrate that the both sides of described grid structure expose is formed the bag-shaped injection region of a n-type lightly doped drain region and a doped indium.
Further, described Semiconductor substrate and gate material layers respectively constitute two terminal electrodes of described antifuse element.
Further, in original state, described Semiconductor substrate and described gate material layers are kept apart by described gate dielectric, and described antifuse element is in nonconducting state.
Further, when applying a predetermined voltage between described Semiconductor substrate and gate material layers, described gate dielectric is breakdown, and described antifuse element is in the conduction state.
Further, the size of described predetermined voltage can be controlled by adjusting the Implantation Energy of described doped indium.
Further, described predetermined voltage is the breakdown voltage of described gate dielectric.
Further, ion implantation technology is adopted to form the bag-shaped injection region of described doped indium.
Further, the Implantation Energy of described ion implanting is 50-80keV.
Further, described gate dielectric is oxide skin(coating).
Further, described gate material layers is polysilicon layer.
Further, described grid structure linear arrangement, square arrangement or serpentine arrangement on the semiconductor substrate.
The present invention also provides for a kind of antifuse element, including: being formed at the grid structure in Semiconductor substrate, described grid structure includes the gate dielectric and the gate material layers that stack gradually from bottom to top; It is formed at the bag-shaped injection region of the n-type lightly doped drain region in the described Semiconductor substrate that the both sides of described grid structure expose and doped indium.
Further, described Semiconductor substrate and gate material layers respectively constitute two terminal electrodes of described antifuse element.
Further, in original state, described Semiconductor substrate and described gate material layers are kept apart by described gate dielectric, and described antifuse element is in nonconducting state.
Further, when applying a predetermined voltage between described Semiconductor substrate and gate material layers, described gate dielectric is breakdown, and described antifuse element is in the conduction state.
Further, the size of described predetermined voltage can be controlled by adjusting the Implantation Energy of described doped indium.
Further, described predetermined voltage is the breakdown voltage of described gate dielectric.
Further, described gate dielectric is oxide skin(coating).
Further, described gate material layers is polysilicon layer.
Further, described grid structure linear arrangement, square arrangement or serpentine arrangement on the semiconductor substrate
According to the present invention it is possible to improve the reliability of antifuse element, simultaneously can according to the predetermined voltage required when needing to control antifuse element work of different semiconductor device.
Accompanying drawing explanation
The drawings below of the present invention is used for understanding the present invention in this as the part of the present invention. Shown in the drawings of embodiments of the invention and description thereof, it is used for explaining principles of the invention.
In accompanying drawing:
Figure 1A-Fig. 1 D is the schematic cross sectional view of each step of the manufacture method of the antifuse element that the present invention proposes;
Fig. 2 is the cumulative distribution figure of the breakdown voltage of the gate dielectric in the antifuse element that the present invention proposes.
Detailed description of the invention
In the following description, a large amount of concrete details is given to provide more thorough understanding of the invention. It is, however, obvious to a person skilled in the art that the present invention can be carried out without these details one or more. In other example, in order to avoid obscuring with the present invention, technical characteristics more well known in the art are not described.
In order to thoroughly understand the present invention, detailed step will be proposed in following description, in order to the antifuse element of explaination present invention proposition and manufacture method thereof. Obviously, the execution of the present invention is not limited to the specific details that the technical staff of semiconductor applications has the knack of. Presently preferred embodiments of the present invention is described in detail as follows, but except these detailed descriptions, the present invention can also have other embodiments.
Should be understood that, when using term " comprising " and/or " including " in this manual, it indicates exists described feature, entirety, step, operation, element and/or assembly, but does not preclude the presence or addition of other features one or more, entirety, step, operation, element, assembly and/or their combination.
Below, the detailed step of the manufacture method of the antifuse element that the present invention proposes is described with reference to Figure 1A-Fig. 1 D.
With reference to Figure 1A-Fig. 1 D, illustrated therein is the schematic cross sectional view of each step of the manufacture method of the antifuse element that the present invention proposes.
First, as shown in Figure 1A, it is provided that Semiconductor substrate 100, the constituent material of described Semiconductor substrate 100 can adopt unadulterated monocrystal silicon, doped with the monocrystal silicon of impurity, silicon-on-insulator (SOI) etc. Exemplarily, in the present embodiment, Semiconductor substrate 100 selects single crystal silicon material to constitute. Being formed with isolation structure 101 in Semiconductor substrate 100, described isolation structure 101 isolates (STI) structure or selective oxidation silicon (LOCOS) isolation structure for shallow trench. Exemplarily, in the present embodiment, described isolation structure 101 isolates (STI) structure for shallow trench. The technique forming described isolation structure 101 is had the knack of by those skilled in the art, does not repeat them here.
Being formed with grid structure in described Semiconductor substrate 100, as an example, described grid structure can include the gate dielectric 102 and the gate material layers 103 that stack gradually from bottom to top. Described gate dielectric 102 can include oxide, e.g., and silicon dioxide (SiO2) layer. Described gate material layers 103 can include one or more in polysilicon layer, metal level, conductive metal nitride layer, conductive metal oxide layer and metal silicide layer, wherein, the constituent material of metal level can be tungsten (W), nickel (Ni) or titanium (Ti); Conductive metal nitride layer can include titanium nitride (TiN) layer; Conductive metal oxide layer can include yttrium oxide (IrO2) layer; Metal silicide layer can include titanium silicide (TiSi) layer. In the present embodiment, described gate dielectric 102 is oxide skin(coating), and described gate material layers 103 is polysilicon layer. The technique forming described grid structure is had the knack of by those skilled in the art, does not repeat them here.
Then, as shown in Figure 1B, the Semiconductor substrate 100 that the both sides of described grid structure expose forms a n-type lightly doped drain region 104. It follows that form a heavy doping drain region 105 on the side in n-type lightly doped drain region 104, its formation process can adopt the formation process of the source/drain region of common MOS transistor.
Then, as shown in Figure 1 C, adopt ion implantation technology in a bag-shaped injection region 106 formed below in described n-type lightly doped drain region 104. The element adulterated in described bag-shaped injection region 106 is indium, and Implantation Energy is 50-80keV.
Then, as shown in figure ip, described quasiconductor 100 and gate material layers 103 form contact plug (not shown). It follows that form interconnecting channel 107, its lower end is connected with described contact plug, and upper end is connected with metal interconnecting wires.
Described Semiconductor substrate 100 and gate material layers 103 respectively constitute two terminal electrodes of the antifuse element that the present invention proposes. In original state, Semiconductor substrate 100 and gate material layers 103 are kept apart by described gate dielectric 102, and described antifuse element is in nonconducting state; When applying a predetermined voltage between described Semiconductor substrate 100 and gate material layers 103, described gate dielectric 102 is breakdown, and described antifuse element is in the conduction state. Meanwhile, the breakdown voltage of gate dielectric 102 in described antifuse element, i.e. described predetermined voltage can be controlled by the bag-shaped injection region 106 of described doped indium. As in figure 2 it is shown, the breakdown voltage Vbd that the abscissa in figure is described gate dielectric 102, vertical coordinate is the Cumulative Distribution Function CDF of described breakdown voltage; Implantation Energy when forming the bag-shaped injection region 106 of described doped indium is more high, and described breakdown voltage is more little, and the cumulative distribution of described breakdown voltage more keeps left.
The manufacturing process of the antifuse element that the invention described above proposes is completely compatible with traditional process for fabricating semiconductor device, it is not necessary to increase extra technique, such that it is able to save manufacturing cost. According to the present invention it is possible to improve the reliability of antifuse element, simultaneously can according to the predetermined voltage required when needing to control antifuse element work of different semiconductor device.
In the described antifuse element shown by Fig. 1 D, described Semiconductor substrate 100 only illustrates a grid structure. In the layout-design of integrated circuit, described grid structure can present difform arrangement, for instance linear array, square arrangement or serpentine arrangement. By this kind of distribution design, when manufacturing the antifuse element that the present invention proposes, it is possible to make full use of the area of silicon chip, improve the integrated level of the integrated circuit (IC) comprising described antifuse element.
The present invention is illustrated already by above-described embodiment, but it is to be understood that, above-described embodiment is only intended to citing and descriptive purpose, and is not intended to limit the invention in described scope of embodiments. In addition it will be appreciated by persons skilled in the art that and the invention is not limited in above-described embodiment, more kinds of variants and modifications can also be made according to the teachings of the present invention, within these variants and modifications all fall within present invention scope required for protection. Protection scope of the present invention is defined by the appended claims and equivalent scope thereof.
Claims (16)
1. a manufacture method for antifuse element, including:
Thering is provided Semiconductor substrate, be formed with grid structure on the semiconductor substrate, described grid structure includes the gate dielectric and the gate material layers that stack gradually from bottom to top;
The described Semiconductor substrate that the both sides of described grid structure expose is formed the bag-shaped injection region of a n-type lightly doped drain region and a doped indium, when applying a predetermined voltage between described Semiconductor substrate and gate material layers, described gate dielectric is breakdown, described antifuse element is in the conduction state, can control the size of described predetermined voltage by adjusting the Implantation Energy of described doped indium.
2. method according to claim 1, it is characterised in that described Semiconductor substrate and gate material layers respectively constitute two terminal electrodes of described antifuse element.
3. method according to claim 1, it is characterised in that in original state, described Semiconductor substrate and described gate material layers are kept apart by described gate dielectric, and described antifuse element is in nonconducting state.
4. method according to claim 1, it is characterised in that described predetermined voltage is the breakdown voltage of described gate dielectric.
5. method according to claim 1, it is characterised in that adopt ion implantation technology to form the bag-shaped injection region of described doped indium.
6. method according to claim 5, it is characterised in that the Implantation Energy of described ion implanting is 50-80keV.
7. method according to claim 1, it is characterised in that described gate dielectric is oxide skin(coating).
8. method according to claim 1, it is characterised in that described gate material layers is polysilicon layer.
9. method according to claim 1, it is characterised in that described grid structure is linear arrangement, square arrangement or serpentine arrangement on the semiconductor substrate.
10. an antifuse element, including:
Being formed at the grid structure in Semiconductor substrate, described grid structure includes the gate dielectric and the gate material layers that stack gradually from bottom to top;
It is formed at the bag-shaped injection region of the n-type lightly doped drain region in the described Semiconductor substrate that the both sides of described grid structure expose and doped indium, when applying a predetermined voltage between described Semiconductor substrate and gate material layers, described gate dielectric is breakdown, described antifuse element is in the conduction state, can control the size of described predetermined voltage by adjusting the Implantation Energy of described doped indium.
11. antifuse element according to claim 10, it is characterised in that described Semiconductor substrate and gate material layers respectively constitute two terminal electrodes of described antifuse element.
12. antifuse element according to claim 10, it is characterised in that in original state, described Semiconductor substrate and described gate material layers are kept apart by described gate dielectric, and described antifuse element is in nonconducting state.
13. antifuse element according to claim 10, it is characterised in that described predetermined voltage is the breakdown voltage of described gate dielectric.
14. antifuse element according to claim 10, it is characterised in that described gate dielectric is oxide skin(coating).
15. antifuse element according to claim 10, it is characterised in that described gate material layers is polysilicon layer.
16. antifuse element according to claim 10, it is characterised in that described grid structure is linear arrangement, square arrangement or serpentine arrangement on the semiconductor substrate.
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| CN201210041696.3A CN103296004B (en) | 2012-02-23 | 2012-02-23 | A kind of antifuse element and manufacture method thereof |
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| CN110739293A (en) * | 2018-07-20 | 2020-01-31 | 无锡华润微电子有限公司 | sub-programmable cell and semiconductor device integrated with sub-programmable cell |
| CN111987150B (en) * | 2019-05-23 | 2024-06-21 | 长鑫存储技术有限公司 | Semiconductor structure, manufacturing method thereof and memory |
| CN111987100B (en) * | 2019-05-23 | 2024-06-21 | 长鑫存储技术有限公司 | Semiconductor structure, manufacturing method thereof and memory |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN101043027A (en) * | 2006-03-23 | 2007-09-26 | 联华电子股份有限公司 | Anti-fuse and stylization method thereof |
| CN101145575A (en) * | 2006-09-15 | 2008-03-19 | 应用智慧有限公司 | Non-volatile memory unit and array |
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| JP2011119640A (en) * | 2009-11-06 | 2011-06-16 | Renesas Electronics Corp | Semiconductor device, and method of manufacturing the same |
| US9224496B2 (en) * | 2010-08-11 | 2015-12-29 | Shine C. Chung | Circuit and system of aggregated area anti-fuse in CMOS processes |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN101043027A (en) * | 2006-03-23 | 2007-09-26 | 联华电子股份有限公司 | Anti-fuse and stylization method thereof |
| CN101145575A (en) * | 2006-09-15 | 2008-03-19 | 应用智慧有限公司 | Non-volatile memory unit and array |
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