CN102931227B - Power semiconductor device structure and preparation method on passivation semiconductor contact surface - Google Patents
Power semiconductor device structure and preparation method on passivation semiconductor contact surface Download PDFInfo
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Abstract
The invention relates to a power semiconductor device structure on a passivation semiconductor contact surface. The power semiconductor device structure comprises a first conduction type drift region, a second conduction type base region is arranged inside the first conduction type drift region, a first conduction type emitter region is arranged inside the second conduction type base region, and a gate oxide arranged in the front of the first conduction type drift region is provided with polycrystalline gates. An emitter arranged on the second conduction type base region contacts to the second conduction type base region and the first conduction type drift region arranged inside the second conduction type base region, and the gate oxide is provided with gate electrodes. The second conduction type collector region is formed on the back surface of the first conduction type drift region, a first current collection metal region is deposited on the back surface of the first conduction type drift region, and a second current collection metal region is deposited on the first current collection metal region. The power semiconductor device structure is characterized in that the first current collection metal region is a metal film formed by Se in deposited mode. The power semiconductor device structure achieves semiconductor surface passivation, and avoids current limiting effects caused by oversize self-resistance.
Description
Technical field
The present invention relates to a kind of semiconductor device and manufacture method thereof, especially a kind of power semiconductor device structure of passivated semiconductor contact surface and preparation method, belong to IGBT technical field.
Background technology
IGBT is that the initial of insulated gate bipolar transistor is called for short, and is a kind of voltage-controlled type power device, is generally applied as high-voltage switch gear.
In the IGBT preparation technology of routine, be first front technique, comprise the PN junction in the formation fronts such as oxidation, ion implantation, exposure, deposit and etching, gate electrode and emitter pattern; Then be the reduction process at the back side and the ion implantation at the back side.The conventional IGBT back side is all the doping of P type, and some device back side doping content is very low, if to do the conducting resistance that can make device well too large for contact resistance, affects the performance of device.Most characteristic of semiconductor device and the surface nature of semiconductor have close relationship, and even skin effect can play a leading role to semiconductor device characteristic, in order to improve device surface performance, sometimes needs to make Passivation Treatment to device surface.For Metals-semiconductor contacts, the Passivation Treatment of semiconductor surface can the schottky barrier height of adjustment interface, to obtain desirable ohm property.But at present, the passivation of semiconductor surface realizes mainly through the method for dielectric layer deposited, and due to the electrical insulation characteristic of dielectric layer, in order to really reduce the contact resistance of interface, the thickness of dielectric layer should not be excessive, and this has certain difficulty in technique.VI race element superthin layer passivated semiconductor surface is utilized will fundamentally to solve this difficult problem.Adopt the method for MBE extension (molecular beam epitaxy) or sputtering at the ultra-thin Se of Si superficial growth, effectively can eliminate Fermi's pinning effect of contact interface, realize passivation.Introduce S and Se superthin layer at metal-semiconductor interface, while realizing semiconductor surface passivation, avoiding the current limit effect caused because self-resistance is excessive, is the effective way realizing ohmic contact.
In patent US20100327314, propose a kind of Ge/Al that adopts as the method for IGBT collector electrode, in that patent, after grinding overleaf and corroding, deposit one deck Ge film and Al film, then at 300 DEG C to 450 DEG C temperature, annealing makes Al be diffused in Ge as p type impurity.The scope of the doping content of Al in Ge is 1018 – 1021/cm
3.This method can reduce the difficulty of preparation, and improves the switching characteristic of IGBT.The method is owing to needing the etching of back metal, if can erode to the metal in front with wet etching, so can only use the method for dry etching, higher to technological requirement.
Summary of the invention
The object of the invention is to overcome the deficiencies in the prior art, a kind of power semiconductor device structure and preparation method of passivated semiconductor contact surface is provided, achieves semiconductor surface passivation, avoid the current limit effect caused because self-resistance is excessive.
According to technical scheme provided by the invention, a kind of power semiconductor device structure of passivated semiconductor contact surface, on the cross section of described semiconductor device, comprise the first conduction type drift region, the first conduction type drift region has the front and back be parallel to each other; The second conduction type base region is provided with in described first conduction type drift region, second conduction type base region is rearwardly extended in direction by the front of the first conduction type drift region, and the extended distance of the second conduction type base region is less than the thickness of the first conduction type drift region; Be provided with the first conduction type emitter region in described second conduction type base region, the first conduction type emitter region is positioned at the top of the second conduction type base region, and the first conduction type emitter region is rearwardly extended in direction by the front of the first conduction type drift region; The second conduction type base region in described first conduction type drift region by the gate oxide be positioned on the first front, conduction type drift region and the first conduction type drift region be positioned at below gate oxide isolated; Described gate oxide is positioned at the center in the first front, conduction type drift region, contacts respectively with the second conduction type base region of both sides, and contacts with the first conduction type emitter region adjacent in the conduction type base region of both sides second; Described gate oxide is provided with polysilicon gate, and the shape of polysilicon gate is consistent with the shape of gate oxide; Described second conduction type base region is positioned at the outer ring in the first front center district, conduction type drift region, and the second conduction type base region is around polysilicon gate and gate oxide; Described second conduction type base region is provided with emitter, and emitter contacts with the first conduction type emitter region in the second conduction type base region and this second conduction type base region, and polysilicon gate is provided with gate electrode; Inject the second conductive type ion at the back side of described first conduction type drift region and form the second conduction type collector region, the first current collection metal area is deposited with at the back side of described first conduction type drift region, the one side of the first current collection metal area covers the back side of the first conduction type drift region, and the another side of the first current collection metal area is deposited with the second current collection metal area; Feature is: described first current collection metal area is the metallic film formed by Se deposit.
Described first current collection metal area is monoatomic layer structure.
The thickness of described first current collection metal area is 0.5nm.
The concentration of described first conduction type emitter region is greater than the concentration of the first conduction type drift region.
The concentration of described second conduction type collector region is greater than the concentration of the second conduction type base region.
Described emitter and gate electrode do not contact.
Described second current collection metal area is Al/Ti/Ni/Ag multiple layer metal.
The thickness of described gate oxide is 1000.
The preparation method of the power semiconductor device structure of passivated semiconductor contact surface of the present invention, feature is, adopts following manufacturing process:
(1) the first conductive type semiconductor substrate with front and back is provided, be the first conduction type drift region between the front and the back side of the first conductive type semiconductor substrate, grow into one deck gate oxide at the front dry-oxygen oxidation of the first conduction type drift region;
(2) in low temperature boiler tube, grow one deck polycrystal layer in the upper surface of gate oxide and utilize photoetching corrosion to go out gate shapes, obtain the gate oxide being positioned at the first conduction type drift region front center and the polysilicon gate be positioned on gate oxide, the shape of polysilicon gate is consistent with the shape of gate oxide;
(3) the front of the first conduction type drift region, around the region of polysilicon gate and gate oxide in autoregistration inject the second conductive type ion, and carry out thermal diffusion, obtain the second conduction type base region; Described second conduction type base region is rearwardly extended in direction by the front of the first conduction type drift region, and the extended distance of the second conduction type base region is less than the thickness of the first conduction type drift region, on cross section, gate oxide contacts with the second conduction type base region of both sides;
(4) the injection window of the first conduction type emitter region is carved at the front lighting of the first conduction type drift region, then injection first conductive type ion is carried out, in the second conduction type base region, the first conduction type emitter region is formed after annealing, the concentration of the first conduction type emitter region is greater than the concentration of the first conduction type drift region, on cross section, gate oxide contacts with the first conduction type emitter region adjacent in the second conduction type base region of adjacent both sides;
(5) metal connecting line making is carried out in the front of above-mentioned first conduction type drift region, first at the Al that front deposit one deck 4 μm of the first conduction type drift region is thick, then the line pattern of Al is eroded away with lithography corrosion process, polysilicon gate forms gate electrode, second conduction type base region forms emitter, emitter contacts with the first conduction type emitter region in the second conduction type base region and this second conduction type base region, and emitter and gate electrode do not contact;
(6) back side of above-mentioned first conduction type drift region is carried out being thinned to desired thickness, then inject the second conductive type ion at the back side of the first conduction type drift region, obtain the second conduction type collector region; Then the back side extension in the first conduction type drift region or sputtering one deck Se metallic film, obtain the first current collection metal area;
(7) the outer surface evaporation in the first current collection metal area forms Al/Ti/Ni/Ag multiple layer metal, obtains the second current collection metal area; Finally annealing in process is carried out at the back side of the first conduction type drift region.
The present invention has the following advantages: semiconductor device structure of the present invention introduces Se film between current collection metal area and the back side of semiconductor substrate, while realizing semiconductor surface passivation, avoiding the current limit effect caused because self-resistance is excessive, is the effective way realizing ohmic contact.
Accompanying drawing explanation
Fig. 1 is structure cutaway view of the present invention.
Fig. 2 ~ Fig. 8 is that the concrete technology of manufacture method of the present invention implements cutaway view, wherein:
Fig. 2 is the structure cutaway view after obtaining gate oxide.
Fig. 3 is the structure cutaway view after obtaining polysilicon gate.
Fig. 4 is the structure cutaway view after obtaining the second conduction type base region.
Fig. 5 is the structure cutaway view after obtaining the first conduction type emitter region.
Fig. 6 is the structure cutaway view after obtaining emitter and gate electrode.
Fig. 7 is the structure cutaway view obtaining the second conduction type collector region and the first current collection metal area.
Fig. 8 is the structure cutaway view obtaining the second current collection metal area.
Embodiment
Below in conjunction with concrete accompanying drawing, the invention will be further described.
As shown in Fig. 1 ~ Fig. 8: for N-type IGBT device, the present invention includes N-drift region 1, gate oxide 2, polysilicon gate 3, emitter 4, gate electrode 5, P type base 6, current collection metal area 9, current collection metal area 8, second, N+ emitter region 7, first, P+ collector region 10.
As shown in Fig. 1, Fig. 8, on the cross section of described IGBT device, semiconductor substrate comprises drift region, N-drift region 1, N-1 and has the front and back be parallel to each other; Be provided with type base, P type base 6, P 6 in described N-drift region 1 rearwardly to be extended in direction by the front of N-drift region 1, and the extended distance of P type base 6 is less than the thickness of N-drift region 1; Be provided with the top that emitter region, N+ emitter region 7, N+ 7 is positioned at P type base 6 in described P type base 6, N+ emitter region 7 is rearwardly extended in direction by the front of N-drift region 1, and the concentration of N+ emitter region 7 is greater than the concentration of N-drift region 1; P type base 6 in described N-drift region 1 by the gate oxide 2 be positioned on front, N-drift region 1 and the N-drift region 1 be positioned at below gate oxide 2 isolated; Described gate oxide 2 is positioned at the center in front, N-drift region 1, contacts respectively with the P type base 6 of both sides, and contacts with N+ emitter region 7 adjacent in P type base, both sides 6; Described gate oxide 2 is provided with polysilicon gate 3, and the shape of polysilicon gate 3 is consistent with the shape of gate oxide 2; Described P type base 6 is positioned at the outer ring in front center district, N-drift region 1, and P type base 6 is around polysilicon gate 3 and gate oxide 2; Described P type base 6 is provided with emitter 4, and emitter 4 contacts with the N+ emitter region 7 in P type base 6 and this P type base 6, and polysilicon gate 3 is provided with gate electrode 5, and emitter 4 and gate electrode 5 do not contact; The concentration injecting B ion formation collector region, P+ collector region 10, P+ 10 at the back side of described N-drift region 1 is greater than the concentration of P type base 6; The one side being deposited with the first current collection metal area 8, current collection metal area 8, first at the back side of described N-drift region 1 covers the back side of N-drift region 1, the another side of the first current collection metal area 8 is deposited with the second current collection metal area 9;
Described first current collection metal area 8 is the metallic films formed by Se deposit; Described second current collection metal area 9 is Al/Ti/Ni/Ag multiple layer metal; The present invention adopts Se material as the material of the first current collection metal area 8 at the back side, N-drift region 1, Se film is introduced between the Si of Al and the N-drift region 1 of the second current collection metal area 9, while realizing semiconductor surface passivation, avoid the current limit effect caused because self-resistance is excessive, it is the effective way realizing ohmic contact, Passivation Treatment can be carried out to the Si surface at the back side, N-drift region 1, thus the schottky barrier height of adjustment interface, obtain desirable ohm property;
The thickness of described gate oxide 2 is 1000.
As shown in Fig. 2 ~ Fig. 8, the manufacture process of the IGBT device of said structure is as follows:
(1) as shown in Figure 2, the N type semiconductor substrate 11 with front and back is provided, be N-drift region 1 between the front and the back side of N type semiconductor substrate 11, grow into the gate oxide 2 of a layer thickness 1000 at the front dry-oxygen oxidation of N-drift region 1, gate oxide 2 is very fine and close oxide layers;
(2) as shown in Figure 3, in low temperature boiler tube, grow one deck polycrystal layer in the upper surface of gate oxide 2 and utilize photoetching corrosion to go out gate shapes, obtain the gate oxide 2 being positioned at N-drift region 1 front center and the polysilicon gate 3 be positioned on gate oxide 2, the shape of polysilicon gate 3 is consistent with the shape of gate oxide 2;
(3) as shown in Figure 4, in the front in N-drift region 1, the region around polysilicon gate 3 and gate oxide 2, B ion is injected in autoregistration, and carries out thermal diffusion, obtains P type base 6; Described P type base 6 is rearwardly extended in direction by the front of N-drift region 1, and the extended distance of P type base 6 is less than the thickness of N-drift region 1, and on cross section, gate oxide 2 contacts with the P type base 6 of both sides;
(4) as shown in Figure 5, the injection window of N+ emitter region 7 is carved at the front lighting of N-drift region 1, then high concentration As ion implantation is carried out, in P type base 6, N+ emitter region 7 is formed after annealing, the concentration of N+ emitter region 7 is greater than the concentration of N-drift region 1, on cross section, gate oxide 2 contacts with N+ emitter region 7 adjacent in the P type base 6 of adjacent both sides;
(5) as shown in Figure 6, metal connecting line making is carried out in the front of above-mentioned N-drift region 1, first at the Al that front deposit one deck 4 μm of N-drift region 1 is thick, then the line pattern of Al is eroded away with lithography corrosion process, polysilicon gate 3 is formed gate electrode 5, P type base 6 forms emitter 4, and emitter 4 contacts with the N+ emitter region 7 in P type base 6 and this P type base 6, and emitter 4 and gate electrode 5 do not contact;
(6) as shown in Figure 7, the back side of above-mentioned N-drift region 1 is carried out being thinned to desired thickness, then inject B ion at the back side of N-drift region 1, obtain P+ collector region 10; Then the back side extension in N-drift region 1 or sputtering one deck Se metallic film, obtain the first current collection metal area 8; Described first current collection metal area 8 will be done get over Bao Yuehao, for monoatomic layer structure, thickness is approximately 0.5nm, cost can fall too low, and the method for molecular beam epitaxy can be adopted when low temperature about 300 degree, overcoming IGBT can not again through the problem of high-temperature technology after doing the front metal that is over;
(7) as shown in Figure 8, the outer surface evaporation in the first current collection metal area 8 forms Al/Ti/Ni/Ag multiple layer metal, obtains the second current collection metal area 9; Finally annealing in process is carried out at the back side of N-drift region 1.
Claims (6)
1. a power semiconductor device structure for passivated semiconductor contact surface, on the cross section of described semiconductor device, comprise the first conduction type drift region, the first conduction type drift region has the front and back be parallel to each other; The second conduction type base region is provided with in described first conduction type drift region, second conduction type base region is rearwardly extended in direction by the front of the first conduction type drift region, and the extended distance of the second conduction type base region is less than the thickness of the first conduction type drift region; Be provided with the first conduction type emitter region in described second conduction type base region, the first conduction type emitter region is positioned at the top of the second conduction type base region, and the first conduction type emitter region is rearwardly extended in direction by the front of the first conduction type drift region; The second conduction type base region in described first conduction type drift region by the gate oxide be positioned on the first front, conduction type drift region and the first conduction type drift region be positioned at below gate oxide isolated; Described gate oxide is positioned at the center in the first front, conduction type drift region, contacts respectively with the second conduction type base region of both sides, and contacts with the first conduction type emitter region adjacent in the conduction type base region of both sides second; Described gate oxide is provided with polysilicon gate, and the shape of polysilicon gate is consistent with the shape of gate oxide; Described second conduction type base region is positioned at the outer ring in the first front center district, conduction type drift region, and the second conduction type base region is around polysilicon gate and gate oxide; Described second conduction type base region is provided with emitter, and emitter contacts with the first conduction type emitter region in the second conduction type base region and this second conduction type base region, and polysilicon gate is provided with gate electrode; Inject the second conductive type ion at the back side of described first conduction type drift region and form the second conduction type collector region, the first current collection metal area is deposited with at the back side of described first conduction type drift region, the one side of the first current collection metal area covers the back side of the first conduction type drift region, and the another side of the first current collection metal area is deposited with the second current collection metal area; It is characterized in that: described first current collection metal area is the metallic film formed by Se deposit;
The concentration of described first conduction type emitter region is greater than the concentration of the first conduction type drift region;
The concentration of described second conduction type collector region is greater than the concentration of the second conduction type base region;
Described emitter and gate electrode do not contact.
2. the power semiconductor device structure of passivated semiconductor contact surface as claimed in claim 1, is characterized in that: described first current collection metal area is monoatomic layer structure.
3. the power semiconductor device structure of passivated semiconductor contact surface as claimed in claim 1, is characterized in that: the thickness of described first current collection metal area is 0.5nm.
4. the power semiconductor device structure of passivated semiconductor contact surface as claimed in claim 1, is characterized in that: described second current collection metal area is Al/Ti/Ni/Ag multiple layer metal.
5. the power semiconductor device structure of passivated semiconductor contact surface as claimed in claim 1, is characterized in that: the thickness of described gate oxide is 1000.
6. a preparation method for the power semiconductor device structure of passivated semiconductor contact surface, is characterized in that, adopts following manufacturing process:
(1) the first conductive type semiconductor substrate with front and back is provided, be the first conduction type drift region between the front and the back side of the first conductive type semiconductor substrate, grow into one deck gate oxide at the front dry-oxygen oxidation of the first conduction type drift region;
(2) in low temperature boiler tube, grow one deck polycrystal layer in the upper surface of gate oxide and utilize photoetching corrosion to go out gate shapes, obtain the gate oxide being positioned at the first conduction type drift region front center and the polysilicon gate be positioned on gate oxide, the shape of polysilicon gate is consistent with the shape of gate oxide;
(3) the front of the first conduction type drift region, around the region of polysilicon gate and gate oxide in autoregistration inject the second conductive type ion, and carry out thermal diffusion, obtain the second conduction type base region; Described second conduction type base region is rearwardly extended in direction by the front of the first conduction type drift region, and the extended distance of the second conduction type base region is less than the thickness of the first conduction type drift region, on cross section, gate oxide contacts with the second conduction type base region of both sides;
(4) the injection window of the first conduction type emitter region is carved at the front lighting of the first conduction type drift region, then injection first conductive type ion is carried out, in the second conduction type base region, the first conduction type emitter region is formed after annealing, the concentration of the first conduction type emitter region is greater than the concentration of the first conduction type drift region, on cross section, gate oxide contacts with the first conduction type emitter region adjacent in the second conduction type base region of adjacent both sides;
(5) metal connecting line making is carried out in the front of above-mentioned first conduction type drift region, first at the Al that front deposit one deck 4 μm of the first conduction type drift region is thick, then the line pattern of Al is eroded away with lithography corrosion process, polysilicon gate forms gate electrode, second conduction type base region forms emitter, emitter contacts with the first conduction type emitter region in the second conduction type base region and this second conduction type base region, and emitter and gate electrode do not contact;
(6) back side of above-mentioned first conduction type drift region is carried out being thinned to desired thickness, then inject the second conductive type ion at the back side of the first conduction type drift region, obtain the second conduction type collector region; Then the back side extension in the first conduction type drift region or sputtering one deck Se metallic film, obtain the first current collection metal area;
(7) the outer surface evaporation in the first current collection metal area forms Al/Ti/Ni/Ag multiple layer metal, obtains the second current collection metal area; Finally annealing in process is carried out at the back side of the first conduction type drift region;
The concentration of described second conduction type collector region is greater than the concentration of the second conduction type base region.
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