CN102915951B - The manufacture method of connecting hole - Google Patents
The manufacture method of connecting hole Download PDFInfo
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- CN102915951B CN102915951B CN201110221369.1A CN201110221369A CN102915951B CN 102915951 B CN102915951 B CN 102915951B CN 201110221369 A CN201110221369 A CN 201110221369A CN 102915951 B CN102915951 B CN 102915951B
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- connecting hole
- manufacture method
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Abstract
The present invention discloses the manufacture method of a kind of connecting hole, comprises the steps: to provide semiconductor base, described semiconductor base is formed layer to be etched；Etch described layer to be etched, form connecting hole；Clean described connecting hole；Barrier layer in described connecting hole；Described cleaning step starts timing while completing；If the time of timing reaches predetermined value, and not yet start the step of described barrier layer, described connecting hole is cleaned again.Cleaning connecting hole again after time-out, the by-product produced in etch step capable of washing, so that resistance value is relatively low, it is ensured that the electric conductivity of connecting hole.
Description
[technical field]
The present invention relates to a kind of semiconductor fabrication process, particularly relate to the manufacture method of a kind of connecting hole.
[background technology]
In the backend process of chip manufacturing, the preparation of connecting hole is one requisite step, connecting hole
Effect mainly double layer of metal connecting line layer is coupled together.Connecting hole is deposited to starting from having cleaned connecting hole
There is one period of waiting time on interior barrier layer, and there is the restriction of predetermined value the waiting time.Owing to predetermined value typically only has
Several hours, therefore often occur that the actual waiting time exceedes the situation of predetermined value.In this case, if
The most effectively processing, the by-product produced the when that etching forming connecting hole is easy to absorb in air
Steam, thus it is bad to cause the barrier layer in follow-up connecting hole to be filled, and connecting hole resistance so can be caused inclined
Height, affects the yield of product.Fig. 1 be the actual waiting time exceed predetermined value after two labels that are not handled by
The yield figure of sheet, being as can be seen from Figure 1 positioned at the chip in the middle part of wafer is bad chip, it is impossible to normal work
Make.
[summary of the invention]
It is an object of the invention to provide the manufacture method of a kind of connecting hole, it improves the yield of chip.
For achieving the above object, the present invention adopts the following technical scheme that the manufacture method of a kind of connecting hole, bag
Include following steps: semiconductor base is provided, described semiconductor base is formed with layer to be etched；Etching is described
Layer to be etched, form connecting hole；Clean described connecting hole；Barrier layer in described connecting hole；Described
Cleaning step starts timing while completing；If the time of timing reaches predetermined value, and not yet starts described
The step of barrier layer, cleans described connecting hole again.
In a preferred embodiment, the time used by described cleaning step again is less than used by described cleaning step
Time.
In a preferred embodiment, the time used by described cleaning step again is five minutes.
In a preferred embodiment, the time used by described cleaning step is 30 minutes.
In a preferred embodiment, described cleaning again uses EKC solution.
In a preferred embodiment, described cleaning uses EKC solution.
After time-out, connecting hole is cleaned again, the by-product produced in etch step capable of washing, so that
Resistance value is relatively low, it is ensured that the electric conductivity of connecting hole.
[accompanying drawing explanation]
Fig. 1 be the actual waiting time exceed predetermined value after the yield figure of two panels chip that is not handled by；
Fig. 2 is the yield figure of the two panels chip after the present embodiment method processes.
[detailed description of the invention]
The manufacture method of the connecting hole of the present embodiment comprises the steps: to provide semiconductor base, semiconductor-based
It is formed with layer to be etched at the end；Etch layer to be etched, form connecting hole；Clean connecting hole；In connecting hole
Barrier layer.The step main wash cleaning connecting hole etches the by-product produced in step layer to be etched,
So so that the resistance value of connecting hole is less.
General cleaning step is accomplished to start barrier layer step and has one period of waiting time, and the waiting time has
The restriction of predetermined value, the predetermined value according to the different waiting time of chip fabrication technique is different.During actual wait
Between not less than predetermined value time, the yield of chip is higher, and this predetermined value can be obtained by experiment.In the present embodiment,
Cleaning step starts timing while completing, and the time of timing is the actual waiting time；If the time of timing
Reach predetermined value, and not yet start the step of barrier layer, connecting hole is cleaned again.Clean again
The above-mentioned cleaning step of step main wash does not cleans and etches the by-product produced in step layer to be etched completely
Thing, this by-product easily absorbs the steam in air, the steam during by-product absorbs air in the waiting time,
Through again cleaning the steam of removable by-product and absorption thereof, so that the resistance value of connecting hole is less,
Ensure the electric conductivity of connecting hole.
The time of cleaning step is without oversize again, and the cleaning of short time i.e. can reach the effect above.Clean step again
The rapid time used is less than the time used by described cleaning step.The general time used by cleaning step is 30
Minute.Draw through overtesting, then the time used by cleaning step be five minutes, test prove five minutes time
Between more appropriate, cleaning performance is preferable.So, the shortest and production capacity is high.
In the present embodiment, clean and use EKC solution, then cleaning is also adopted by EKC solution.EKC solution is
Purchased from EKC Technology, the solution of Inc., Hayward, CA.EKC solution be an amine be main divesting
Agent (amine-based stripper), is mainly and azanol, organic solvent, suppression caustic and water composition, energy
Enough removing etches the by-product etc. produced in step layer to be etched.So, cost is relatively low.
Fig. 2 is the actual waiting time to exceed predetermined value, the yield figure of the two panels chip after cleaning step again.
Comparison diagram 1 and Fig. 2, it can be seen that the yield of the chip of Fig. 2 is higher, the chip on the wafer of Fig. 2 is substantially
Good chip.The most visible, the method effect of the present embodiment is obvious.
Embodiment described above only have expressed the several embodiments of the present invention, and it describes more concrete and detailed,
But therefore can not be interpreted as the restriction to the scope of the claims of the present invention.It should be pointed out that, for this area
Those of ordinary skill for, without departing from the inventive concept of the premise, it is also possible to make some deformation and
Improving, these broadly fall into protection scope of the present invention.Therefore, the protection domain of patent of the present invention should be with appended
Claim is as the criterion.
Claims (4)
1. a manufacture method for connecting hole, comprises the steps:
Semiconductor base is provided, described semiconductor base is formed layer to be etched；
Etch described layer to be etched, form connecting hole；
Clean described connecting hole；
Barrier layer in described connecting hole；
It is characterized in that: described cleaning step starts timing while completing；If the time of timing reaches predetermined
Value, and not yet start the step of described barrier layer, cleans described connecting hole again, described again
Clean and use EKC solution, then clean the time used less than the time used by described cleaning step.
The manufacture method of connecting hole the most according to claim 1, it is characterised in that: described clean step again
The rapid time used is five minutes.
The manufacture method of connecting hole the most according to claim 1 and 2, it is characterised in that: described cleaning
Time used by step is 30 minutes.
The manufacture method of connecting hole the most according to claim 1, it is characterised in that: described cleaning uses
EKC solution.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201110221369.1A CN102915951B (en) | 2011-08-03 | 2011-08-03 | The manufacture method of connecting hole |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201110221369.1A CN102915951B (en) | 2011-08-03 | 2011-08-03 | The manufacture method of connecting hole |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN102915951A CN102915951A (en) | 2013-02-06 |
| CN102915951B true CN102915951B (en) | 2016-09-21 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201110221369.1A Active CN102915951B (en) | 2011-08-03 | 2011-08-03 | The manufacture method of connecting hole |
Country Status (1)
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| CN (1) | CN102915951B (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104091758B (en) * | 2014-07-25 | 2017-03-15 | 上海华力微电子有限公司 | A kind of method for improving crystal column surface microenvironment after via etch |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2008235778A (en) * | 2007-03-23 | 2008-10-02 | Matsushita Electric Ind Co Ltd | Production process of semiconductor device |
| CN100578731C (en) * | 2007-08-21 | 2010-01-06 | 联华电子股份有限公司 | Method for cleaning semiconductor substrate |
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2011
- 2011-08-03 CN CN201110221369.1A patent/CN102915951B/en active Active
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| CN102915951A (en) | 2013-02-06 |
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