CN100578731C - Method for cleaning semiconductor substrate - Google Patents
Method for cleaning semiconductor substrate Download PDFInfo
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- CN100578731C CN100578731C CN200710141772A CN200710141772A CN100578731C CN 100578731 C CN100578731 C CN 100578731C CN 200710141772 A CN200710141772 A CN 200710141772A CN 200710141772 A CN200710141772 A CN 200710141772A CN 100578731 C CN100578731 C CN 100578731C
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Abstract
The invention discloses a method of cleaning a semiconductor base. Firstly, a semiconductor base is provided, wherein the semiconductor base comprises a material layer and a patterned photoetching rubber layer; the patterned photoetching rubber layer is positioned above the material layer; then the patterned photoetching rubber layer serves as an etching mask to conduct the contact etching process for the material layer so as to form etch holes on the material layer; a cleaning solvent is utilized to conduct the cleaning process for the semiconductor base; and finally, de-ionized water is utilized to conduct the washing process for the semiconductor base, wherein the temperature range of the de-ionized water is between 30 DEG C and 99 DEG C.
Description
Technical field
The invention provides a kind of cleaning method, refer to a kind of cleaning method that utilizes washing process to come the clean semiconductor substrate especially.
Background technology
In the manufacture process of semiconductor integrated circuit, often use pattern formation and design transfer that gold-tinted and etch process carry out layers of material on the wafer.For instance, when making the contact plunger of integrated circuit, promptly with the patterning photoresist layer as etch hard mask, with after not being patterned dielectric materials layer etching that photoresist layer covers and removing, again the patterning photoresist layer is removed, then in the connector hole, form desired metal material layer again, to finish contact plunger.
See also Fig. 1, what it illustrated is the schematic flow sheet that known method forms connector, and known method includes the following step:
Step 101: wafer is provided earlier, includes dielectric materials layer on the wafer;
Step 103: on dielectric materials layer, form photoresist layer, and photoresist layer is carried out gold-tinted technology, so that predetermined pattern is projected on the photoresist layer;
Step 105: the photoresist layer that will not be exposed is removed, and stays next patterning photoresist layer on wafer;
Step 107: wafer is carried out etch process, plasma dry etch technology or reactive ion etching (reactive ion etching normally, RIE) technology, with the design transfer of patterning photoresist layer to the dielectric materials layer of below, in dielectric materials layer, to form required connector hole;
Step 109: carry out the oxygen gas plasma cineration technics, to remove the patterning photoresist layer;
Step 111: carry out solvent clean technology (solvent cleaning process), utilize the high temperature cleaning solvent, for example 70 ℃ azanol class (hydroxylamine) solvent is removed the sidewall macromolecule and the residue that are positioned at dielectric material laminar surface, connector hole inwall and connector hole bottom;
Step 113: utilize 25 ℃ deionized water (deionized water, DI water) further to remove sidewall macromolecule and the cleaning solvent that is positioned on the dielectric materials layer;
Step 115: form one deck barrier layer in wafer surface, be covered in dielectric material laminar surface, connector hole inwall and connector hole bottom;
Step 117: form the layer of metal layer in wafer surface, be covered on the barrier layer, and be filled in the connector hole; And
Step 119: carry out grinding technics,, in dielectric materials layer, form connector thus to remove unnecessary barrier layer and unnecessary metal level.
Its plasma composition of aforesaid plasma dry etch or reactive ion etching technique can produce the various etch byproducts that is difficult to remove with organic substance in the photoresist layer, its constituent may come from material layer, photoresist layer and the etching gas on etched base material, the base material.These etch byproducts also may change to some extent along with different etching machines, process conditions and different etched material, and industry just is difficult to these be called the sidewall macromolecule with the etch byproducts that the oxygen gas plasma cineration technics is disposed.
The cleanliness factor of wafer surface is in fact very huge for the influence of finished product rate, be not affected in order to ensure follow-up finished product rate, before deposited barrier layer, these etch byproducts must be removed from wafer surface effectively, but but must not have influence on metallic circuit or the semiconductor device that has formed simultaneously.Therefore, after the oxygen gas plasma cineration technics, wafer can be sent in the semiconductor wet chem workstation cleaning of the cleaning fluid of accepting aforementioned 70 ℃ of azanol kind solvents etc., then accepts the cleaning of 25 ℃ of deionized waters, carries out subsequent technique afterwards again.
Yet when these wafers were accepted final finished product rate test, the finished product rate that test result demonstrates but still may be not as expection.According to the result of finished product rate test as can be known, even under identical technological parameter, operate, still may have different finished product rates by the handled wafer of different boards or the wafer of the handled different batches of identical board.For instance, may have more fault of construction by the handled wafer of specific board.Along with semiconductor technology enters highdensity deep-submicron from generation to generation, it is more remarkable that different situation takes place the finished product rate, and these faults of construction tend to occur in the crystal edge chip on every side.
Through finding after the experiment repeatedly, rate of finished products just is cleaning solvent residual of solvent clean technology not as the main cause of expection.Solvent clean technology itself belongs to a kind of open technology, that is to say, volatilizable one-tenth branch in the cleaning solvent is loss and going out gradually in the process of cleaning, make the viscosity of cleaning solvent itself improve gradually, the concentration of cleaning solvent also slowly changes, and the various accessory substances that are suspended in the cleaning solvent are also more and more.Therefore, long more when the process time of solvent clean technology, cleaning solvent also is difficult to remove with wafer surface with regard to easier being attached in the connector hole.But residual cleaning solvent often can't see through wafer acceptance test (wafer acceptance testing immediately, WAT) or the tangent plane of structure observe and be detected, but the existence of cleaning solvent can destroy being electrically connected between the device of metal level and below, cause the junction resistance value of the metal level inserted and its below device excessive or be electrically connected inefficacy, residual cleaning solvent even may have influence on subsequent technique or the structure of follow-up formation.
Hold,, then can be positioned at metal level bottom the connector hole because of deionized water and solvent action and then corrosion if the long-time deionized water that uses is to sweep off residual solvent.So in order to reduce the residual of cleaning solvent, the board that the finished product rate is lower must be accelerated the replacing frequency of its cleaning solvent.That is to say that the situation excessive for fear of cleaning solvent viscosity takes place, the replacement cycle of cleaning solvent must shorten, and the cycle of changing cleaning solvent by original per 12 hours changes per cleaning solvent that will more renew in 8 hours into.This not only can increase the cost of process time and cleaning solvent, and also quite limited for the improvement of finished product rate.
In view of this, known method not only may be produced the wafer of low rate of finished products, but also can waste huge technology cost and time, treats improved place so the clean method of known wafer still has.
Summary of the invention
Therefore, the present invention utilizes the deionized water of high temperature to residue in the suprabasil solvent of semiconductor to remove than the short process time, to promote the finished product rate in this cleaning method that a kind of semiconductor-based end is provided.
According to a preferred embodiment of the present invention, the invention provides the cleaning method at a kind of semiconductor-based end.At first, provide the semiconductor-based end, the semiconductor-based end, include material layer and patterning photoresist layer, and the patterning photoresist layer is positioned on the material layer.Afterwards, utilize the patterning photoresist layer to come etched material layer, in material layer, to form the etching hole as etching mask.Then, utilize cleaning solvent that solvent clean technology (solvent cleaning process) is carried out in the semiconductor substrate.Thereafter utilize deionized water that washing process is carried out in the semiconductor substrate, wherein the temperature range of deionized water is between 30 ℃ to 99 ℃, and reaction time range is between 30 seconds to 5 minutes.
According to another preferred embodiment of the invention, the present invention provides the cleaning method at a kind of semiconductor-based end in addition.At first, provide the semiconductor-based end, the semiconductor-based end, include material layer.Afterwards, utilize cleaning solvent that solvent clean technology is carried out in semiconductor substrate and material layer, wherein cleaning solvent includes the azanol constituents.Then, utilize deionized water that washing process is carried out in the semiconductor substrate, wherein the temperature range of deionized water is between 30 ℃ to 99 ℃, and reaction time range is between 30 seconds to 5 minutes.
For above-mentioned purpose of the present invention, feature and advantage can be become apparent, better embodiment cited below particularly, and conjunction with figs. are described in detail below.Yet following preferred implementation and graphic only for reference and explanation usefulness are not to be used for to the present invention's limitr in addition.
Description of drawings
What Fig. 1 illustrated is the schematic flow sheet that known method forms connector.
What Fig. 2,3,4,5,6,7 and 8 illustrated is the generalized section of the cleaning method at the semiconductor-based end of the preferred embodiments of the present invention.
What Fig. 9 illustrated is the schematic flow sheet that the preferred embodiments of the present invention are cleaned the semiconductor-based end.
Description of reference numerals
101,103,105,107,109 steps 111,113,115,117,119 steps
120 dielectric materials layers of the semiconductor-based ends 112
114 patterning photoresist layers, 122 etching holes
124 barrier layers, 126 conductive layers
128 connectors, 130 soaking compartments
132 feed-lines, 140 cleaning solvents
142 deionized waters, 144 sidewall macromolecules
146 conductors, 201,203,205,207,209 steps
211,213,215 steps
Embodiment
Please refer to Fig. 2 to Fig. 9, what Fig. 2 to Fig. 8 illustrated is the generalized section of the cleaning method at the semiconductor-based end of the preferred embodiments of the present invention, and Fig. 9 illustrates is the schematic flow sheet that the preferred embodiments of the present invention are cleaned the semiconductor-based end, and wherein components identical or position are still continued to use identical symbol and represented.Be noted that graphic only for the purpose of description, do not map according to life size.
At first, shown in the step 201 of Fig. 2 and Fig. 9, provide the semiconductor-based end 120 earlier, include conductor 146, dielectric materials layer 112 and patterning photoresist layer 114 at semiconductor-based the end 120.Wherein know as the right institute of ordinary skill person, in the time will utilizing photoresist to carry out pattern formation with design transfer, usually need earlier photoresist liquid to be coated on predetermined material surface, after being projected to image on the photoresist layer via gold-tinted technology, remove through the photoresist layer that toasts and development step will not be exposed again, use forming aforesaid patterning photoresist layer 114.Generally speaking, the semiconductor-based end 120 can be by silicon base, contain silicon base or silicon-coated insulated (Silicon-on-Insulator SOI) waits semi-conducting material to constitute, and for example is wafer.Dielectric materials layer 112 can be made of oxide or the insulating material such as silica that are mixed with boron, phosphorus.Patterning photoresist layer 114 can include positive photoetching rubber material or negative photoresist material.Conductor 146 can be the conductive region in any conductive materials or the semiconductor device, for example grid of the drain region of the source region of metallic circuit, conductive plunger, metal oxide semiconductor transistor, metal oxide semiconductor transistor, metal oxide semiconductor transistor, or the join domain of diode element or the like.Be noted that in other embodiments of the invention, aforementioned dielectric materials layer 112 is also replaceable to be other non-dielectric materials layers, for example film of aluminum metal layer or aluminium alloy passivation layer etc.
Then, shown in the step 203 of Fig. 3 and Fig. 9, etch process is carried out in semiconductor substrate 120, for example plasma etch process or reactive ion etching process etc., with the design transfer of patterning photoresist layer 114 to the dielectric materials layer 112 of below, in dielectric materials layer 112, to form required etching hole 122, for example contact plunger hole (contact plug hole), interlayer connector hole (via plug hole) or trench (trench) pattern, and expose conductor 146.
Afterwards, shown in the step 205 of Fig. 4 and Fig. 9, utilization divests (striping) technology and removes patterning photoresist layer 114, for example carries out oxygen gas plasma cineration technics or wet chemical etch technology etc.Thereafter, the semiconductor-based end 120, can be transferred into the cleaning that the semiconductor wet chem workstation carries out the semiconductor-based end 120, to remove lip-deep post-etch residues in the semiconductor-based ends 120 and sidewall macromolecule 144, shown in the step 207 of Fig. 5 and Fig. 9, then carry out solvent clean technology (solvent cleaningprocess), the semiconductor-based end 120 is placed into to be accepted rotation and soaks in the soaking compartment 130.Be injected with the cleaning solvent 140 of high temperature in the soaking compartment 130, azanol class (hydroxylamine) solvent of 70 ℃ etc. for example, be positioned at the sidewall macromolecule 144 and the residue of dielectric materials layer 112 surfaces, etching hole 122 inwalls and etching hole 122 bottoms with removal, about usually about 5-30 minute of its soak time, for example 10 minutes.Subsequently, semiconductor substrate 120 is rotated drying (spin-drying) technology, utilizes the inertia and the centrifugal force at the semiconductor-based end 120 of rotation to remove most cleaning solvent 140 at the semiconductor-based end 120.
The cleaning solvent 140 here can be the various solvent that contains amine (amine-base) solvent or fluoride (fluoride-base) etc., for example EKC-270 or ACT-935.According to this preferred embodiment, the cleaning solvent 140 in the soaking compartment 130 includes EKC-270.The EKC-270 cleaning solvent is a kind of commercialization post-etch residues remover of being produced by EKC Technology Inc of Du Pont (post-etch residueremover), often is used to remove behind organic polymer composition on the semiconductor-based basal surface, the photoresist ashing residue and organic metal etch residue or the like in the semiconductor wet cleaning.EKC-270 cleaning solvent major ingredients is an azanol class material.The ACT-935 cleaning solvent then is the post-etch residues remover of being produced by Ashland company, and major ingredients is monoethanolamine and azanol class material.
Cleaning solvent 140 injects soaking compartment 130 via the feed-line 132 of cleaning solvent control valve (not being shown among the figure) and cleaning solvent.In the middle of feed-line 132, can be provided with liquid delivery pump Pu (not being shown among the figure).In addition, before cleaning solvent 140 entered soaking compartment 130, cleaning solvent 140 can be placed in earlier in the storage tank and (not be shown among the figure).Storage tank includes heater (heater), in order to cleaning solvent 140 is heated to suitable technological temperature.For instance, the boiling point of EKC-270 cleaning solvent approximately is 110 ℃ to 170 ℃, and therefore the temperature of EKC-270 cleaning solvent should not be higher than 110 ℃ here.Actual technological temperature can be adjusted according to the structural material at the semiconductor-based end 120 and the state of arts of solvent clean technology or the like parameter, wants on the one hand to remove etch byproducts effectively, must not have influence on the conductor 146 that has formed on the other hand.
Subsequently, shown in the step 209 of Fig. 6 and Fig. 9, utilize 142 pairs of semiconductor substrates of deionized water 120 to carry out washing process, further remove the cleaning solvent 140 that is positioned on the dielectric materials layer 112.The temperature range of employed deionized water 142 is between 30 ℃ to 99 ℃ in the washing process, and for example 70 ℃, reaction time range for example was 1 minute between 30 seconds to 5 minutes.In the process of washing process, the cleaning solvent 140 that residues in surface, the semiconductor-based ends 120, etching hole 122 sidewalls and bottom, etching hole 122 holes can be subjected to the heating and the dissolving of deionized water 142, therefore the viscosity of cleaning solvent 140 just can descend, and because of effectively shortening the washing time, be unlikely to excessive corrosion conductor 146 surfaces, make that cleaning solvent 140 is easier to be removed from surface, the semiconductor-based ends 120.
On the other hand owing to be to use the deionized water 142 of high temperature to carry out washing process here, so deionized water 142 can than be easier to cleaning solvent 140 in the composition reaction that is hydrolyzed, make that cleaning solvent 140 is easier to be dissolved in deionized water 142 and to be with and to remove.In addition, under the environment of high temperature, deionized water 142 can also help washing process to remove the oxide and the polymer substance on surface, the semiconductor-based ends 120 with the accessory substance that cleaning solvent 140 reactions are produced.For instance, when cleaning solvent 140 included the EKC-270 cleaning solvent, deionized water 142 can produce ammonium hydroxide with azanol class substance reaction, utilizes ammonium hydroxide to assist to remove oxide and polymer substance.
Wherein, abovementioned steps 207 can alternately be carried out repeatedly with step 209.That is to say that solvent clean technology and washing process can be multiple step (multi-cycle).Thus, the semiconductor-based end 120, can be carried out solvent clean technology and washing process more repeatedly after washing process, till residue, the sidewall macromolecule 144 on surface, the semiconductor-based ends 120 nearly all are removed with cleaning solvent 140.
Afterwards, shown in the step 211 of Fig. 9, drying process is carried out in semiconductor substrate 120, for example utilize nitrogen to come drying of semiconductor substrate 120.Then, shown in the step 213 and step 215 of Fig. 7, Fig. 9, form one deck adhesion coating or barrier layer 124 on surface, the semiconductor-based ends 120, be covered in dielectric materials layer 112 surfaces, etching hole 122 sidewalls and etching hole 122 bottoms, form one deck conductive layer 126 on surface, the semiconductor-based ends 120 again, be covered on the barrier layer 124, and be filled in the etching hole 122.Wherein, conductive layer 126 can utilize tungsten (W), titanium nitride (TiN), tungsten titanium metal materials such as (TiW) or its mixture to constitute.
As the step 217 of Fig. 8 and Fig. 9 shown in, carry out flatening process thereafter,, CMP (Chemical Mechanical Polishing) process for example, to remove unnecessary barrier layer 124 and unnecessary conductive layer 126, in dielectric materials layer 112, form connector 128, for example contact plunger or interlayer connector thus.
In another embodiment of the present invention, before solvent clean technology, can include pre-washing process in addition.Pre-washing process is to utilize 142 pairs of semiconductor substrates 120 of deionized water of high temperature to clean equally, wherein washing process, solvent clean technology can utilize same technology board or same process tool to carry out with pre-washing process, also can utilize different process board or different process instrument to carry out.For instance, washing process, solvent clean technology can be carried out in same semiconductor wet chem workstation with pre-washing process, and spendable process tool includes solvent clean instrument (solvent cleaning tool) or scrubbing tool (scrubber cleaning tool).
In addition, solvent clean technology can continue pre-washing process and directly carry out, and washing process solvent clean technology and directly carrying out and then.In other words, between solvent clean technology and the pre-washing process, can not carry out drying steps or the like technology between washing process and the solvent clean technology.In addition, between solvent clean technology and the pre-washing process, also can carry out other steps between washing process and the solvent clean technology according to the actual process needs, for example intermediate flux soaks into (intermediate post-solventrinse, IPR) step or scrub step.
It is that example is carried out explanation of the present invention that previous embodiment is to use plug structure, yet, this field tool knows that usually the knowledgeable should understand, the present invention is characterized in to use the high temperature deionized water to remove suprabasil cleaning solvent of semiconductor and residue, therefore the present invention need not be confined to make plug structure, and the present invention also can be used for forming or clean metal connecting line construction or connection gasket structure.For instance, the dielectric materials layer 112 of previous embodiment can replace with any other material layer, aluminum metallic material layer for example, the patterns of openings that can have any pattern of patterning photoresist layer 114, and patterning photoresist layer 114 can replace with the hard mask of other materials, for example contains the hard mask of oxynitrides.In other words, the present invention can be used for the cleaning after the etching of various film, or the cleaning before the various depositing of thin film.
Because the present invention uses the high temperature deionized water to remove the suprabasil residue of semiconductor, therefore has following advantage.At first, the high temperature deionized water can remove suprabasil cleaning solvent of semiconductor and residue effectively, so can significantly promote the produced finished product rate of the present invention, also makes the rate of finished products difference value of different platform dwindle, and promotes the stability of technology.Secondly, owing to cleaning solvent can be removed effectively, so the present invention can increase the replacement cycle of cleaning solvent, the cleaning solvent that did not need just more renew in per 8 hours.Therefore, not only can reduce the time that solution spent of changing, increase productivity ratio (productivity), can also save the technology cost.Moreover because the rate of finished products of board improves and the rate of finished products difference value of different platform is dwindled, the difference value of the acceptable technological parameter of each board is also bigger.That is to say that the present invention can utilize a plurality of boards to carry out same technology easily, and needn't worry that the product of different platform made can be very different.
The above only is the preferred embodiments of the present invention, and all equalizations of doing according to claim of the present invention change and modify, and all should belong to covering scope of the present invention.
Claims (21)
1. the cleaning method at a semiconductor-based end includes:
The semiconductor-based end is provided, and this semiconductor-based end, include material layer and patterning photoresist layer, and this patterning photoresist layer is positioned on this material layer;
Utilize this patterning photoresist layer to come this material layer of etching, in this material layer, to form the etching hole as etching mask;
Divest this patterning photoresist layer, utilize cleaning solvent that solvent clean technology is carried out at this semiconductor-based end then; And
Utilize deionized water that washing process is carried out at this semiconductor-based end, and the temperature range of this deionized water is between 30 ℃ to 99 ℃, to remove this cleaning solvent.
2. cleaning method as claimed in claim 1, wherein the reaction time range of this washing process is between 30 seconds to 5 minutes.
3. cleaning method as claimed in claim 1, wherein this solvent clean technology and this washing process are multiple step.
4. cleaning method as claimed in claim 1, wherein this cleaning solvent includes the azanol constituents.
5. cleaning method as claimed in claim 1, wherein the temperature of this cleaning solvent is lower than 110 ℃.
6. cleaning method as claimed in claim 1, wherein this material layer includes dielectric materials layer.
7. cleaning method as claimed in claim 1, wherein this etching hole includes contact plunger hole or interlayer connector hole.
8. cleaning method as claimed in claim 1 includes the step at this semiconductor-based end of Rotary drying in addition after this solvent clean technology.
9. cleaning method as claimed in claim 1 includes the step of being carried out drying process this semiconductor-based end in addition after this washing process.
10. cleaning method as claimed in claim 9, wherein this drying process is to utilize dry this semiconductor-based end of nitrogen.
11. cleaning method as claimed in claim 1 included the step of removing this patterning photoresist layer in addition before this solvent clean technology.
12. cleaning method as claimed in claim 1, wherein this solvent clean technology and this washing process are to carry out among same board.
13. cleaning method as claimed in claim 1, wherein this solvent clean technology and this washing process are to carry out among different platform.
14. cleaning method as claimed in claim 1 included in addition before this solvent clean technology and utilizes this deionized water to be carried out the step of pre-washing process this semiconductor-based end.
15. cleaning method as claimed in claim 14, wherein this solvent clean technology is to carry out among same board with this pre-washing process.
16. cleaning method as claimed in claim 14, wherein this solvent clean technology is to carry out among different platform with this pre-washing process.
17. the cleaning method at a semiconductor-based end includes:
The semiconductor-based end is provided, and this semiconductor-based end, include material layer;
Utilize cleaning solvent that solvent clean technology is carried out at this semiconductor-based end and this material layer, this cleaning solvent includes the azanol constituents; And
Utilize deionized water that washing process is carried out at this semiconductor-based end, and the temperature range of this deionized water is between 30 ℃ to 99 ℃, to remove this cleaning solvent.
18. cleaning method as claimed in claim 17, wherein the reaction time range of this deionized water is between 30 seconds to 5 minutes.
19. cleaning method as claimed in claim 17, wherein this solvent clean technology and this washing process are multiple steps.
20. cleaning method as claimed in claim 17 includes the step of rotating this semiconductor-based end in addition after this solvent clean technology.
21. cleaning method as claimed in claim 17 includes the step of being carried out drying process this semiconductor-based end in addition after this washing process.
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| Application Number | Priority Date | Filing Date | Title |
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| CN200710141772A CN100578731C (en) | 2007-08-21 | 2007-08-21 | Method for cleaning semiconductor substrate |
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| CN200710141772A CN100578731C (en) | 2007-08-21 | 2007-08-21 | Method for cleaning semiconductor substrate |
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| CN100578731C true CN100578731C (en) | 2010-01-06 |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN102915951B (en) * | 2011-08-03 | 2016-09-21 | 无锡华润上华科技有限公司 | The manufacture method of connecting hole |
| CN103594366A (en) * | 2012-08-14 | 2014-02-19 | 中芯国际集成电路制造(上海)有限公司 | A transistor forming method |
| CN104517806B (en) * | 2013-09-30 | 2017-07-21 | 芝浦机械电子装置股份有限公司 | Substrate processing method using same and substrate board treatment |
| CN105448670A (en) * | 2014-08-21 | 2016-03-30 | 中芯国际集成电路制造(上海)有限公司 | Photoresistor removing method, semiconductor device manufacturing method, and semiconductor device |
| CN104900493B (en) * | 2015-05-20 | 2018-02-16 | 中国航天科技集团公司第九研究院第七七一研究所 | A kind of cleaning method of the big depth-to-width ratio TSV blind holes of crystal column surface |
| CN108417532A (en) * | 2018-03-23 | 2018-08-17 | 上海华虹宏力半导体制造有限公司 | The forming method of contact plunger |
| CN112850238B (en) * | 2021-02-03 | 2022-12-23 | 厦门特仪科技有限公司 | Silicon chip photoetching is with antifouling conveying equipment |
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