CN102890427A

CN102890427A - Method for preparing skewed data in field programmable gate array (FPGA) of direct-writing type photoetching system

Info

Publication number: CN102890427A
Application number: CN2012103499262A
Authority: CN
Inventors: 陈勇; 陈修涛; 张爱民
Original assignee: TIANJIN XINSHUO PRECISION MACHINERY CO Ltd
Current assignee: Zhejiang Jinxin Microelectronics Technology Co.,Ltd.
Priority date: 2012-09-18
Filing date: 2012-09-18
Publication date: 2013-01-23
Anticipated expiration: 2032-09-18
Also published as: CN102890427B

Abstract

The invention discloses a method for preparing skewed data in a field programmable gate array (FPGA) of a direct-writing type photoetching system. The method comprises the following steps of: storing gray-scale map data which are output by an upper detail drawing computer into a double-data rate synchronous dynamic random access memory (DDR) in a scanning line format; after the number of lines of the gray-scale map data reaches a certain number, reading data from the DDR by a control module in the FPGA at an interval which is formed according to a skew factor N, storing the data into a random access memory (RAM) of the FPGA through a data bus, and buffering the data; reading the skewed data from the RAM of the FPGA by the control module in the FPGA in a format which is formed according to the skew factor N, inputting the skewed data into a conversion matrix, converting gray scale, and extracting scanning data; and storing the converted data into the RAM of the FPGA through the data bus, buffering the data, and writing the data into a digital micro-mirror device (DMD) scanning display data area of the DDR in a subsequent operation period. The method has the advantages that bitmap data is not required to be processed by the upper detail drawing computer, the detail drawing data processing capacity is improved, the bit data processing capacity of the FPGA is embodied, skew scanning speed is increased, and the utilization rate of resources of the FPGA is high.

Description

The method that a kind of FPGA medium dip data of write-through etching system are prepared

Technical field

The present invention relates to semicon industry and printed circuit board industry technical field of lithography, be specifically related to a kind of method of FPGA medium dip data preparation of write-through etching system.

Background technology

Nonangular scan exposure structure in the write-through etching system, finish whole Data Preparations by upper component computing machine, polar plot is converted to the dot matrix grid map, is converted to by gray-scale map again and can directly inputs to the scale-of-two black-white point system of battle formations that digital micro-mirror (DMD) shows.In the scan exposure structure that tilts, upper component computing machine also needs the scale-of-two black-white point system of battle formations is converted according to inclination factor N(angle of inclination) image rotating regenerates data.The computing unit of computing machine has reached 64bit, and minimum calculation unit also is 8bit, and the read-write of 8bit data and the speed of processing can not show a candle to the fast operation of 64bit, and the bit computing will be slower.Inclination mode scan exposure can improve the resolution of exposure image, the big or small grid precision that determines resolution is controlled by inclination factor N, the grid precision that doubles, corresponding data processing amount will increase by 4 times, and computer resource is also seriously wasted in the processing of a large amount of bit data.

Characteristics of the present invention are to finish tilt data to prepare in FPGA, and the gray-scale map data are converted to for the black-white point system of battle formations after the inclination of micro mirror (DMD) scanning demonstration.

Summary of the invention

The objective of the invention is: the characteristics of performance FPGA, the gray-scale map data are converted to for the black-white point system of battle formations after the inclination of micro mirror (DMD) scanning demonstration, alleviate the pessimistic time waste of upper component computing machine.

Technical scheme of the present invention is as follows:

A kind of FPGA medium dip data preparation method of write-through etching system is characterized in that, may further comprise the steps:

(1) at first the gray-scale map data of upper component computer export is stored among the DDR by the scan line form;

(2) after the gray-scale map data reach certain line number, the spacing reading out data that control module control is formulated by inclination factor N from DDR among the FPGA also cushions in the RAM of FPGA through data bus;

(3) data after the form that control module is formulated by inclination factor N again among the FPGA is read from the RAM of FPGA are input to transition matrix and carry out the conversion of gray scale and the extraction of scan-data;

(4) data after the conversion cushion in data bus is restored the RAM of FPGA, and wait for that micro mirror (DMD) scanning that writes DDR when the next operating cycle shows the data field.

Described DDR refers to dynamic synchronization storer DDR2 or DDR3.

Described FPGA is V5, the V6 of Xilinx company, the model FPGA of V7 series.

DDR of the present invention only has a circuit-switched data, address bus, data among the DDR read also and are controlled by FPGA, FPGA needs simultaneously parallel control micro mirror (DMD) scanning demonstration work, therefore will be with the periodic duty of timeslice form to twice of DDR read, twice is write operation, and be synchronized in micro mirror (DMD) the scanning demonstration work.

Advantage of the present invention is:

1, saves upper component computing machine to the processing of data bitmap, increased the component data-handling capacity;

2, performance FPGA processes the bit data ability, has accelerated dip sweeping speed;

3, the FPGA resource utilization is high.

Description of drawings

Fig. 1 is module diagram among the FPGA of the present invention.

Fig. 2 is that DDR medium dip data of the present invention read schematic diagram.

Fig. 3 is that RAM medium dip data of the present invention read key diagram.

Fig. 4 is DDR work schedule schematic diagram among the FPGA of the present invention.

Fig. 5 is FPGA medium dip state machine key diagram of the present invention.

Embodiment

The present invention is the method that a kind of FPGA medium dip data of direct-write photoetching system are prepared, for convenience of description, and selected inclination factor N=4.

With reference to Fig. 1, module is embodied as FPGA and reads data among the DDR by 128bit data bus 1 among the FPGA of the present invention, DDR is with burst type work, finish the read/write of 256 bit data at every turn, reading data is divided into two 64bit data buss 2, deposit simultaneously among the FPGA buffer memory in the

RAM storer

4 and 6 in,

RAM storer

4 and 6 shares the address bus 9 that writes and the address bus 8 of reading, control module 11 deposits sequential in according to DDR work status signals 3 control data, also to control simultaneously data reading order among the RAM, read 8 data from RAM storer 4 first and give transition matrix 10 through 16bit data bus 5, give transition matrix 10 from read 8 data from RAM storer 6 through 16bit data bus 7 again, transition matrix 10 divides into groups the 256bit data that input is advanced again, be converted to 16 16bit data of new layout, deposit respectively among the FPGA buffer memory in the

RAM storer

15 and 18 in by 16bit data bus 12,

RAM storer

15 and 18 shares the address bus 13 that writes and the address bus 14 of reading, read and be respectively 64bit data bus 16, be combined as 128bit data bus 19 and input to the DDR driver module, send out full scale will signal 20 behind the full data line of control module 11 data buffer storage in

RAM storer

15 and 18, according to the permission read output signal 21 that returns, and time clock 17 control increasing progressively from

RAM storer

15 and 18 reading out data addresses.Control module 11 is from DDR work status signals 3 continuous read signals, DDR can send operation signal 22 during access time, send the address of read-write DDR and control data by address bus 23.

With reference to Fig. 2, selected inclination factor N=4 in the embodiments of the invention, the gray scale of view data is used 16 grades of gray scales, and namely each picture point needs 4 bit data to represent gray-scale value; DDR work is set as burst mode of operation in order to bring into play maximal efficiency, and burst data length is 4, and namely DDR one secondary burst read/write data has 256bit.Because resource-constrained among the FPGA, view data can not all directly once be finished the tilted image rotation in FPGA, resource is how much closely related among the price of fpga chip and the FPGA, in order to save cost on the hardware, adopts two step image inclinations to rotate after optimizing.The first step is utilized reading address variation on DDR, and second step reading address in the RAM of FPGA changes.The gray-scale map data of upper component computer input leave among the DDR by the scan line form, order is deposited, when reading out data from DDR, read according to certain intervals, gap length is to calculate according to the length gauge of inclination factor N and row, realizes the first step rotation of view data by sequential storage, interval reading manner.From DDR, read tilt data, just can carry out after being stored in again certain line number among the DDR, otherwise will cause partial data to overflow outside the storage space, random figure phenomenon occurs.The burst gray-scale map that to read 256bit data are 1 * 64 dot matrix from DDR, the gray-scale map of delegation's dot matrix needs form row at 64, according to inclination factor N=4, need the combination of 16 row data to finish first step Sloped rotating, when therefore from DDR, reading delegation's tilt data, first row 64 dot array datas directly read, and every row 64 dot array datas need to move forward 16 row thereafter, until that data line reads is complete.

With reference to Fig. 3, the RAM that the second step image inclination is rotated in FPGA in the embodiments of the invention finishes, read for the first time from DDR the data of Sloped rotating sequentially leave in the RAM of FPGA with the form of going, per 16 * 256bit is a storage area, 16 grades of gradation datas of representative image such as each point among Fig. 3, per 4 points form the view data of 16bit, there are 64 dot image in delegation, the dot matrix image of totally 16 row, control module 11 output image data reading address, each row of data reads 4 16bit, buffer memory completely after from reading first at last the view data of first 4 16bit, move delegation on successively thereafter and move right 4 and read view data and finish image second step Sloped rotating.Whenever from DDR, read afterwards data line and then be stored in corresponding RAM storage area, deposit order continuous circulation address, the address that the second step Sloped rotating reads from RAM is read 4 16bit view data with the inverted order mode and is finished Sloped rotating take the row address that deposits in as initial.

With reference to Fig. 3,1, the image inclination data have 16 * 4 16bit to deliver to transition matrix 10 at every turn in the embodiments of the invention, in transition matrix 10, again divide into groups, tell 4 gray scale tomographic images, the view data of form recomposition 4 row 16 dot matrix that show according to the dip sweeping data again.

With reference to Fig. 4,5, the read-write sequence of image inclination operation DDR needs that to read among the DDR work of data synchronous with micro mirror DMD in the embodiments of the invention, namely when micro mirror DMD reads the idle periods (low level) of DDR timing waveform (DMD), there is the view data of upper component computer input then to deposit among the DDR, work schedule is such as (WR1), depositing line number in satisfies the Sloped rotating data volume and then reads among the RAM, work schedule is such as (RD), finish delegation's tilt data conversion and then write back among the DDR, work schedule is such as (WR2).Micro mirror DMD reads data demonstration among the DDR, because front and back frame display image data is without higher correlativity, each frame data that micro mirror DMD shows all will all read from DDR, therefore the time occupancy is large, but the periodicity of reading out data is strong, in the idle period of time of reading out data, the operation view data deposit writing after the reading, change of DDR, image inclination data in.Every display update one frame data are finished inclination conversion and the reading writing working of data line synchronously.

Claims

1. the method for the FPGA medium dip data of write-through etching system preparation is characterized in that, may further comprise the steps:

(4) data after the conversion cushion in data bus is restored the RAM of FPGA, and wait for that the micro mirror DMD scanning that writes DDR when the next operating cycle shows the data field.

2. the FPGA medium dip data preparation method of write-through etching system according to claim 1 is characterized in that, described DDR refers to dynamic synchronization storer DDR2 or DDR3.

3. the FPGA medium dip data preparation method of write-through etching system according to claim 1 is characterized in that, described FPGA is V5, the V6 of Xilinx company, the model FPGA of V7 series.