CN102855331B - Method of converting EDA (Electronic Document Authorization) files to ATE (Automatic Test Equipment) machine station format files - Google Patents
Method of converting EDA (Electronic Document Authorization) files to ATE (Automatic Test Equipment) machine station format files Download PDFInfo
- Publication number
- CN102855331B CN102855331B CN201210355952.6A CN201210355952A CN102855331B CN 102855331 B CN102855331 B CN 102855331B CN 201210355952 A CN201210355952 A CN 201210355952A CN 102855331 B CN102855331 B CN 102855331B
- Authority
- CN
- China
- Prior art keywords
- file
- pin
- information
- wgl
- eda
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000000034 method Methods 0.000 title claims abstract description 40
- 238000012360 testing method Methods 0.000 title claims abstract description 19
- 238000013475 authorization Methods 0.000 title abstract 2
- 238000006243 chemical reaction Methods 0.000 claims abstract description 26
- 238000005516 engineering process Methods 0.000 claims abstract description 10
- 102100028029 SCL-interrupting locus protein Human genes 0.000 claims description 15
- 238000004458 analytical method Methods 0.000 claims description 6
- 230000006835 compression Effects 0.000 claims description 4
- 238000007906 compression Methods 0.000 claims description 4
- 238000013461 design Methods 0.000 abstract description 7
- 238000012545 processing Methods 0.000 abstract description 7
- 239000004065 semiconductor Substances 0.000 abstract description 5
- 230000008569 process Effects 0.000 description 7
- 230000006870 function Effects 0.000 description 5
- 230000008859 change Effects 0.000 description 4
- 238000010586 diagram Methods 0.000 description 2
- 230000009471 action Effects 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 238000013501 data transformation Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000005008 domestic process Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 230000009466 transformation Effects 0.000 description 1
- 230000001131 transforming effect Effects 0.000 description 1
Landscapes
- Tests Of Electronic Circuits (AREA)
- Information Retrieval, Db Structures And Fs Structures Therefor (AREA)
Abstract
The invention discloses a method of converting EDA (Electronic Document Authorization) files to ATE (Automatic Test Equipment) machine station format files. The method comprises the following steps of: processing (E) VCD (Video Compact Disc) format files in the EDA files by using a series of processing steps to produce WGL (Wingate License File) format files; and secondly converting the WGL format files and STIL (Standard Test Interface Language) format files in the EDA files to the ATE machine station format files by using a series of processing steps. According to the method disclosed by the invention, a special file processing technology is adopted, so that the conversion time is greatly reduced, wherein the WGL conversion time is about one third of a foreign product, so that a blank space of the field of national semiconductor testing is filled, and a new selection is supplied for enterprises needing the technical scheme of the invention, such as design companies and ATE manufacturers.
Description
Technical field
The present invention relates to a kind of conversion method of ATE board file, be specifically related to a kind ofly can directly change the conversion method of EDA file to ATE board formatted file, belong to semiconductor test technical field.
Background technology
EDA(Electronic Design Automation, electric design automation) file, there is multiple file layout, specifically comprise VCD (Value Change Dump) file layout, EVCD (Extended Value Change Dump) file layout, WGL(Waveform Generation Language, waveform generation language) file layout and STIL(Standard Test Interface Language, Standard Test Interface Language) file layout.Wherein, VCD file and EVCD file are all a kind of file layouts based on ASCII character, for recording the signal message being produced by EDA emulation tool, form between them is basically identical, both key distinctions are the information of EVCD file with pin type, be that this pin of mark is input pin or output pin, VCD file is without this pin type information.
At present, in semiconductor test field, EDA file is to ATE (Automatic Test Equipment, automatically testization equipment) board file switching software monopolizes by the product of TestInsight company of Israel and the Vtran of the U.S. completely, at present at home, a part has the company of financial strength, carries out the conversion of ATE board file by the software of buying Israel or u s company, as the Hai Si of Huawei etc., but the switching software of external ATE board file still has following shortcoming:
The first, external software is not supported V50, and some are compared with the board of low side, as VTT, and Chroma 3360 etc.
The second, external software is not supported repeat compression, and the ATE formatted file after conversion is bulky.
The 3rd, after VCD file and the conversion of EVCD file, cannot compare.VCD file and EVCD file including the full detail of each pin, must use the fixing cycle to make it periodization, in the time that each cycle is determined to sequential format, may have the omission of some time sequence information, so the signal after conversion will be followed original signal difference, chip testing can think that chip logic function goes wrong, and produces and judges by accident and incur loss through delay volume production; Or test is passed through, and problematic logic function chip is thought by mistake to the chip of perfect in shape and function.
In addition, most of design corporation of our country is by manually or carry out the conversion of ATE board file with script.
Manually conversion is to use electrical form or text editor, can implement to convert to ATE board formatted file for small documents, the not WGL with Scan information and STIL file layout, but the efficiency of manually changing is very low, a general slip-stick artist changes a file one day at least, one week at most.Large file (more than 10M), carries out manually transforming consuming time huge with the WGL of Scan information and STIL file layout, and accuracy cannot ensure.Manually turn VCD file layout and EVCD file layout Arabian Nights especially, wherein relate to the periodization of waveform, the definition of each cycle sequential format, its workload is manual cannot completing all.
Some design corporations are used script to carry out EDA file and are converted to ATE board file, can improve conversion efficiency, but be confined to simple WGL file layout, when EDA file layout flexibly some or during with Scan information, script will go wrong and even change and make mistakes, and brings unpredictable risk to the chip testing in later stage.
The domestic method that does not also have design corporation VCD file and EVCD file to be converted to ATE board file at present, reason is not yet to find solution for the problem identificatioin of each cycle sequential.
Summary of the invention
Technical matters to be solved by this invention is the defect for the existing ATE board file conversion relating in background technology, propose the conversion plan that a kind of EDA file is converted to ATE board formatted file, be converted to solve EDA file some problems that exist in ATE board formatted file.
The present invention is for solving the problems of the technologies described above by the following technical solutions:
A kind of method that EDA file is converted to ATE board formatted file, first the file of the file of the VCD form in EDA file and EVCD form is converted to the file of WGL form, then WGL file in EDA file and STIL file is transformed to ATE board formatted file; Wherein the file of the file of VCD form and EVCD form is converted to the file concrete steps of WGL form and is:
Step 101, first, reads the pin information comprising in VCD and EVCD file, analyzes the pin name information that obtains each pin; Then, the logical message while generating VCD, EVCD file according to eda software is determined the type of each pin, and uses waveform reader to determine the cycle of clock pins;
Step 102, reads the full detail of VCD and EVCD file, then carries out successively analytical procedure, periodization treatment step, sequential set-up procedure, specific as follows:
A, analytical procedure: by pin information time m-ly extract along information, preserve respectively taking each pin as unit each pin time m-along information, generate the first intermediate file temp.wave;
B, periodization treatment step: for each pin, the first intermediate file temp.wave A step being generated according to definite cycle of step 101 cuts, obtain the second intermediate file temp.cycled and the 3rd intermediate file temp.index, wherein the second intermediate file temp.cycled records index and the corresponding line number of this index that each pin is used, and the 3rd intermediate file temp.index records the corresponding data of index and the shape information that each pin is used;
C, sequential set-up procedure: by the data of the 3rd intermediate file temp.index and shape information be transformed into corresponding vector data and time m-along information, generate the 4th intermediate file temp. mask;
Step 103, generate WGL file step: the data and the sequential collection Tset that obtain every row vector according to the second intermediate file temp.cycled and the 4th intermediate file temp.mask, described sequential collection Tset is the sequential that whole pins that every row vector is corresponding use, the sequential collection Tset information getting is kept in internal memory, generates WGL file.
Further, a kind of method that EDA file is converted to ATE board formatted file of the present invention, described by WGL file in EDA file and STIL file conversion ATE board formatted file, comprise the following steps:
Step 201, loads WGL, STIL file, and the pin information in file reading uses pin editing machine to edit pin, determines final pin information, and this pin information comprises the title of order of the pin and each pin;
Step 202, is used blocks of files to read technology and starts conversion according to the definite pin information of step 201, generates test vector file Pattern and sequential file Timing after EOC;
Step 203, the test vector file Pattern forming according to step 202 and sequential file Timing generate ATE board formatted file.
Further, a kind of method that EDA file is converted to ATE board formatted file of the present invention, described step 201 is in the time of the pin information reading in WGL file, and the key word in WGL file comprises ScanCell, ScanChain and ScanState; Wherein: the Cell number that ScanCell comprises with ScanChain is consistent, this Cell number is more than or equal to the data length containing in ScanState; ScanState comprises ScanChain and Scan data, Scan data by 0,1 and X form; The Cell sequence consensus comprising as ScanCell and ScanChain, the order of the Scan data in ScanState is constant, when the Cell reversed in order that ScanCell and ScanChain comprise, the Scan data order reversion in ScanState, 0 become 1,1 become 0, X is constant.
Further, a kind of method that EDA file is converted to ATE board formatted file of the present invention, when the position of Cell in ScanChain be "! " time, represent that the Scan data data in the ScanState of opposite position should be reversed.
Further, a kind of method that EDA file is converted to ATE board formatted file of the present invention, in the analytical procedure of step 102 by pin information time m-while extracting along information, also comprise when whether setting is removed the m-part prefix along information or the step of suffix.
Further, a kind of method that EDA file is converted to ATE board formatted file of the present invention, in the sequential set-up procedure of step 102, by the data of the 3rd intermediate file temp.index and shape information be transformed into corresponding vector data and time m-during along information, also comprise the step of removing burr Jet in shape information.
Further, a kind of method that EDA file is converted to ATE board formatted file of the present invention, in step 103, while generating WGL file, also comprise and select as required output mode, described output mode comprises edge relatively or the comparison of windowing, and selects whether to use compression repeat.
The present invention adopts above technical scheme, compared with prior art has following beneficial effect:
The present invention has adopted special file processing technology, greatly reduced switching time, wherein WGL switching time about external product 1/3rd, fill up the blank in domestic semiconductor test field, for design corporation, ATE manufacturer etc. need the enterprise of this programme to offer new selection.
Switching strategy of the present invention is to convert VCD file layout and EVCD file layout to intermediate file format WGL, and then converts WGL, STIL to specific ATE board file; The waveform software that can check VCD, EVCD and WGL is provided, can has checked very intuitively and compare.
Brief description of the drawings
Fig. 1 is the process flow diagram that in method of the present invention, VCD file layout EVCD file layout is converted to WGL file layout.
Fig. 2 is the process flow diagram that in method of the present invention, WGL file layout and STIL file layout convert specific ATE board file layout to.
Embodiment
Below in conjunction with accompanying drawing, technical scheme of the present invention is further described in detail:
As shown in Figure 1, VCD file and EVCD conversion key step are:
1. read the pin information in VCD file and EVCD file, analyze and process pin information, use waveform reader to determine the cycle.
If 2. defined prefix or the suffix on m-edge need to remove time, at the waveform of the corresponding time span of front or rear removal of whole waveform.This parameter works at step 102 sub-step A.
If 3. client need to remove some burr (Jet, burr refers in the of short duration saltus step in the inside of single cycle), input the ratio (being the proportion in shared whole cycle of burr) of burr, select as required Compare Mode(output mode), Edge(is along relatively) or the Window(comparison of windowing), select whether to use repeat compression (repeat is a key word in WGL file).Described parameter works in step 103.
4. after the various parameters of conversion all determine, parameter can be preserved into configuration file, VCD file and EVCD file that convenient conversion is of the same type use.
5. Parse(analyzes) process is by the time of the pin in VCD file and EVCD file and extract along information, according to pin come the holding time and along information (VCD file and EVCD file be according to the time preserve pin and along information), generate the first intermediate file temp.wave, this process is mainly the structure that changes VCD file and EVCD, makes it conveniently to read for software.
6. Cyclize(periodization) process be by Parse generate the first intermediate file temp.wave in each pin cut according to the given cycle.The second intermediate file temp.cycled and the 3rd intermediate file temp.index are the files after Cyclize, wherein 2. temp.cycled has recorded index that each pin uses and corresponding line number, and the 4th intermediate file temp.index preserves data and the shape information that index is corresponding.
7. Timing Mask(sequential is adjusted) process is that the 3rd intermediate file temp.index converts the 4th intermediate file temp. mask to, by the data transformation of the 3rd intermediate file temp. index become vector data, waveform and time m-edge, be saved in the 4th intermediate file temp. mask.When Tset(sequential collection, the sequential that the whole pins of every row Vector use) too much time, the easiest method is revised Compare(output in the 4th intermediate file temp. mask exactly) information, patterned alter mode is provided in this method.
8. the last WGL file that generates.
In Fig. 1, sequential adjustment member is the difficult point of VCD file and EVCD conversion, this part relates to a line in every row Vector(Pattern), the determining and the transformation of concrete waveform of Tset, obtain data and the sequential collection Tset of every row vector according to the second intermediate file temp.cycled and the 4th intermediate file temp.mask, described sequential collection is the sequential that whole pins that every row vector is corresponding use, the sequential collection Tset information getting is kept in internal memory, generates WGL file.
As shown in Figure 2, WGL and STIL file step of converting are:
1. load WGL/STIL file, read pin information, use pin editing machine to pin editor, comprise movement, search, replace, delete; Preserve the information of pin, can directly open pin information file and do editor's action.
2. function is selected.Can select to preserve annotation, launch circulation, illegal Tset(is with the Tset of underscore beginning name) character processing, for Scan file (with respect to Parallel form, Parallel is parallel file, and Scan is the file of serial), can select the length (character length) of every row Scan vector, flatten Scan, WGL form another one function is that Scan State Bit is reversed.
3. determine all conversion parameters, start conversion, the present invention has used blocks of files to read technology, and uses multithreading, has greatly reduced that file reads and the processing time.
4. use blocks of files to read technology and start conversion, after EOC, generate test vector file Pattern and sequential file Timing.
WGL and STIL are the files of periodization, simple with respect to VCD file and EVCD.The difficult point of this part is the conversion of WGL Scan Pattern, WGL Scan Pattern relates to ScanCell, ScanChain and ScanState(ScanCell, ScanChain and ScanState are the key words in WGL file), the Cell number that ScanCell comprises with ScanChain is consistent, ScanState comprises ScanChain and Scan data, Scan data are by 0, 1 and X composition, this Cell number is more than or equal to the data length containing in ScanState, the cell sequence consensus that ScanCell and ScanChain comprise, ScanState order is constant, the Cell reversed in order that ScanCell and ScanChain comprise, the reversion of ScanState order, in ScanChain, contain "! ", represent that the ScanState data of opposite position should reverse, 0 become 1,1 become 0, X is constant, described opposite position be "! " position of place Cell, in this method, adding the option of Scan State Bit reversion is exactly singularity and the complicacy based on Scan Pattern.
Conversion bright spot in Fig. 2 is to have used blocks of files to read technology, reduce by approximately 1/3rd time overhead, not obvious for this advantage of small documents, but most WGL, STIL file are all the sizes that hundreds of million is even gone up G, semiconductor test is an industry with time race, and it is the important bright spot of this method that time overhead reduces.
In the present invention, have individual waveform reader, can support VCD, EVCD and WGL formatted file, current waveform reader on the market is not supported WGL form, and this method supports that the object of WGL is mainly in order to facilitate VCD, EVCD to convert the comparison of WGL to.
Claims (6)
1. one kind is converted to EDA file the method for ATE board formatted file, it is characterized in that, first the file of the file of the VCD form in EDA file and EVCD form is converted to the file of WGL form, then WGL file in EDA file and STIL file is transformed to ATE board formatted file; Wherein the file of the file of VCD form and EVCD form is converted to the file concrete steps of WGL form and is:
Step 101, first, reads the pin information comprising in VCD and EVCD file, analyzes the pin name information that obtains each pin; Then, the logical message while generating VCD, EVCD file according to eda software is determined the type of each pin, and uses waveform reader to determine the cycle of clock pins;
Step 102, reads the full detail of VCD and EVCD file, then carries out successively analytical procedure, periodization treatment step, sequential set-up procedure, specific as follows:
A, analytical procedure: by pin information time m-ly extract along information, preserve respectively taking each pin as unit each pin time m-along information, generate the first intermediate file temp.wave;
B, periodization treatment step: for each pin, the first intermediate file temp.wave A step being generated according to definite cycle of step 101 cuts, obtain the second intermediate file temp.cycled and the 3rd intermediate file temp.index, wherein the second intermediate file temp.cycled records index and the corresponding line number of this index that each pin is used, and the 3rd intermediate file temp.index records the corresponding data of index and the shape information that each pin is used;
C, sequential set-up procedure: by the data of the 3rd intermediate file temp.index and shape information be transformed into corresponding vector data and time m-along information, generate the 4th intermediate file temp. mask;
Step 103, generate WGL file step: the data and the sequential collection Tset that obtain every row vector according to the second intermediate file temp.cycled and the 4th intermediate file temp.mask, described sequential collection Tset is the sequential that whole pins that every row vector is corresponding use, the sequential collection Tset information getting is kept in internal memory, generates WGL file;
Described by WGL file in EDA file and STIL file conversion ATE board formatted file, comprise the following steps:
Step 201, loads WGL, STIL file, and the pin information in file reading uses pin editing machine to edit pin, determines final pin information, and this pin information comprises the title of order of the pin and each pin;
Step 202, is used blocks of files to read technology and starts conversion according to the definite pin information of step 201, generates test vector file Pattern and sequential file Timing after EOC;
Step 203, the test vector file Pattern forming according to step 202 and sequential file Timing generate ATE board formatted file.
2. a kind of method that EDA file is converted to ATE board formatted file according to claim 1, it is characterized in that, described step 201 is in the time of the pin information reading in WGL file, and the key word in WGL file comprises ScanCell, ScanChain and ScanState; Wherein: the Cell number that ScanCell comprises with ScanChain is consistent, this Cell number is more than or equal to the data length containing in ScanState; ScanState comprises ScanChain and Scan data, Scan data by 0,1 and X form; The Cell sequence consensus comprising as ScanCell and ScanChain, the order of the Scan data in ScanState is constant, when the Cell reversed in order that ScanCell and ScanChain comprise, the Scan data order reversion in ScanState, 0 become 1,1 become 0, X is constant.
3. a kind of method that EDA file is converted to ATE board formatted file according to claim 2, is characterized in that: when the position of Cell in ScanChain is! Time, represent that the Scan data data in the ScanState of opposite position should be reversed.
4. a kind of method that EDA file is converted to ATE board formatted file according to claim 1, it is characterized in that: in the analytical procedure of step 102 by pin information time m-while extracting along information, also comprise when whether setting is removed the m-part prefix along information or the step of suffix.
5. a kind of method that EDA file is converted to ATE board formatted file according to claim 1, it is characterized in that: in the sequential set-up procedure of step 102, by the data of the 3rd intermediate file temp.index and shape information be transformed into corresponding vector data and time m-during along information, also comprise the step of removing burr in shape information.
6. a kind of method that EDA file is converted to ATE board formatted file according to claim 1, it is characterized in that: in step 103, while generating WGL file, also comprise and select as required output mode, described output mode comprises edge relatively or the comparison of windowing, and selects whether to use repeated compression.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210355952.6A CN102855331B (en) | 2012-09-24 | 2012-09-24 | Method of converting EDA (Electronic Document Authorization) files to ATE (Automatic Test Equipment) machine station format files |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210355952.6A CN102855331B (en) | 2012-09-24 | 2012-09-24 | Method of converting EDA (Electronic Document Authorization) files to ATE (Automatic Test Equipment) machine station format files |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN102855331A CN102855331A (en) | 2013-01-02 |
| CN102855331B true CN102855331B (en) | 2014-12-10 |
Family
ID=47401919
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201210355952.6A Active CN102855331B (en) | 2012-09-24 | 2012-09-24 | Method of converting EDA (Electronic Document Authorization) files to ATE (Automatic Test Equipment) machine station format files |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN102855331B (en) |
Families Citing this family (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106872872B (en) * | 2015-12-14 | 2020-07-03 | 北京确安科技股份有限公司 | Chip test vector conversion method |
| CN107506340B (en) * | 2017-08-11 | 2019-10-18 | 深圳市贝思科尔软件技术有限公司 | A kind of data transfer device and system |
| CN111708621B (en) * | 2020-05-22 | 2024-03-29 | 伟恩测试技术(武汉)有限公司 | Display method of Pattern file based on multithread parallel processing |
| CN112257359B (en) * | 2020-10-21 | 2024-04-16 | 海光信息技术股份有限公司 | Debugging method, device, debugging system and storage medium for data waveform |
| CN112285538B (en) * | 2020-10-30 | 2022-09-20 | 国核自仪系统工程有限公司 | Chip testing method and system |
| CN112710947A (en) * | 2020-12-22 | 2021-04-27 | 上海华岭集成电路技术股份有限公司 | ATE-based functional test method and tool |
| CN117829052B (en) * | 2024-01-15 | 2024-06-25 | 上海宏泰芯半导体科技有限公司 | ModelSim and test system joint simulation debugging method |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1647248A (en) * | 2002-04-11 | 2005-07-27 | 株式会社爱德万测试 | Manufacturing method and apparatus to avoid prototype-hold in ASIC/SOC manufacturing |
-
2012
- 2012-09-24 CN CN201210355952.6A patent/CN102855331B/en active Active
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1647248A (en) * | 2002-04-11 | 2005-07-27 | 株式会社爱德万测试 | Manufacturing method and apparatus to avoid prototype-hold in ASIC/SOC manufacturing |
Non-Patent Citations (7)
| Title |
|---|
| Measurement World 》.2001,第1-5页. * |
| STIL-ATE与EDA之间的桥梁;孙亚春;《中国集成电路》;20100630(第133期);全文 * |
| Tony Taylor，Robert Ruiz.Elements of STIL bridge design and test.《Test & Measurement World 》.2001,第1－5页. * |
| Tony Taylor,Robert Ruiz.Elements of STIL bridge design and test.《Test & * |
| 孙亚春.STIL-ATE与EDA之间的桥梁.《中国集成电路》.2010,(第133期),70－72. * |
| 连接EDA和ATE专家系统方法;陈敏 樊锐;《电子测量技术》;20021231(第6期);全文 * |
| 陈敏 樊锐.连接EDA和ATE专家系统方法.《电子测量技术》.2002,(第6期),14，15. * |
Also Published As
| Publication number | Publication date |
|---|---|
| CN102855331A (en) | 2013-01-02 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN102855331B (en) | Method of converting EDA (Electronic Document Authorization) files to ATE (Automatic Test Equipment) machine station format files | |
| CN104679658A (en) | Test method and test system for WEB pages | |
| CN109062584A (en) | Device, method, system and the storage medium of a kind of multiple chips of while burning | |
| CN102331967A (en) | Method for managing chip verification test cases | |
| CN110543621B (en) | Multi-format result document analysis system of aviation detection equipment and use method thereof | |
| CN103377123B (en) | A kind of web page code automated testing method and device | |
| CN102608517A (en) | Method for rapidly creating integrated circuit test program package | |
| CN112365167B (en) | Dynamic ontology model-based power grid equipment digital twin construction method and device | |
| CN102565683B (en) | Generation and verification method of test vector | |
| CN109902318B (en) | Method and device for generating standard time delay format file | |
| CN111400169B (en) | Method and system for automatically generating netlist file for testing software and hardware | |
| CN104699473A (en) | Timing constraint file generation method and device and RTL (Register Transfer Level) simulation equipment | |
| CN105158673A (en) | ATE machine table file generation method and device | |
| CN114510902A (en) | Simulation result verification method, device, equipment and computer storage medium | |
| CN117214664A (en) | Method, system, device, equipment and storage medium for offline testing chip | |
| CN110927587B (en) | Method and device for generating battery pack charge and discharge test report | |
| JP5396143B2 (en) | Multi-power supply simulation result analysis apparatus and result analysis method | |
| CN115718249A (en) | ATE-oriented chip test vector conversion method | |
| CN103427803B (en) | Based on the method for the filtering burr of synchronous circuit | |
| CN102882611B (en) | Automatic test method and device for radio-frequency performance comparison | |
| CN108256003A (en) | A kind of method that union operation efficiencies are improved according to analysis Data duplication rate | |
| CN104268314B (en) | Waveform display method is measured based on Easy HDL emulation logic analyzers | |
| CN113917311A (en) | Chip parameter tolerance testing method and device | |
| CN103530479A (en) | Partial testability design system and method for electronic design interchange format (EDIF) netlist-class circuits and based on Perl | |
| JP2020098413A (en) | Test support device, test support method and computer program |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| TR01 | Transfer of patent right | ||
| TR01 | Transfer of patent right |
Effective date of registration: 20220411 Address after: Room 617, No. 1, Lane 666, China (Shanghai) pilot Free Trade Zone, Pudong New Area, Shanghai, 201204 Patentee after: Shanghai GuBo Technology Co.,Ltd. Address before: 210000 Room 102, building 15, chunjingyuan, Jingming Jiayuan, Yuhuatai District, Nanjing, Jiangsu Province Patentee before: Rui Qiping |