CN117214664A - Method, system, device, equipment and storage medium for offline testing chip - Google Patents
Method, system, device, equipment and storage medium for offline testing chip Download PDFInfo
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Abstract
The application provides a method, a system, a device, equipment and a storage medium for offline testing of chips, wherein the method comprises the steps of obtaining configuration information of the chips to be tested, wherein the configuration information comprises the following steps: model and interface data of the chip to be tested; acquiring an input/output IO state corresponding to the configuration information from a memory through a microcontroller, and sending the IO state to a field programmable gate array module; and giving an IO state to an interface of the chip to be tested through the field programmable gate array module, and testing the chip to be tested. The method can achieve the effect of efficiently and accurately testing the chip.
Description
Technical Field
The present application relates to the field of chip testing, and in particular, to a method, system, apparatus, device, and storage medium for offline testing of chips.
Background
At present, in the production and manufacturing process of chips, partial finished products are bad chips and cannot be normally used due to the complexity of manufacturing processes, huge process steps, environmental factors (no degree, environmental humidity, temperature and the like), and even mature processes can only ensure the yield of 95 percent and even lower. It must not be acceptable for the customer to sell these chips directly without any processing. ATE tests will be performed at various stages of the chip.
However, during the test of ATE, a phenomenon of low yield of chips, that is, a phenomenon that a large number of chips are screened out by ATE due to test failure, is often encountered.
Therefore, how to test the chip efficiently and accurately is a technical problem to be solved.
Disclosure of Invention
The embodiment of the application aims to provide a method for testing chips off-line, and the technical scheme of the embodiment of the application can achieve the effect of efficiently and accurately testing the chips.
In a first aspect, an embodiment of the present application provides a method for offline testing a chip, including obtaining configuration information of a chip to be tested, where the configuration information includes: model and interface data of the chip to be tested; acquiring an input/output IO state corresponding to the configuration information from a memory through a microcontroller, and sending the IO state to a field programmable gate array module; and giving an IO state to an interface of the chip to be tested through the field programmable gate array module, and testing the chip to be tested.
In the embodiment of the application, the microcontroller and the field programmable gate array module cooperate to achieve the effect of rapidly realizing chip test by carrying out logic processing of configuration information and IO state transmission of the field programmable gate array module, and the independent chip test of the system is carried out by acquiring the configuration information to achieve the effect of off-line processing, so that the process of testing chips can be efficiently and accurately realized.
In some embodiments, before acquiring the configuration information of the chip to be tested, the method further includes: obtaining a test file corresponding to the model of the chip to be tested; analyzing the test file through the microcontroller to obtain a plurality of IO states, wherein the plurality of IO states comprise IO states; the plurality of IO states are stored by the memory.
In the embodiment of the application, the corresponding test file can be directly obtained according to the model of the chip to be tested, the offline processing effect can be realized after the analysis and the test of the system, and the chip test can be realized more conveniently.
In some embodiments, after the interface that gives the IO state to the chip to be tested through the field programmable gate array module and tests the chip to be tested, the method further includes: acquiring a return state of a chip to be tested; and analyzing the return state by the microcontroller and outputting the test result in real time.
In the embodiment of the application, the return state can be analyzed by the microcontroller, and the test result can be accurately output.
In some embodiments, obtaining, by the microcontroller, an input/output IO state corresponding to the configuration information from the memory, and sending the IO state to the field programmable gate array module, includes: acquiring an IO state corresponding to the model of the chip to be tested from a memory through a microcontroller; and analyzing and configuring the IO state through the microcontroller to obtain a high-low level state, and sending the high-low level state to the field programmable gate array module.
In the embodiment of the application, the connection between the field programmable gate array module and the IO interface can be realized through the transmission of the high-low level state, and the chip test can be accurately completed.
In some embodiments, the method for testing the chip to be tested by giving the IO state to the interface of the chip to be tested through the field programmable gate array module includes: and giving a high-low level state to an interface of the chip to be tested through the field programmable gate array module, and testing the chip to be tested to obtain a test result.
In the embodiment of the application, the interface of the chip to be tested can be endowed with a high-low level state through the field programmable gate array module, and the chip to be tested is subjected to high-school and accurate test.
In a second aspect, an embodiment of the present application provides a system for offline testing of chips, including:
a microcontroller module and a field programmable gate array module;
the microcontroller module is used for: acquiring an input/output IO state corresponding to configuration information of a chip to be tested from a memory, sending the IO state to a field programmable gate array module, receiving a return state of the chip to be tested sent by the field programmable gate array module, and analyzing the return state to obtain a test result;
the field programmable gate array module is used for: and receiving the IO state sent by the microcontroller module, giving the IO state to an interface of the chip to be tested, and obtaining a return state.
Optionally, the system further comprises:
the system comprises a man-machine interaction screen, a memory, an external communication interface and a parallel IO interface;
the man-machine interaction screen is used for: receiving a test result sent by the microcontroller module, displaying the test result, and providing an instruction for testing the chip to be tested for the microcontroller module;
the memory is used for: providing the IO status to the microcontroller module;
the external communication interface is used for: obtaining a test file corresponding to the model of the chip to be tested;
the parallel IO interface is used for: and connecting the chip to be tested.
In a third aspect, an embodiment of the present application provides an apparatus for offline testing a chip, including:
the device comprises an acquisition module, a processing module and a processing module, wherein the acquisition module is used for acquiring configuration information of a chip to be tested, and the configuration information comprises: model and interface data of the chip to be tested;
the transfer module is used for acquiring the input/output IO state corresponding to the configuration information from the memory through the microcontroller and sending the IO state to the field programmable gate array module;
the testing module is used for giving the IO state to the interface of the chip to be tested through the field programmable gate array module and testing the chip to be tested.
Optionally, the apparatus further includes:
the analyzing module is used for acquiring the test file corresponding to the model of the chip to be tested before the acquiring module acquires the configuration information of the chip to be tested;
analyzing the test file through the microcontroller to obtain a plurality of IO states, wherein the plurality of IO states comprise IO states;
the plurality of IO states are stored by the memory.
Optionally, the apparatus further includes:
the output module is used for acquiring the return state of the chip to be tested after the test module gives the IO state to the interface of the chip to be tested through the field programmable gate array module and tests the chip to be tested;
and analyzing the return state by the microcontroller and outputting the test result in real time.
Optionally, the transfer module is specifically configured to:
acquiring an IO state corresponding to the model of the chip to be tested from a memory through a microcontroller;
and analyzing and configuring the IO state through the microcontroller to obtain a high-low level state, and sending the high-low level state to the field programmable gate array module.
Optionally, the test module is specifically configured to:
and giving a high-low level state to an interface of the chip to be tested through the field programmable gate array module, and testing the chip to be tested to obtain a test result.
In a fourth aspect, an embodiment of the present application provides an electronic device comprising a processor and a memory storing computer readable instructions which, when executed by the processor, perform the steps of the method as provided in the first aspect above.
In a fifth aspect, an embodiment of the present application provides a readable storage medium having stored thereon a computer program which when executed by a processor performs the steps of the method as provided in the first aspect above.
Additional features and advantages of the application will be set forth in the description which follows, and in part will be apparent from the description, or may be learned by practice of the embodiments of the application. The objectives and other advantages of the application will be realized and attained by the structure particularly pointed out in the written description and claims thereof as well as the appended drawings.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are needed in the embodiments of the present application will be briefly described below, it should be understood that the following drawings only illustrate some embodiments of the present application and should not be considered as limiting the scope, and other related drawings can be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a flowchart of a method for offline testing a chip according to an embodiment of the present application;
FIG. 2 is a schematic block diagram of a system for offline testing of chips provided by an embodiment of the present application;
FIG. 3 is a schematic block diagram of an apparatus for offline testing of chips according to an embodiment of the present application;
fig. 4 is a schematic structural diagram of an apparatus for offline testing chips according to an embodiment of the present application.
Detailed Description
The following description of the embodiments of the present application will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present application, but not all embodiments. The components of the embodiments of the present application generally described and illustrated in the figures herein may be arranged and designed in a wide variety of different configurations. Thus, the following detailed description of the embodiments of the application, as presented in the figures, is not intended to limit the scope of the application, as claimed, but is merely representative of selected embodiments of the application. All other embodiments, which can be made by a person skilled in the art without making any inventive effort, are intended to be within the scope of the present application.
It should be noted that: like reference numerals and letters denote like items in the following figures, and thus once an item is defined in one figure, no further definition or explanation thereof is necessary in the following figures. Meanwhile, in the description of the present application, the terms "first", "second", and the like are used only to distinguish the description, and are not to be construed as indicating or implying relative importance.
Some of the terms involved in the embodiments of the present application will be described first to facilitate understanding by those skilled in the art.
FPGA (Field Programmable Gate Array) (field programmable gate array module): is a product of further development on the basis of programmable devices such as PAL (programmable array logic), GAL (general-purpose array logic) and the like. The programmable device is used as a semi-custom circuit in the field of Application Specific Integrated Circuits (ASICs), which not only solves the defect of custom circuits, but also overcomes the defect of limited gate circuits of the original programmable device.
ARM singlechip: the (micro controller) is a single-chip microcomputer taking the ARM processor as a core, and is an emerging product which appears in recent years along with the increasing degree of intellectualization and networking of electronic equipment. The arm singlechip gradually steps into the high-end market with the advantages of low power consumption and high cost performance, and becomes a current mainstream product.
WGL file: (test file) is an abbreviation for Waveform Generation Language. It is an editable text file; the ATPG program is generated by an ATPG program in an EDA tool set, and is a file convenient for ATE conversion; if the WGL file corresponds to a file in the ATE, the WGL file is a pin file, a timing file and a pattern file;
the application is applied to the scene of chip test, and the specific scene is the combination of ARM (microcontroller) and FPGA (field programmable gate array module), which are definitely divided into work, can be suitable for various different conditions, ARM is responsible for complex logic processing, FPGA is responsible for high-speed parallel port IO transmission, and finally realizes automatic identification of various WGL files and automatic and efficient completion of test.
At present, in the production and manufacturing process of chips, partial finished products are bad chips and cannot be normally used due to the complexity of manufacturing processes, huge process steps, environmental factors (no degree, environmental humidity, temperature and the like), and even mature processes can only ensure the yield of 95 percent and even lower. It must not be acceptable for the customer to sell these chips directly without any processing. ATE tests will be performed at various stages of the chip. However, during the test of ATE, a phenomenon of low yield of chips, that is, a phenomenon that a large number of chips are screened out by ATE due to test failure, is often encountered.
For this purpose, the application obtains the configuration information of the chip to be tested, wherein the configuration information comprises: model and interface data of the chip to be tested; acquiring an input/output IO state corresponding to the configuration information from a memory through a microcontroller, and sending the IO state to a field programmable gate array module; and giving an IO state to an interface of the chip to be tested through the field programmable gate array module, and testing the chip to be tested. The microcontroller and the field programmable gate array module cooperate to achieve the effect of rapidly realizing chip test by carrying out logic processing of configuration information and IO state transmission of the field programmable gate array module, and achieve the effect of off-line processing by obtaining the configuration information and carrying out independent chip test of the system, thereby realizing the process of testing chips efficiently and accurately.
In the embodiment of the application, the execution body may be an offline test chip device in an offline test chip system, and in practical application, the offline test chip device may be electronic devices such as a terminal device and a server, which is not limited herein.
The method for offline testing of chips according to an embodiment of the present application is described in detail below with reference to fig. 1.
Referring to fig. 1, fig. 1 is a flowchart of a method for offline testing a chip according to an embodiment of the present application, where the method for offline testing a chip shown in fig. 1 includes:
step 110: and acquiring configuration information of the chip to be tested.
Wherein the configuration information includes: the model and interface data of the chip to be tested, and the configuration information can also comprise information such as the name and material of the chip. The chip to be tested may be a chip carried in any machine or device.
In some embodiments of the present application, before obtaining the configuration information of the chip to be tested, the method further includes: obtaining a test file corresponding to the model of the chip to be tested; analyzing the test file through the microcontroller to obtain a plurality of IO states, wherein the plurality of IO states comprise IO states; the plurality of IO states are stored by the memory.
In the process, the corresponding test file can be directly obtained according to the model of the chip to be tested, the off-line processing effect can be realized after the analysis and the test of the system, and the chip test can be realized more conveniently.
The memory may also store various test data and test reports generated by the micro-control, among other things.
Step 120: and acquiring an input/output IO state corresponding to the configuration information from the memory through the microcontroller, and sending the IO state to the field programmable gate array module.
In some embodiments of the present application, obtaining, by a microcontroller, an input/output IO state corresponding to configuration information from a memory, and sending the IO state to a field programmable gate array module, includes: acquiring an IO state corresponding to the model of the chip to be tested from a memory through a microcontroller; and analyzing and configuring the IO state through the microcontroller to obtain a high-low level state, and sending the high-low level state to the field programmable gate array module.
In the process, the connection between the field programmable gate array module and the IO interface can be realized through the transmission of the high-low level state, and the chip test can be accurately completed.
The high-low level states include high level, low level, active high level and active low level.
Step 130: and giving an IO state to an interface of the chip to be tested through the field programmable gate array module, and testing the chip to be tested.
In some embodiments of the present application, an interface for giving an IO state to a chip to be tested through a field programmable gate array module, the testing of the chip to be tested includes: and giving a high-low level state to an interface of the chip to be tested through the field programmable gate array module, and testing the chip to be tested to obtain a test result.
In the process, the high-low level state can be endowed to the interface of the chip to be tested through the field programmable gate array module, and the chip to be tested is subjected to college and accurate test.
In some embodiments of the present application, after the interface for giving the IO status to the chip to be tested by the field programmable gate array module, the method further includes: acquiring a return state of a chip to be tested; and analyzing the return state by the microcontroller and outputting the test result in real time.
In the process, the application can analyze the return state through the microcontroller and accurately output the test result.
In one embodiment, when all the chip tests are not completed, the steps 110-140 are re-executed, and the tests of the incomplete test chips are performed one by one.
In the process shown in fig. 1, the configuration information of the chip to be tested is obtained, where the configuration information includes: model and interface data of the chip to be tested; acquiring an input/output IO state corresponding to the configuration information from a memory through a microcontroller, and sending the IO state to a field programmable gate array module; and giving an IO state to an interface of the chip to be tested through the field programmable gate array module, and testing the chip to be tested. The microcontroller and the field programmable gate array module cooperate to achieve the effect of rapidly realizing chip test by carrying out logic processing of configuration information and IO state transmission of the field programmable gate array module, and achieve the effect of off-line processing by obtaining the configuration information and carrying out independent chip test of the system, thereby realizing the process of testing chips efficiently and accurately.
The system for offline testing of chips according to an embodiment of the present application is described in detail below with reference to fig. 2.
Referring to fig. 2, fig. 2 is a schematic block diagram of a system for offline testing chips according to an embodiment of the present application, where the system for offline testing chips shown in fig. 2 includes:
a microcontroller module and a field programmable gate array module;
the microcontroller module is used for: acquiring an input/output IO state corresponding to configuration information of a chip to be tested from a memory, sending the IO state to a field programmable gate array module, receiving a return state of the chip to be tested sent by the field programmable gate array module, and analyzing the return state to obtain a test result;
the field programmable gate array module is used for: and receiving the IO state sent by the microcontroller module, giving the IO state to an interface of the chip to be tested, and obtaining a return state.
Specifically, the microcontroller is further used for completing analysis and storage of the test file into a memory (DDR storage module), acquiring information sent in the memory storage in the test process, simultaneously controlling information interaction of the man-machine interaction interface, completing control of the field programmable gate array module and completing complex data analysis and logic processing.
Optionally, the system further comprises:
the system comprises a man-machine interaction screen, a memory, an external communication interface and a parallel IO interface;
the man-machine interaction screen is used for: receiving a test result sent by the microcontroller module, displaying the test result, and providing an instruction for testing the chip to be tested for the microcontroller module;
the memory is used for: providing the IO status to the microcontroller module;
the external communication interface is used for: obtaining a test file corresponding to the model of the chip to be tested;
the parallel IO interface is used for: and connecting the chip to be tested.
Specific: the external communication interface is also used for connecting data interaction between the external upper computer and the microcontroller.
Optionally, the system is connected with a test file transmission upper computer and a chip to be tested.
When the chip designer gives the test files to the chip designer, the test files are loaded in the test system by the module, each test file is only loaded once, and the test files can be used in the system permanently later, so that the offline effect is realized.
Specific: and selecting a test file to be imported from the upper computer, then connecting the system to the system, and clicking a key to start importing the system. And the system microcontroller is responsible for receiving and analyzing the test file, converting the test format into the beat and transmitting the IO state data, storing the IO state data into a test system memory, and displaying the importing state and the progress in real time by the upper computer. Each test file only needs to be imported once. The test system stores a plurality of test files. The specific number depends on the memory size.
The method of off-line testing the chip was described above with reference to fig. 1, and the apparatus for off-line testing the chip is described below with reference to fig. 3 to 4.
Referring to fig. 3, a schematic block diagram of an apparatus 300 for offline testing of chips is provided in an embodiment of the present application, where the apparatus 300 may be a module, a program segment, or a code on an electronic device. The apparatus 300 corresponds to the embodiment of the method of fig. 1 described above, and is capable of performing the steps involved in the embodiment of the method of fig. 1. Specific functions of the apparatus 300 will be described below, and detailed descriptions thereof will be omitted herein as appropriate to avoid redundancy.
Optionally, the apparatus 300 includes:
the obtaining module 310 is configured to obtain configuration information of a chip to be tested, where the configuration information includes: model and interface data of the chip to be tested;
the transfer module 320 is configured to obtain, from the memory, an input/output IO state corresponding to the configuration information through the microcontroller, and send the IO state to the field programmable gate array module;
the testing module 330 is configured to give the IO status to the interface of the chip to be tested through the field programmable gate array module, and test the chip to be tested.
Optionally, the apparatus further includes:
the analyzing module is used for acquiring the test file corresponding to the model of the chip to be tested before the acquiring module acquires the configuration information of the chip to be tested; analyzing the test file through the microcontroller to obtain a plurality of IO states, wherein the plurality of IO states comprise IO states; the plurality of IO states are stored by the memory.
Optionally, the apparatus further includes:
the output module is used for acquiring the return state of the chip to be tested after the test module gives the IO state to the interface of the chip to be tested through the field programmable gate array module and tests the chip to be tested; and analyzing the return state by the microcontroller and outputting the test result in real time.
Optionally, the transfer module is specifically configured to:
acquiring an IO state corresponding to the model of the chip to be tested from a memory through a microcontroller; and analyzing and configuring the IO state through the microcontroller to obtain a high-low level state, and sending the high-low level state to the field programmable gate array module.
Optionally, the test module is specifically configured to:
and giving a high-low level state to an interface of the chip to be tested through the field programmable gate array module, and testing the chip to be tested to obtain a test result.
Referring to fig. 4, a schematic block diagram of an apparatus for offline testing of chips according to an embodiment of the present application may include a memory 410 and a processor 420. Optionally, the apparatus may further include: a communication interface 430 and a communication bus 440. The apparatus corresponds to the embodiment of the method of fig. 1 described above, and is capable of performing the steps involved in the embodiment of the method of fig. 1, and specific functions of the apparatus may be found in the following description.
In particular, the memory 410 is used to store computer readable instructions.
The processor 420, which processes the readable instructions stored in the memory, is capable of performing the various steps in the method of fig. 1.
Communication interface 430 is used for signaling or data communication with other node devices. For example: for communication with a server or terminal, or with other device nodes, although embodiments of the application are not limited in this regard.
A communication bus 440 for enabling direct connection communication of the above-described components.
The communication interface 430 of the device in the embodiment of the present application is used for performing signaling or data communication with other node devices. The memory 410 may be a high-speed RAM memory or a non-volatile memory (non-volatile memory), such as at least one disk memory. Memory 410 may also optionally be at least one storage device located remotely from the aforementioned processor. The memory 410 has stored therein computer readable instructions which, when executed by the processor 420, perform the method process described above in fig. 1. Processor 420 may be used on apparatus 300 and to perform functions in the present application. By way of example, the processor 420 described above may be a general purpose processor, a digital signal processor (Digital Signal Processor, DSP), an application specific integrated circuit (Application Specific Integrated Circuit, ASIC), an off-the-shelf programmable gate array (Field Programmable Gate Array, FPGA) or other programmable logic device, discrete gate or transistor logic device, discrete hardware components, and the embodiments of the application are not limited in this regard.
Embodiments of the present application also provide a readable storage medium, which when executed by a processor, performs a method process performed by an electronic device in the method embodiment shown in fig. 1.
It will be clear to those skilled in the art that, for convenience and brevity of description, reference may be made to the corresponding procedure in the foregoing method for the specific working procedure of the apparatus described above, and this will not be repeated here.
In summary, the embodiments of the present application provide a method, a system, an apparatus, a device, and a storage medium for offline testing a chip, where the method includes obtaining configuration information of a chip to be tested, where the configuration information includes: model and interface data of the chip to be tested; acquiring an input/output IO state corresponding to the configuration information from a memory through a microcontroller, and sending the IO state to a field programmable gate array module; and giving an IO state to an interface of the chip to be tested through the field programmable gate array module, and testing the chip to be tested. The method can achieve the effect of efficiently and accurately testing the chip.
In the several embodiments provided in the present application, it should be understood that the disclosed apparatus and method may be implemented in other manners. The apparatus embodiments described above are merely illustrative, for example, of the flowcharts and block diagrams in the figures that illustrate the architecture, functionality, and operation of possible implementations of apparatus, methods and computer program products according to various embodiments of the present application. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of code, which comprises one or more executable instructions for implementing the specified logical function(s). It should also be noted that in some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams and/or flowchart illustration, and combinations of blocks in the block diagrams and/or flowchart illustration, can be implemented by special purpose hardware-based systems which perform the specified functions or acts, or combinations of special purpose hardware and computer instructions.
In addition, functional modules in the embodiments of the present application may be integrated together to form a single part, or each module may exist alone, or two or more modules may be integrated to form a single part.
The functions, if implemented in the form of software functional modules and sold or used as a stand-alone product, may be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application may be embodied essentially or in a part contributing to the prior art or in a part of the technical solution, in the form of a software product stored in a storage medium, comprising several instructions for causing a computer device (which may be a personal computer, a server, a network device, etc.) to perform all or part of the steps of the method according to the embodiments of the present application. And the aforementioned storage medium includes: a U-disk, a removable hard disk, a Read-Only Memory (ROM), a random access Memory (RAM, random Access Memory), a magnetic disk, or an optical disk, or other various media capable of storing program codes.
The above description is only an example of the present application and is not intended to limit the scope of the present application, and various modifications and variations will be apparent to those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application should be included in the protection scope of the present application. It should be noted that: like reference numerals and letters denote like items in the following figures, and thus once an item is defined in one figure, no further definition or explanation thereof is necessary in the following figures.
The foregoing is merely illustrative of the present application, and the present application is not limited thereto, and any person skilled in the art will readily recognize that variations or substitutions are within the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.
It is noted that relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.
Claims (10)
1. A method of off-line testing of a chip, comprising:
obtaining configuration information of a chip to be tested, wherein the configuration information comprises: model and interface data of the chip to be tested;
acquiring an input/output IO state corresponding to the configuration information from a memory through a microcontroller, and sending the IO state to a field programmable gate array module;
and giving the IO state to an interface of the chip to be tested through the field programmable gate array module, and testing the chip to be tested.
2. The method of claim 1, wherein prior to the obtaining the configuration information of the chip under test, the method further comprises:
obtaining a test file corresponding to the model of the chip to be tested;
analyzing the test file through the microcontroller to obtain a plurality of IO states, wherein the plurality of IO states comprise the IO state;
storing the plurality of IO states by the memory.
3. The method according to claim 1 or 2, wherein after the interface giving the IO status to the chip under test by the field programmable gate array module, the method further comprises:
acquiring the return state of the chip to be tested;
and analyzing the return state by the microcontroller and outputting a test result in real time.
4. The method according to claim 1 or 2, wherein the obtaining, by the microcontroller, the input/output IO state corresponding to the configuration information from the memory, and sending the IO state to the field programmable gate array module, includes:
acquiring the IO state corresponding to the model of the chip to be tested from a memory through a microcontroller;
and analyzing and configuring the IO state through a microcontroller to obtain a high-low level state, and sending the high-low level state to the field programmable gate array module.
5. The method of claim 4, wherein the interface that gives the IO status to the chip under test through the field programmable gate array module, testing the chip under test, comprises:
and giving the high-low level state to an interface of the chip to be tested through the field programmable gate array module, and testing the chip to be tested to obtain a test result.
6. A system for off-line testing of chips, comprising:
a microcontroller module and a field programmable gate array module;
the microcontroller module is used for: acquiring an input/output IO state corresponding to configuration information of a chip to be tested from a memory, sending the IO state to a field programmable gate array module, receiving a return state of the chip to be tested sent by the field programmable gate array module, and analyzing the return state to obtain a test result;
the field programmable gate array module is configured to: and receiving the IO state sent by the microcontroller module, and giving the IO state to an interface of the chip to be tested to obtain the return state.
7. The system of claim 6, wherein the system further comprises:
the system comprises a man-machine interaction screen, a memory, an external communication interface and a parallel IO interface;
the man-machine interaction screen is used for: receiving a test result sent by the microcontroller module, displaying the test result, and providing an instruction for testing the chip to be tested for the microcontroller module;
the memory is used for: providing the IO status to the microcontroller module;
the external communication interface is used for: obtaining a test file corresponding to the model of the chip to be tested;
the parallel IO interface is used for: and connecting the chip to be tested.
8. An apparatus for off-line testing of chips, comprising:
the device comprises an acquisition module, a processing module and a processing module, wherein the acquisition module is used for acquiring configuration information of a chip to be tested, and the configuration information comprises: model and interface data of the chip to be tested;
the transfer module is used for acquiring the input/output IO state corresponding to the configuration information from the memory through the microcontroller and sending the IO state to the field programmable gate array module;
and the testing module is used for giving the IO state to the interface of the chip to be tested through the field programmable gate array module and testing the chip to be tested.
9. An electronic device, comprising:
a memory and a processor, the memory storing computer readable instructions that, when executed by the processor, perform the steps in the method of any of claims 1-5.
10. A computer-readable storage medium, comprising:
computer program which, when run on a computer, causes the computer to perform the method according to any one of claims 1-5.
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