CN109542707A - Test code generating method and system based on register - Google Patents
Test code generating method and system based on register Download PDFInfo
- Publication number
- CN109542707A CN109542707A CN201811468952.0A CN201811468952A CN109542707A CN 109542707 A CN109542707 A CN 109542707A CN 201811468952 A CN201811468952 A CN 201811468952A CN 109542707 A CN109542707 A CN 109542707A
- Authority
- CN
- China
- Prior art keywords
- register
- port
- array
- dut
- test code
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
- G06F11/2273—Test methods
Landscapes
- Engineering & Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Computer Hardware Design (AREA)
- Quality & Reliability (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Debugging And Monitoring (AREA)
Abstract
The present invention provides a kind of test code generating method and system based on register, the described method includes: S1, parsing DUT top document and register definitions file, extract the input/output port signal that configuration port register and port record register are connected；S2, the input/output port signal and register definitions file connected according to configuration port register and port record register, generate the test code of configuration port register and port record register.The present invention records register for configuration port register and port, can automatically generate test code by the top document and register definitions file that parse DUT, improve testing efficiency, ensured test quality, and have good reusability.
Description
Technical field
The present invention relates to digital integrated electronic circuit verification technique fields, more particularly to a kind of test code based on register
Generation method and system.
Background technique
SoC (System on a Chip, system on chip) chip typically refer to include CPU He other a variety of submodules core
Piece can complete a series of relatively complete functions relatively independently.It usually there will be the control for configuring other modules in SoC chip
Signal processed and the register for recording other module working conditions.The more complicated SoC chip of function generally comprises complexity and compares
High numerous submodules, and this often means that the port configuration registers needed and port record register number can be bigger
(hundreds of thousands of be all possible situation).
It is tested if going to write SystemVerilog (SV language) code manually directly against each register, it is right
It need to be to do is in each register: 1) determining that function phases need naked eyes to go to find out the port that each field of register is connected
And sort out；2) it is gone to write corresponding test code according to the function type of each field and institute connectivity port.Specifically, for
Whether configuration port register needs to the register assignment and checks corresponding output port with the respective field one in register
Cause, for port record register need to respective input poll tax on children value and read the register see its respective field value whether with
Just now the input port of assignment was consistent.With the increase of register and port number, the code for writing the method for code manually is write
Amount and debug time can be linearly increasing, and the probability for mistake occur is consequently increased.
In addition, the frame of test and excitation can be generated in universal test code generating method in the prior art, but can not be automatic
Extract the generation of the register and port and realization concrete function test code of specific function.
Therefore, in view of the above technical problems, it is necessary to a kind of test code generating method based on register be provided and be
System.
Summary of the invention
In view of this, the purpose of the present invention is to provide a kind of test code generating method and system based on register.
To achieve the goals above, the technical solution that one embodiment of the invention provides is as follows:
A kind of test code generating method based on register, which comprises
S1, parsing DUT top document and register definitions file extract configuration port register and port record deposit
The input/output port signal that device is connected；
S2, the input/output port signal and register connected according to configuration port register and port record register
File is defined, the test code of configuration port register and port record register is generated.
As a further improvement of the present invention, the step S1 includes:
S11, DUT top document and register definitions file are obtained；
S12, parsing DUT top document obtain the list of DUT output port and are stored in the first array, obtain DUT input port
List is simultaneously stored in the second array；Register definitions file is parsed, register field name list is obtained and is stored in third array；
S13, third array is inquired with the first array, the DUT output port occurred in third array deposit first is defeated
Array out；Third array is inquired with the second array, by the DUT input port occurred in third array deposit the second output number
Group.
As a further improvement of the present invention, the step S2 includes:
S21, the test generation that all DUT output port signals in the first output array are generated with configuration port register
Code；
S22, the test generation that all DUT input port signals in the second output array are generated with port record register
Code.
As a further improvement of the present invention, the step S21 specifically:
First generate a random number；
The random number write-in of generation is measured and sets port register；
The value for the output port for waiting the configuration port register to be connected is equal to the value of expected register respective field,
And timing is carried out, if being more than the value of preset clock cycle output port still without reporting an error and tying equal to expected value
Beam emulation.
As a further improvement of the present invention, the step S22 specifically:
By the signal assignment of surveyed port record register connection at a random value；
Wait the preset clock cycle；
It reads the value of corresponding port record register and checks whether corresponding field is equal to connected input port
Value, if unequal, report an error and terminates to emulate.
As a further improvement of the present invention, the step S13 further include:
Judge to configure in port register and port record register field name and input/output port title whether phase
Together, if it is not identical, by field name and input/output port title according to uniform rules batch processing to identical.
As a further improvement of the present invention, the DUT top document in the step S1 and register definitions file pass through
Perl script is parsed.
Another embodiment of the present invention provides technical solution it is as follows:
A kind of test code generating system based on register, the system comprises:
Information extraction unit extracts configuration port register for parsing DUT top document and register definitions file
The input/output port signal connected with port record register；
Code generating unit is tested, the input for being connected according to configuration port register and port record register is defeated
Exit port signal and register definitions file generate the test code of configuration port register and port record register.
As a further improvement of the present invention, the information extraction unit is also used to:
Obtain DUT top document and register definitions file；
DUT top document is parsed, the list of DUT output port is obtained and is stored in the first array, obtains the list of DUT input port
And it is stored in the second array；Register definitions file is parsed, register field name list is obtained and is stored in third array；
Third array is inquired with the first array, by the DUT output port occurred in third array deposit the first output number
Group；Third array is inquired with the second array, by the DUT input port occurred in third array deposit the second output array.
As a further improvement of the present invention, the test code generating unit is also used to:
All DUT output port signals in first output array are generated with the test code of configuration port register；
All DUT input port signals in second output array are generated with the test code of port record register.
The invention has the following advantages:
Register is recorded for configuration port register and port, by the top document and register definitions that parse DUT
File can automatically generate test code, improve testing efficiency, ensure test quality, and have good reusability.
Detailed description of the invention
In order to more clearly explain the embodiment of the invention or the technical proposal in the existing technology, to embodiment or will show below
There is attached drawing needed in technical description to be briefly described, it should be apparent that, the accompanying drawings in the following description is only this
The some embodiments recorded in invention, for those of ordinary skill in the art, without creative efforts,
It is also possible to obtain other drawings based on these drawings.
Fig. 1 is the flow diagram of the test code generating method in the present invention based on register；
Fig. 2 is the module diagram of the test code generating system in the present invention based on register；
Fig. 3 is the flow diagram of the test code generating method in a specific embodiment of the invention based on register；
Fig. 4 is the exemplary diagram of register definitions file in a specific embodiment of the invention；
Fig. 5 is the exemplary diagram that configuration port register tests code in a specific embodiment of the invention；
Fig. 6 is the exemplary diagram that a specific embodiment middle port of the invention records register testing code.
Specific embodiment
Technical solution in order to enable those skilled in the art to better understand the present invention, below in conjunction with of the invention real
The attached drawing in example is applied, technical scheme in the embodiment of the invention is clearly and completely described, it is clear that described implementation
Example is only a part of the embodiment of the present invention, instead of all the embodiments.Based on the embodiments of the present invention, this field is common
Technical staff's every other embodiment obtained without making creative work, all should belong to protection of the present invention
Range.
The invention discloses a kind of test code generating method and system based on register, by DUT (design
Under test, design to be measured) top document and register definitions file automatically parse out configuration port register and port note
Register information is recorded, and automatically generates corresponding test code.
Join shown in Fig. 1, the test code generating method based on register is divided into information extraction and test code building two
Point, comprising:
S1, parsing DUT top document and register definitions file extract configuration port register and port record deposit
The input/output port signal that device is connected；
S2, the input/output port signal and register connected according to configuration port register and port record register
File is defined, the test code of configuration port register and port record register is generated.
Two kinds of registers involved in the present invention:
1) configure port register: the value of each field of this register can be transmitted to corresponding output port, and CPU can be with
This register is modified to change the value of output port, these output port signals are commonly used in other modules of control/configuration；
2) port records register: each field value of this register is equal to corresponding input port signal, and CPU can be with
The value of this register is read to check the value of corresponding input port, commonly used in recording the state letter that other modules are brought
Breath.
Preferably, step S1 includes:
S11, DUT top document and register definitions file are obtained；
S12, parsing DUT top document obtain the list of DUT output port and are stored in the first array, obtain DUT input port
List is simultaneously stored in the second array；Register definitions file is parsed, register field name list is obtained and is stored in third array；
S13, third array is inquired with the first array, the DUT output port occurred in third array deposit first is defeated
Array out；Third array is inquired with the second array, by the DUT input port occurred in third array deposit the second output number
Group.
Preferably, step S2 includes:
S21, the test generation that all DUT output port signals in the first output array are generated with configuration port register
Code；
S22, the test generation that all DUT input port signals in the second output array are generated with port record register
Code.
Accordingly, join shown in Fig. 2, the test code generating system based on register includes:
Information extraction unit 10 extracts the deposit of configuration port for parsing DUT top document and register definitions file
The input/output port signal that device and port record register are connected；
Code generating unit 20 is tested, the input for being connected according to configuration port register and port record register
Output port signal and register definitions file generate the test code of configuration port register and port record register.
Below in conjunction with specific embodiment, the present invention is described in detail.
Join shown in Fig. 3, the test code generating method based on register in a specific embodiment of the invention, including following step
It is rapid:
Information extraction link parses DUT top document and register definitions file, extracts configuration port register and end
The input/output port signal that mouth record register is connected.
The link is divided into three steps, specifically:
The first step obtains DUT top document and register definitions file.
Ginseng Fig. 4 show register definitions file example in the present embodiment, longitudinal four column be respectively register title,
Location, field name, bit range.
Second step parses DUT top document, obtains the list of DUT output port and is stored in the first array, obtains DUT input
Port list is simultaneously stored in the second array；Register definitions file is parsed, register field name list is obtained and is stored in third number
Group.
In the present embodiment, DUT top document is parsed, matches " output " keyword in DUT top document, it will thereafter
The DUT output port followed is saved into the first array；Match DUT top document in " input " keyword, by followed by
DUT input port is saved into the second array.Register definitions file is parsed, all register words name sections are extracted and is stored in the
Three arrays.
DUT top document and register definitions file pass through perl script (PracticalExtraction in the present embodiment
And Reporting Language, a kind of scripting language) it is parsed, other modes can also be used in other embodiments
It is parsed.
Third step inquires third array with the first array, judges whether each output port title occurs in the first array
In third array, the DUT output port occurred in third array (i.e. the port that is configured of configuration port register) is deposited
Enter the first output array；Third array is inquired with the second array, judges whether each input port title occurs in the second array
In third array, the DUT input port occurred in third array (i.e. port records the port that register is recorded) is deposited
Enter the second output array.
Third step implied condition is these two types of registers in register definitions file under normal conditions in the present embodiment
The title of respective field and the title of corresponding input/output port are identical, if configuration port register and port record deposit
Field name and input/output port title be not directly identical in device, but has other Uniform Name rules, then in third step
It can be first by port name according to being searched again after uniform rules batch processing.
Code building link is tested, the input/output terminal connected according to configuration port register and port record register
Message number and register definitions file generate the test code of configuration port register and port record register.
This link to be obtained according to a upper link first output array, second output array in signal list and
The information such as position range of each field generate corresponding SystemVerilog and test code in register definitions file.It is identical to test
Card environment under only need disposably be arranged test Code Template, so that it may automatically generated under modules both registers from
Dynamic test code.
What it is for the port generation in the first output array is the test code for configuring port register, specifically, right
Each register belonging to signal generates following test code:
The first step first generates random number (in corresponding diagram 5 the 1st be about to random value be stored in write_data variable)；
Second step, by the random number of generation be written surveyed register (in corresponding diagram 5 the 2nd row calling cpu_write this
Config_reg register is written in write_data by task)；
Third step, the value for the output port for waiting the register to be connected are equal to the value of expected register respective field,
Clocked operation is done at the same time, if being more than given time output port still without being equal to expected value, is reported an error and is tied
(3-14 row, waits the port config_0 within the timeout_cycle given clock cycle in corresponding diagram 5 for beam emulation
Value is equal to write_data [31:16], the value of the port config_1 is equal to write_data [16:0], reports an error less than if if waiting).
The port generation in array is exported for second is the test code of port record register, specifically, right
Each register belonging to signal generates following test code:
The first step, by the signal assignment of surveyed register connection, at a random value, (the 1st row, is incited somebody to action in corresponding diagram 6
The port status_0 assignment is at random value)；
Second step waits given clock cycle (the 2nd row, waits wait_cycle clock cycle in corresponding diagram 6)；
Third step reads the value of corresponding port record register and checks whether corresponding field is equal to connected input
The value of port reports an error if unequal and terminates emulation (3-7 row in corresponding diagram 6 reads the value of status_reg register
Read_data variable is arrived out, judges whether read_data [31:0] is equal to the port status_0 later, is reported if unequal
It is wrong).
Usually there is large number of configuration port register and port record register, these two types deposit in SoC system
Device is respectively provided with determining functional mode, traditional to go to write the method for test code to each register manpower there are code writings
And the workload of code debugging is very big, and is easy the problem of malfunctioning, the present invention only needs to provide the top document and register of DUT
The test code of above-mentioned two classes register can be automatically generated by defining file, greatly improve verification efficiency and effective guarantee
Test quality.
The solution of the present invention is ok in multiple modules comprising above-mentioned two classes register under given verification environment
It directly uses, test generation can be generated using this method by only needing to make a small amount of modification in part verification environment variation
Code, reusability are good.
As can be seen from the above technical solutions, the invention has the following advantages that
Register is recorded for configuration port register and port, by the top document and register definitions that parse DUT
File can automatically generate test code, improve testing efficiency, ensure test quality, and have good reusability.
System, device, module or the unit that above-described embodiment illustrates can specifically realize by computer chip or entity,
Or it is realized by the product with certain function.
For convenience of description, it is divided into various modules when description apparatus above with function to describe respectively.Certainly, implementing this
The function of each module can be realized in the same or multiple software and or hardware when specification one or more embodiment.
It should also be noted that, the terms "include", "comprise" or its any other variant are intended to nonexcludability
It include so that the process, method, commodity or the equipment that include a series of elements not only include those elements, but also to wrap
Include other elements that are not explicitly listed, or further include for this process, method, commodity or equipment intrinsic want
Element.In the absence of more restrictions, the element limited by sentence " including one ... ", it is not excluded that including described
There is also other identical elements in the process, method of element, commodity or equipment.
It will be understood by those skilled in the art that the embodiment of this specification one or more embodiment can provide as method, be
System or computer program product.Therefore, complete hardware embodiment, complete software can be used in this specification one or more embodiment
The form of embodiment or embodiment combining software and hardware aspects.Moreover, this specification one or more embodiment can be used
In computer-usable storage medium (the including but not limited to disk that one or more wherein includes computer usable program code
Memory, CD-ROM, optical memory etc.) on the form of computer program product implemented.
This specification one or more embodiment can computer executable instructions it is general on
It hereinafter describes, such as program module.Generally, program module includes executing particular task or realization particular abstract data type
Routine, programs, objects, component, data structure etc..Can also practice in a distributed computing environment this specification one or
Multiple embodiments, in these distributed computing environments, by being executed by the connected remote processing devices of communication network
Task.In a distributed computing environment, the local and remote computer that program module can be located at including storage equipment is deposited
In storage media.
It is obvious to a person skilled in the art that invention is not limited to the details of the above exemplary embodiments, Er Qie
In the case where without departing substantially from spirit or essential attributes of the invention, the present invention can be realized in other specific forms.Therefore, no matter
From the point of view of which point, the present embodiments are to be considered as illustrative and not restrictive, and the scope of the present invention is by appended power
Benefit requires rather than above description limits, it is intended that all by what is fallen within the meaning and scope of the equivalent elements of the claims
Variation is included within the present invention.Any reference signs in the claims should not be construed as limiting the involved claims.
In addition, it should be understood that although this specification is described in terms of embodiments, but not each embodiment is only wrapped
Containing an independent technical solution, this description of the specification is merely for the sake of clarity, and those skilled in the art should
It considers the specification as a whole, the technical solutions in the various embodiments may also be suitably combined, forms those skilled in the art
The other embodiments being understood that.
Claims (10)
1. a kind of test code generating method based on register, which is characterized in that the described method includes:
S1, parsing DUT top document and register definitions file extract configuration port register and port record register institute
The input/output port signal of connection；
S2, the input/output port signal and register definitions that register is connected are recorded according to configuration port register and port
File generates the test code of configuration port register and port record register.
2. test code generating method according to claim 1, which is characterized in that the step S1 includes:
S11, DUT top document and register definitions file are obtained；
S12, parsing DUT top document obtain the list of DUT output port and are stored in the first array, obtain the list of DUT input port
And it is stored in the second array；Register definitions file is parsed, register field name list is obtained and is stored in third array；
S13, third array is inquired with the first array, by the DUT output port occurred in third array deposit the first output number
Group；Third array is inquired with the second array, by the DUT input port occurred in third array deposit the second output array.
3. test code generating method according to claim 2, which is characterized in that the step S2 includes:
S21, the test code that all DUT output port signals in the first output array are generated with configuration port register；
S22, the test code that all DUT input port signals in the second output array are generated with port record register.
4. test code generating method according to claim 3, which is characterized in that the step S21 specifically:
First generate a random number；
The random number write-in of generation is measured and sets port register；
The value for the output port for waiting the configuration port register to be connected is equal to the value of expected register respective field, goes forward side by side
Row timing, if being more than the value of preset clock cycle output port still without reporting an error and terminating to imitate equal to expected value
Very.
5. test code generating method according to claim 3, which is characterized in that the step S22 specifically:
By the signal assignment of surveyed port record register connection at a random value；
Wait the preset clock cycle；
It reads the value of corresponding port record register and checks whether corresponding field is equal to the value of connected input port, if
It is unequal, then it reports an error and terminates to emulate.
6. test code generating method according to claim 2, which is characterized in that the step S13 further include:
Whether identical judge to configure field name and input/output port title in port register and port record register, if
It is not identical, then by field name and input/output port title according to uniform rules batch processing to identical.
7. test code generating method according to claim 1, which is characterized in that the DUT top layer text in the step S1
Part and register definitions file are parsed by perl script.
8. a kind of test code generating system based on register, which is characterized in that the system comprises:
Information extraction unit extracts configuration port register and end for parsing DUT top document and register definitions file
The input/output port signal that mouth record register is connected；
Code generating unit is tested, the input/output terminal for being connected according to configuration port register and port record register
Message number and register definitions file generate the test code of configuration port register and port record register.
9. test code generating system according to claim 8, which is characterized in that the information extraction unit is also used to:
Obtain DUT top document and register definitions file；
DUT top document is parsed, the list of DUT output port obtained and is stored in the first array, obtain the list of DUT input port and deposit
Enter the second array；Register definitions file is parsed, register field name list is obtained and is stored in third array；
Third array is inquired with the first array, by the DUT output port occurred in third array deposit the first output array；With
Second array inquires third array, by the DUT input port occurred in third array deposit the second output array.
10. test code generating system according to claim 9, which is characterized in that the test code generating unit is also
For:
All DUT output port signals in first output array are generated with the test code of configuration port register；
All DUT input port signals in second output array are generated with the test code of port record register.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811468952.0A CN109542707A (en) | 2018-12-03 | 2018-12-03 | Test code generating method and system based on register |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811468952.0A CN109542707A (en) | 2018-12-03 | 2018-12-03 | Test code generating method and system based on register |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN109542707A true CN109542707A (en) | 2019-03-29 |
Family
ID=65853594
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201811468952.0A Withdrawn CN109542707A (en) | 2018-12-03 | 2018-12-03 | Test code generating method and system based on register |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN109542707A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111861858A (en) * | 2020-07-10 | 2020-10-30 | 浪潮(北京)电子信息产业有限公司 | Method and device for starting image compression function verification and related equipment |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20040073839A1 (en) * | 2002-10-11 | 2004-04-15 | Toros Zeynep M. | Software programmable verification tool having a single built-in self-test (BIST) module for testing and debugging multiple memory modules in a device under test (DUT) |
| CN106294052A (en) * | 2016-07-25 | 2017-01-04 | 北京联盛德微电子有限责任公司 | The method of testing of a kind of depositor read-write and device |
| CN106484415A (en) * | 2016-10-08 | 2017-03-08 | 武汉瑞纳捷电子技术有限公司 | A kind of register configuration code automatic generation method and device |
| CN107104827A (en) * | 2017-04-12 | 2017-08-29 | 上海斐讯数据通信技术有限公司 | DMZ method for automatically testing functions and system based on Socket |
| CN107436762A (en) * | 2017-07-03 | 2017-12-05 | 北京东土军悦科技有限公司 | A kind of register Code document generating method, device and electronic equipment |
-
2018
- 2018-12-03 CN CN201811468952.0A patent/CN109542707A/en not_active Withdrawn
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20040073839A1 (en) * | 2002-10-11 | 2004-04-15 | Toros Zeynep M. | Software programmable verification tool having a single built-in self-test (BIST) module for testing and debugging multiple memory modules in a device under test (DUT) |
| CN106294052A (en) * | 2016-07-25 | 2017-01-04 | 北京联盛德微电子有限责任公司 | The method of testing of a kind of depositor read-write and device |
| CN106484415A (en) * | 2016-10-08 | 2017-03-08 | 武汉瑞纳捷电子技术有限公司 | A kind of register configuration code automatic generation method and device |
| CN107104827A (en) * | 2017-04-12 | 2017-08-29 | 上海斐讯数据通信技术有限公司 | DMZ method for automatically testing functions and system based on Socket |
| CN107436762A (en) * | 2017-07-03 | 2017-12-05 | 北京东土军悦科技有限公司 | A kind of register Code document generating method, device and electronic equipment |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111861858A (en) * | 2020-07-10 | 2020-10-30 | 浪潮(北京)电子信息产业有限公司 | Method and device for starting image compression function verification and related equipment |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN101093521B (en) | FPGA emulation device and method | |
| US7770066B2 (en) | Method and system for converting USB | |
| CN111428431B (en) | Automatic test and recording method and system supporting EDA software | |
| CN107526676B (en) | Cross-system test method and device | |
| CN111965530A (en) | JTAG-based FPGA chip automatic test method | |
| CN113342583B (en) | Chip verification system, method, device, equipment and storage medium | |
| CN109743301A (en) | A kind of data receiving-transmitting system and method based on Modbus agreement | |
| CN115656792B (en) | Test method and test platform for chip testability design | |
| CN103036734A (en) | Logic verification method and logic verification system for network chip | |
| CN106294144A (en) | Generation method, system and the server of the test vector of serial communication protocol | |
| CN112732508A (en) | Zynq-based configurable general IO test system and test method | |
| CN114816980A (en) | Automatic testing device and method for embedded communication system | |
| CN115684896A (en) | Chip testability design test method, test platform, and generation method and device thereof | |
| CN112084802A (en) | RFID tag chip verification system | |
| CN115576768A (en) | Universal verification platform architecture automatic generation method based on UVM | |
| CN107622017A (en) | A kind of analytic method of general automation software test | |
| CN109542707A (en) | Test code generating method and system based on register | |
| CN115684894B (en) | Test method and test platform for chip testability design | |
| CN115684895B (en) | Chip testability design test method, test platform, and generation method and device thereof | |
| CN116956801A (en) | Chip verification method, device, computer equipment and storage medium | |
| CN115421020A (en) | Method for generating test signal of integrated circuit and test method | |
| CN113177388B (en) | Device, system and method for testing and verifying IP (Internet protocol) core | |
| CN115470106A (en) | Verification method and system for reconfigurable chip | |
| CN108802600A (en) | A kind of integrated circuit verification system and method based on FPGA | |
| CN100389425C (en) | Method and equipment for implementing verification of digital-analog mixed type IC |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| CB02 | Change of applicant information | ||
| CB02 | Change of applicant information |
Address after: 215000 unit 13 / 16, 4th floor, building B, No.5 Xinghan street, Suzhou Industrial Park, Jiangsu Province Applicant after: Suzhou Shengke Communication Co.,Ltd. Address before: 215000 unit 13 / 16, 4th floor, building B, No.5 Xinghan street, Suzhou Industrial Park, Jiangsu Province Applicant before: CENTEC NETWORKS (SU ZHOU) Co.,Ltd. |
|
| WW01 | Invention patent application withdrawn after publication | ||
| WW01 | Invention patent application withdrawn after publication |
Application publication date: 20190329 |