CN115470106A - Verification method and system for reconfigurable chip - Google Patents
Verification method and system for reconfigurable chip Download PDFInfo
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Abstract
The invention provides a verification method of a reconfigurable chip, which comprises the following steps: and according to the item information in the verification management table, constraining the internal variables of the verification environment to obtain test excitation. And detecting the reconfigurable chip to be verified through test excitation to obtain test data. And the reference model in the verification environment acquires reference data according to the project information and the test data. And comparing the test data with the reference data to obtain a verification result. The combination of the cases of the verification module and the verification environment of the reconfigurable chip is managed through the verification case management table, so that the verification automation can be improved, the labor is saved, and the verification time is saved. Meanwhile, the invention also provides a verification system of the reconfigurable chip.
Description
Technical Field
The invention relates to the field of reconfigurable chip production and research and development. The invention particularly relates to a verification method and a verification system of a reconfigurable chip.
Background
The reconfigurable chip verification is a vital step in the research and development process of the reconfigurable chip, and the functions of the reconfigurable chip are tested through a large number of test cases in the verification process so as to ensure the correctness and reliability of the functions of the reconfigurable chip. With the increasing scale of the reconfigurable chip, the verification complexity of the reconfigurable chip is also improved. In the verification process, the function of the reconfigurable chip is ensured to be correct through a large number of verification cases, and the verification efficiency of the reconfigurable chip is reduced for the management modes of the large number of verification cases and the simulation time consumption brought by the large number of cases.
In the prior art, the verification case statistics needs to be manually performed, the work time is long, mistakes are easy to make, the statistics difficulty is high, and verification personnel who are not the verification case are not easy to check, so that the verification period is prolonged.
Disclosure of Invention
The invention aims to provide a verification method of a reconfigurable chip, which can improve the automation of verification, save labor and save verification time by managing the combination of a use case of a verification module and a verification environment of the reconfigurable chip through a verification use case management table.
In one aspect of the present invention, a verification method for a reconfigurable chip is provided, which includes: and according to the item information in the verification management table, restricting the internal variables of the verification environment to obtain test excitation. And detecting the reconfigurable chip to be verified through test excitation to obtain test data. And the reference model in the verification environment acquires reference data according to the project information and the test data. And comparing the test data with the reference data to obtain a verification result.
In an embodiment of the verification method for the reconfigurable chip of the present invention, the method further includes: and establishing a verification management table. And verifying column information in the management table as item information. The row information in the verification management table corresponds to an independent verification use case. The verification management table is an electronic form that can be edited.
The project information includes: the system comprises use case names, configuration information, definition information, uvm _ test information, use case grouping information, use case state information, simulation information before and after simulation and text interpretation information corresponding to use cases.
In another embodiment of the verification method of the reconfigurable chip of the invention, the use case name corresponds to an individual verification use case.
The configuration information includes set values of internal variables of the verification environment. The internal variables include: the excitation module sets variables and the reference model sets variables.
uvm _ test information includes: the name of the register model verification method and the name of the normal function test method.
The use case grouping information includes: and testing information in batches.
The front imitation and rear imitation information comprises: pre-emulation verification command information or post-emulation verification command information.
The use case state information includes: failure, pass, not verified, not implemented, risky, discarded, and low priority status information. In another embodiment of the verification method of the reconfigurable chip of the invention, the verification method comprises the following steps:
and converting the item information in the verification management table into a format file. The format file includes an item information field. And reading an item information field in the format file and inputting the item information field into the verification environment.
And verifying the environment to judge whether the received information is regression testing information, and if so, performing batch testing under simplified touch. If not, testing in the normal mode is carried out.
After the batch test under the reduced touch is carried out, whether the test result has an error case test or not is judged, if yes, the test under the normal mode is passed, and if not, the test result information is recorded.
In another embodiment of the verification method of the reconfigurable chip of the invention, the method further comprises:
and detecting the reconfigurable chip to be verified through the test excitation, and acquiring input feedback test data of the reconfigurable chip to be verified. And configuring a register model in the verification environment through the project information, and acquiring the output data of the register model.
And inputting the input feedback test data and the output data of the register model into the reference model to obtain reference data.
In a second aspect of the present invention, a verification system for a reconfigurable chip is provided, which includes:
a verification use case unit configured to load a verification management table. The authentication management table includes item information. And
a verification environment configured to receive a verification management table from a verification use case unit. The verification environment includes:
and the excitation module is configured to restrict the internal variable of the verification environment to obtain the test excitation according to the item information in the verification management table.
And the output module is configured to detect the reconfigurable chip to be verified through the test excitation to acquire the test data.
A reference model configured to obtain reference data from the project information and the test data.
And the comparison module is configured to compare the reference data according to the test data to obtain a verification result.
In another embodiment of the verification system of the reconfigurable chip of the present invention, the verification case unit is further configured to: and establishing a verification management table. And verifying column information in the management table as item information. The row information in the verification management table corresponds to an independent verification use case. The verification management table is an electronic form that can be edited.
The project information includes: the system comprises use case names, configuration information, definition information, uvm _ test information, use case grouping information, use case state information, simulation information before and after simulation and text interpretation information corresponding to use cases.
In another embodiment of the verification system of the reconfigurable chip of the present invention, the verification system further includes: a conversion module configured to convert the item information in the authentication management table into a format file. The format file includes an item information field. And reading an item information field in the format file and inputting the item information field into the verification environment.
In another embodiment of the verification system of the reconfigurable chip of the present invention, the verification system includes: and the directory allocation module is configured to receive the format file output by the conversion module at the input end.
A register model configured such that an input of the register model is capable of receiving a format file from the directory allocation module. And the output end of the register model is provided with an apb interface or a CGRA interface.
In still another embodiment of the verification system of the reconfigurable chip of the present invention, the verification system includes:
an input agent unit configured to include an incentive module and an input monitor.
The excitation module is also configured to have its input connected to the output of the catalog distribution module and to obtain the item information via the catalog distribution module. The output of the excitation module is connected with the reconfigurable chip to be verified, and the reconfigurable chip to be verified can be detected through test excitation.
The input monitor is configured to obtain input feedback test data of the reconfigurable chip to be verified.
The reference model is further configured such that an input of the reference model is connected to an output of the register model, and register model output data is obtained from the register model. And inputting the input feedback test data and the output data of the register model into the reference model to obtain reference data.
The characteristics, technical features, advantages and implementation manners of the verification method of the reconfigurable chip will be further described in a clear and understandable manner by combining the drawings.
Drawings
Fig. 1 is a flow chart for explaining a verification method of a reconfigurable chip in one embodiment of the present invention.
Fig. 2 is a schematic diagram for explaining a verification system of a reconfigurable chip in one embodiment of the present invention.
Fig. 3 is a diagram for explaining a verification system of a reconfigurable chip in still another embodiment of the present invention.
Fig. 4 is a flowchart for explaining a verification method of a reconfigurable chip in another embodiment of the present invention.
FIG. 5 is a diagram for illustrating configuration information of a verification use case management table according to an embodiment of the present invention.
Fig. 6 is a structural diagram for explaining a reconfigurable chip verification method according to an embodiment of the present invention.
Fig. 7 is a diagram illustrating a structure of a verification use case management table according to an embodiment of the present invention.
FIG. 8 is a flow chart illustrating a verification use case management table in one embodiment of the invention.
FIG. 9 is a flow chart for illustrating batch testing of a verification case management table in one embodiment of the invention.
Detailed Description
In order to more clearly understand the technical features, objects and effects of the present invention, embodiments of the present invention will now be described with reference to the accompanying drawings, in which the same reference numerals indicate the same or structurally similar but functionally identical elements.
"exemplary" means "serving as an example, instance, or illustration" herein, and any illustration, embodiment, or steps described as "exemplary" herein should not be construed as a preferred or advantageous alternative. For the sake of simplicity, the drawings only schematically show the parts relevant to the present exemplary embodiment, and they do not represent the actual structure and the true scale of the product.
In one aspect of the present invention, a verification method for a reconfigurable chip is provided, as shown in fig. 1 and 2, including the following steps:
and step S101, according to the item information in the verification management table, constraining the internal variables of the verification environment 102 to obtain test excitation.
Step S102, detecting the reconfigurable chip 201 to be verified through test excitation to obtain test data.
In step S103, the reference model 105 in the verification environment 102 acquires reference data according to the project information and the test data. And comparing the test data with the reference data to obtain a verification result.
The invention provides a reconfigurable chip verification method and case management, wherein a verification case management table is used for managing the combination of cases of verification modules and a reconfigurable chip verification environment, so that the automation of verification can be improved, the labor is saved, and the verification time is saved.
In an embodiment of the verification method for the reconfigurable chip of the present invention, step S101 further includes: and establishing a verification management table. And verifying column information in the management table as item information. The row information in the verification management table corresponds to an independent verification use case. The verification management table is an electronic form that can be edited.
The project information includes: the system comprises use case names, configuration information, definition information, uvm _ test information, use case grouping information, use case state information, simulation information before and after simulation and text interpretation information corresponding to use cases.
And managing the verification cases of the reconfigurable chip by using a verification case management table, wherein each line of the verification case management table represents one verification case, and the verification cases comprise case names, character strings or numerical value configuration information, definition information, used uvm _ test, case grouping, case states, front simulation and rear simulation and corresponding word explanation of the cases.
Correspondingly generating configuration information of all use case json formats according to the verification use case management table; the storage format of the verification use case management table is an Excel format.
Therefore, if the configuration information of the verification case management table changes, the configuration information can be directly modified without re-simulation compiling, so that the simulation efficiency is improved, and if multiple cases exist, different groups can be added into the verification case management table, and regression can be directly carried out according to the groups, so that effective management is realized.
In another embodiment of the verification method of the reconfigurable chip of the invention, the use case name corresponds to an individual verification use case.
The configuration information includes set values of internal variables of the verification environment 102. The internal variables include: the excitation module sets variables and the reference model sets variables.
uvm _ test information includes: the name of the register model verification method and the name of the normal function test method.
The use case grouping information comprises: and testing information in batches.
The front imitation and rear imitation information comprises: pre-emulation verification command information or post-emulation verification command information.
The use case state information includes: failure, pass, not verified, not implemented, risky, discarded, and low priority status information.
Extracting effective information of a verification case management table to generate a corresponding scene case; the use case names correspond to different verification use cases. The configuration information includes strings/values that may correspond to variable enumeration/value types within the verification environment 102. If the information is not configured, the corresponding variable is random under a reasonable constraint condition, and a random verification scene in a constraint range is generated.
The definition information of the verification case management table can change the verification environment 102, and the definition information in the environment is uniformly managed.
Using uvm _ test, a different uvm _ test in the verification environment 102 is selected.
The use of batch test is convenient for the use of case grouping, and the whole group of cases can be tested by one-time batch test.
And selecting a front imitation and a rear imitation, wherein the front imitation and the rear imitation of the selected case can be configured in the verification case management table.
Each case state of the verification case management table includes Failure (FAIL), PASS (PASS), not verified (notch), not realized (notch), risk (ISSUE), discard (retry), and low priority (lowcriteria), and the verification management table counts data of each state.
In another embodiment of the verification method of the reconfigurable chip of the invention, the verification method comprises the following steps:
the item information in the verification management table is converted into a format file, such as a json format file, and the json format file is taken as an example to describe the verification method of the reconfigurable chip in the present invention. The json format file comprises item information fields. The entry information fields in the json format file are read and entered into the verification environment 102. And converting effective information of the verification case management table into json files to generate configuration, verifying the constraint of the corresponding configuration of the environment 102, randomly generating a reasonable verification scene, and exciting the reconfigurable chip 201 to be verified.
As shown in fig. 9, the verification environment 102 determines whether the received information is regression test information, and if so, performs batch testing under a reduced touch; if not, testing in a normal mode; after the batch test under the simplified touch is carried out, whether an error case test exists in the test result is judged, if yes, the test under the normal mode is passed, and if not, the test result information is recorded.
In another embodiment of the verification method of the reconfigurable chip of the invention, the method further comprises:
the reconfigurable chip 201 to be verified is detected through the test excitation, and input feedback test data of the reconfigurable chip 201 to be verified is obtained. Register models in the verification environment 102 are configured through the project information, and register model output data are obtained.
The input feedback test data and the register model output data are input to the reference model 105, and the reference data is acquired.
In a second aspect of the present invention, there is provided a verification system for a reconfigurable chip, as shown in fig. 2, including:
a verification use case unit 101 configured to load a verification management table. The authentication management table includes item information. The configuration information in the verification case management table may be used as constraint information to constrain random data of the reconfigurable chip 201 to be verified, and may also be used as configuration within a constraint range, the reconfigurable chip 201 to be verified activates and configures a register working mode, a data size, and a transmission interface, a data size corresponding to a register is generated in a data packet, and the data size is transmitted to the reconfigurable chip 201 to be verified by using different interfaces.
Generation of excitation data, comprising: if the configuration information in the verification case management table is empty or partially empty, the corresponding configuration is generated randomly in a constraint range in a full or partial mode, and the reconfigurable chip 201 to be verified excites the reasonable random configuration register to randomly generate a reasonable verification scene.
A verification environment 102 configured to receive a verification management table from the verification use case unit 101. The verification environment 102 includes:
an incentive module 103 configured to constrain the internal variables of the verification environment 102 to obtain test incentives according to the item information in the verification management table.
And the output module 104 is configured to detect the reconfigurable chip 201 to be verified through the test excitation to acquire the test data.
A reference model 105 configured to obtain reference data from the project information and the test data. The reference model outputs the input excitation data to the comparison module through monitoring, and waits for the result of the reconfigurable chip 201 to be verified.
A comparison module 106 configured to compare the reference data according to the test data to obtain a verification result.
Excitation data is input into the reconfigurable chip 201 to be verified, the output result of the reconfigurable chip 201 to be verified is monitored, packaged and sent to the comparison module, and compared with the output result of the reference model, and the verification result of the reconfigurable chip 201 to be verified is obtained.
Loading excitation through the reconfigurable chip 201 to be verified and the reference model respectively, including:
inputting an excitation into the reconfigurable chip 201 to be verified: according to the definition information in the verification case management table, the reconfigurable chip 201 to be verified configures a register through an apb or CGRA interface, and simultaneously, the verification environment generates randomly generated data with corresponding size and format according to the configuration and inputs the randomly generated data into the reconfigurable chip 201 to be verified, wherein the configuration comprises a working mode, the size of the generated data and a transmission interface.
Reference model input excitation: inputting and monitoring interface data packet to reference model according to register model
In another embodiment of the verification system of the reconfigurable chip of the present invention, the verification case unit 101 is further configured to: and establishing a verification management table. And verifying column information in the management table as item information. The row information in the verification management table corresponds to an independent verification use case. The verification management table is an electronic form that can be edited.
The project information includes: the system comprises use case names, configuration information, definition information, uvm _ test information, use case grouping information, use case state information, simulation information before and after simulation and text interpretation information corresponding to use cases.
In another embodiment of the verification system of the reconfigurable chip of the present invention, as shown in fig. 3, the verification system further includes: a conversion module 107 configured to convert the item information in the verification management table into a json format file. The json format file includes item information fields. The entry information fields in the json format file are read and entered into the verification environment 102.
In another embodiment of the verification system of the reconfigurable chip of the present invention, the verification system includes: a directory allocation module 108 (virtual _ sequence) configured to receive the json format file output by the conversion module 107 at an input.
A register model 109 configured such that an input of the register model is capable of receiving json format files from the directory assignment module. And the output end of the register model is provided with an apb interface or a CGRA interface.
In still another embodiment of the verification system of the reconfigurable chip of the present invention, the verification system includes:
an input agent unit 301 configured to include an excitation module 103 and an input monitor 302.
The incentive module 103 is further configured such that an input of the incentive module 103 is connected to an output of the catalog allocation module, and the item information is obtained by the catalog allocation module. The output of the excitation module 103 is connected to the reconfigurable chip 201 to be verified, and the reconfigurable chip 201 to be verified can be detected through test excitation.
The input monitor 302 is configured to obtain input feedback test data of the reconfigurable chip 201 to be verified.
The reference model 105 is further configured such that an input of the reference model 105 is connected to an output of the register model, and register model output data is obtained from the register model. The input feedback test data and the register model output data are input to the reference model 105, and the reference data is acquired.
In one embodiment of the present invention, a method for verifying a reconfigurable chip includes: the method comprises the steps of generating verification specific excitation or random excitation through valid information of a verification use case management table, recording valid information (use case name, use case grouping, configuration information, definition information, used uvm _ test, definition information, front simulation and rear simulation) and use case states of all verification use cases, and combining the configuration information by character strings and numerical values to strengthen visualization of the verification use case management table.
The verification case management table adopts an editable and strong-universality electronic form editor such as an Excel format. And verifying the sheet of the case management table, and generating different json tables corresponding to different sheets or generating different json tables according to different case groups. The verification case management table is directly associated with the verification environment, and the verification case is directly managed through the verification case management table, so that manual operation on the verification environment is reduced. The modification of the verification case management table can directly modify the configuration of the verification environment without recompilation, thereby saving the simulation compilation time and improving the verification efficiency.
The verification case management table comprises state information, statistics case states, detailed configuration of explanation cases and overall project progress. The verification case management table comprises case groups and optional case names, the case groups use common case groups and random case groups, and the verification cases comprise register model test cases and normal function test cases.
The verification case management table is converted into a json format and input into a verification environment, and the verification environment generates excitation in a constraint range and randomly generates data to the reconfigurable chip 201 to be verified according to effective information of the management table. In the json process of converting the verification case management table, the variable is in a verification environment hierarchical path, and the variable path is virtual _ sequence.
And verifying the names of different case groups in the json conversion process of the case management table. The size of the configured resolution is judged, and random data with corresponding size, file types 240P and 720P and the like are generated. And judging and configuring the input and output among a working mode CFA, YUV, RGB format conversion, an interface dvp and a dma interface. And for information such as configuration resolution, a working mode, an interface and the like, configuring a register of the reconfigurable chip 201 to be verified through an apb or CGRA interface in the verification environment.
The process verifies the environment to generate excitation, and inputs the excitation to the reconfigurable chip 201 to be verified. Monitoring input data and data input into the to-be-verified reconfigurable chip 201 by the verification environment register model, packaging and sending the data into the reference model, sending data output by the reference model as expected data into the comparison module, waiting for the to-be-verified reconfigurable chip 201 to output, and comparing the data with the output of the to-be-verified reconfigurable chip 201.
The reconfigurable chip 201 to be verified is processed by the excitation input generated by the verification environment and then output to the comparison module. The comparison module receives data input by the reference model and the reconfigurable chip 201 to be verified, and compares the data in real time, and the comparison result is used as a verification function result.
Generating json format configuration by using a verification case management table, generating excitation by the configuration through a verification environment, and comparing results generated after data are transmitted into the reconfigurable chip 201 to be verified and the reference model to obtain a verification result. The verification result is recorded in the verification case management table, and the maturity of the reconfigurable chip 201 to be verified at present can be counted. The verification case management table can be configured based on uvm _ test, and uvm _ test is divided into a verification method and a normal function test provided by the register model.
The verification case management tables can manage regression according to groups, the verification case management tables are divided into two groups, namely normal function test and random test, and case regression can be started in batches through different sheets during regression. The verification case management table can count the number of cases and the states of the cases, and can provide reference for verification.
In an embodiment of the present invention, an efficient reconfigurable chip verification method and use case management are provided, and the method in the embodiment of the present invention is described below with reference to the drawings in the embodiment of the present invention, where the described embodiment is only a preferred example of the present invention, and the content protected by the present invention is not limited to the content of the specific embodiment.
The verification methodology is one of trends of reconfigurable chip verification, universal Verification Methodology (UVM) is a typical representative thereof, and a verification engineer can construct a functional verification environment with a standardized hierarchical structure and an interface by using reusable components thereof.
Fig. 4 and 5 are diagrams illustrating a reconfigurable chip verification method according to the present invention, in which a verification case management table is combined with a UVM verification environment, effective information of the verification case management table is transmitted to the verification environment, the verification environment is constrained to generate excitation, the excitation is transmitted to a comparison model after being processed by a reference model, and the comparison model is compared with an output of a reconfigurable chip to be verified to obtain a result of a reconfigurable chip verification case.
In the reconfigurable chip verification method, the verification management table is shown in table 1, and the modification of the configuration information of the verification management table does not need to be recompiled, so that the compilation time is saved, and the simulation verification time is further saved. The verification case management table can modify the structure of the verification environment by configuring the define column information, and can centrally manage the define information when the define information is more in the verification environment.
TABLE 1
The verification case management table can select a front simulation or a gate-level simulation through configuring the column information of the gate _ sim. The verification use case management table can distinguish use cases from batch regression use cases by groups by configuring use case groups. The verification use case management table may specify uvm _ test in the verification environment used through a uvm _ test column.
When the reconfigurable chip to be verified is immature, the verification case management table can limit cases by configuring a plurality of pieces of configuration information to realize debugging of typical cases, when the reconfigurable chip to be verified completes one type of functions, the verification case management table can realize randomness of partial function cases by configuring partial information, when the reconfigurable chip to be verified is mature or regressed, the verification case management table can realize full randomness of cases without configuring or with little configuration information, the verification environment establishment can be synchronous with the design of the reconfigurable chip to be verified, the maturity of the reconfigurable chip to be verified is gradually improved by the verification case management table through subtraction, the development period of the reconfigurable chip is shortened, and verification automation and visualization are realized.
Fig. 6 shows a simulation structure of a verification method for a reconfigurable chip according to an embodiment of the present invention. As shown in fig. 6, the verification case management table is an entry of the reconfigurable chip verification, and is used for managing all cases of the reconfigurable chip verification, completing input of excitation by configuring variables in virtual _ sequence, respectively inputting the input to the register model and the input excitation module, and sending the input to the reconfigurable chip 201 to be verified, the reference model monitors the register model configuration and the input interface data of the reconfigurable chip 201 to be verified, and transmits the input interface data to the comparison model after being processed by the reference model, and compares the input interface data with the output of the reconfigurable chip 201 to be verified, so as to obtain the result of the reconfigurable chip verification case.
The verification case management table changes a verification structure by defining a define column, a register model instantiation CGRA interface in the verification environment is defined when CGRA is defined, and an apb interface is not defined when CGRA is defined. Fig. 7 is a flow of a use case management method according to the present invention, a use case of a verification use case management table is input into a verification environment by converting a json format to generate an excitation, and optionally, the format of the verification use case management table is an Excel format.
When the verification use case management table is converted into a json format, each line represents a use case, and the obtained effective items comprise a use case name, a use case group, configuration information, definition information, used uvm _ test, the definition information, a front simulation and a rear simulation, which are all effective information transmitted into a verification environment and influence a verification result together.
The verification management table management use case flow, as shown in fig. 8, may include the steps of: the verification case management table passes valid information of the verification case of each row. And transmitting the verification environment to generate excitation, and inputting the excitation to the reconfigurable chip to be verified. And data information of the monitoring module in the input agent is transmitted into the reference model, and the output of the reference model is input into the comparison module and compared with the data information of the monitoring module in the output agent.
And obtaining the case verification result, and counting the result state to a verification case management table. As shown in fig. 9, the verification case management table may be grouped, the verification cases may be grouped, tested in batch, or tested in regression, and in order to save server resources and simulate verification efficiency, the script is distinguished according to whether the test in batch is tested in regression.
If the test is not the regression test, the case test under the normal mode with the waveform information is carried out, and the case result is recorded to the verification case management table. If the regression test is carried out, the case test under the simplified mode without the waveform information is carried out, and then whether secondary regression is carried out or not is judged according to whether the case has errors or not.
And if the case has errors in the regression mode, performing secondary regression testing on the erroneous verification case in the normal mode, and recording case results to a verification case management table. And if the use case is correct in the regression mode, directly recording the use case result to a verification use case management table.
It should be understood that although the present description is described in terms of various embodiments, not every embodiment includes only a single embodiment, and such description is for clarity purposes only, and those skilled in the art will recognize that the embodiments described in the various embodiments can be combined as appropriate to form other embodiments as would be understood by those skilled in the art.
The above-listed detailed description is only a specific description of a possible embodiment of the present invention, and they are not intended to limit the scope of the present invention, and equivalent embodiments or modifications made without departing from the technical spirit of the present invention should be included in the scope of the present invention.
Claims (10)
1. A verification method of a reconfigurable chip is characterized by comprising the following steps:
according to the project information in the verification management table, the internal variables of the verification environment are restrained to obtain test excitation;
testing data are obtained through the reconfigurable chip to be verified through the test excitation detection;
a reference model in the verification environment acquires reference data according to the project information and the test data;
and comparing the reference data according to the test data to obtain a verification result.
2. The verification method of the reconfigurable chip according to claim 1, further comprising:
establishing a verification management table; column information in the verification management table is the project information; the row information in the verification management table corresponds to an independent verification case; the verification management table is an editable electronic table;
the project information includes: the system comprises use case names, configuration information, definition information, uvm _ test information, use case grouping information, use case state information, simulation information before and after simulation and text interpretation information corresponding to use cases.
3. The verification method of a reconfigurable chip according to claim 2,
the case name corresponds to an individual verification case;
the configuration information includes a set value of an internal variable of the verification environment; the internal variables include: the excitation module sets variables and the reference model sets variables;
the uvm _ test information includes: the name of the register model verification method and the name of the normal function test method;
the use case grouping information includes: batch testing information;
the front-imitation and rear-imitation information comprises: front simulation verification command information or rear simulation verification command information;
the use case state information comprises: failure, pass, not verified, not implemented, risky, discarded, and low priority status information.
4. The verification method of the reconfigurable chip according to claim 3, comprising:
converting the project information in the verification management table into a format file; the format file comprises the project information field; reading an item information field in the format file and inputting the item information field into the verification environment;
the verification environment judges whether the received information is regression test information, if so, batch test under reduced touch is carried out; if not, testing in a normal mode;
after the batch test under the reduced touch is carried out, whether the test result has an error case test or not is judged, if yes, the test under the normal mode is passed, and if not, the test result information is recorded.
5. The verification method of the reconfigurable chip according to claim 1, further comprising:
detecting a reconfigurable chip to be verified through the test excitation, and acquiring input feedback test data of the reconfigurable chip to be verified;
configuring a register model in the verification environment through the project information, and acquiring register model output data;
and inputting the input feedback test data and the output data of the register model into the reference model to obtain reference data.
6. A verification system for a reconfigurable chip, comprising:
a verification use case unit configured to load a verification management table; the verification management table comprises project information;
a verification environment configured to receive the verification management table from the verification use case unit; the verification environment includes:
the excitation module is configured to restrict the internal variables of the verification environment to obtain test excitation according to the item information in the verification management table;
the output module is configured to detect the reconfigurable chip to be verified through the test excitation to acquire test data;
a reference model configured to obtain reference data from the project information and the test data;
and the comparison module is configured to compare the reference data according to the test data to obtain a verification result.
7. The verification system of the reconfigurable chip of claim 6, wherein the verification case unit is further configured to: establishing a verification management table; column information in the verification management table is the project information; the row information in the verification management table corresponds to an independent verification case; the verification management table is an editable electronic table;
the project information includes: the system comprises use case names, configuration information, definition information, uvm _ test information, use case grouping information, use case state information, simulation information before and after simulation and text interpretation information corresponding to use cases.
8. The verification system of the reconfigurable chip according to claim 6, further comprising:
a conversion module configured to convert the item information in the verification management table into a format file; the format file comprises the project information field; and reading an item information field in the format file and inputting the item information field into the verification environment.
9. The verification system of the reconfigurable chip according to claim 8, comprising:
the directory distribution module is configured to receive the format file output by the conversion module at the input end;
a register model configured such that an input of the register model is capable of receiving the format file from the directory allocation module; and the output end of the register model is provided with an apb interface or a CGRA interface.
10. The verification system of the reconfigurable chip according to claim 9, comprising:
an input agent unit configured to include the stimulus module and an input monitor;
the excitation module is also configured to connect the input of the excitation module with the output of the catalog distribution module, and acquire project information through the catalog distribution module; the output of the excitation module is connected with the reconfigurable chip to be verified, and the reconfigurable chip to be verified can be detected through the test excitation;
the input monitor is configured to acquire input feedback test data of the reconfigurable chip to be verified;
the reference model is also configured to obtain register model output data from the register model by connecting the input of the reference model with the output of the register model; and inputting the input feedback test data and the output data of the register model into the reference model to obtain reference data.
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| CN116301724A (en) * | 2023-03-16 | 2023-06-23 | 济南新语软件科技有限公司 | Method, device, equipment and storage medium for generating non-repeated pseudo random number |
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| CN116301724A (en) * | 2023-03-16 | 2023-06-23 | 济南新语软件科技有限公司 | Method, device, equipment and storage medium for generating non-repeated pseudo random number |
| CN116301724B (en) * | 2023-03-16 | 2023-09-26 | 济南新语软件科技有限公司 | Method, device, equipment and storage medium for generating non-repeated pseudo random number |
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