CN112710947A - ATE-based functional test method and tool - Google Patents
ATE-based functional test method and tool Download PDFInfo
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- CN112710947A CN112710947A CN202011527950.1A CN202011527950A CN112710947A CN 112710947 A CN112710947 A CN 112710947A CN 202011527950 A CN202011527950 A CN 202011527950A CN 112710947 A CN112710947 A CN 112710947A
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- 238000011990 functional testing Methods 0.000 title claims abstract description 25
- 238000000034 method Methods 0.000 title claims abstract description 22
- 238000012360 testing method Methods 0.000 claims abstract description 195
- 238000006243 chemical reaction Methods 0.000 claims abstract description 72
- 102100028029 SCL-interrupting locus protein Human genes 0.000 claims 2
- 238000004088 simulation Methods 0.000 description 9
- 230000006870 function Effects 0.000 description 8
- 230000004048 modification Effects 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 230000000737 periodic effect Effects 0.000 description 3
- 238000010998 test method Methods 0.000 description 3
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2832—Specific tests of electronic circuits not provided for elsewhere
- G01R31/2834—Automated test systems [ATE]; using microprocessors or computers
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Abstract
The invention relates to an ATE-based functional test tool, which comprises a conversion tool and a test tool, wherein the conversion tool and the test tool are integrated into a whole, the conversion tool carries out format conversion on a file to be tested, and the test tool can test the file converted by the conversion tool and feed back a test result in real time. Also provided is an ATE-based functional test method, comprising: the conversion tool converts the format of the file to be tested into a format which can be tested by the test tool so as to form a test text; the test tool tests the test text and feeds back a test result; modifying part of parameters of the file to be tested, directly converting the modified part of parameters by a conversion tool to form a new test text, and testing the new test text by the test tool on line and feeding back a test result in real time. After the file to be tested is modified, the modified part can be directly converted, and the test tool can test the converted file in real time, so that the time for converting the file is greatly saved.
Description
Technical Field
The invention relates to the field of circuit testing, in particular to a function testing method and tool based on ATE.
Background
In the functional test of the existing automatic test system (ATE), a file to be tested provided by a customer or an inventor needs to be converted into a format file which can be tested by the ATE, such as a file in a VCD format, and then converted into a still file by certain software, and then converted into a format which can be recognized by the ATE by the software. In the prior art, a file to be tested is converted into a format capable of being tested in a conversion tool and then is transmitted to ATE for testing, wherein the conversion tool and the ATE are two independent machines. Usually, the format conversion time is long, and some times even two hours. However, during debugging of the test engineer, the test file to be tested may need to be modified repeatedly, and each time the test file is modified, the test file is saved and then converted on the conversion tool. If the frequency of modifying the test file is too high, repeated conversion is required, that is, if one conversion of the test file takes two hours, two more hours, four hours in total, are required for conversion after one modification, and six hours in total are required for conversion if the file is modified again. The time is spent, and the efficiency is low.
Disclosure of Invention
The invention aims to provide a function test method and a function test tool based on ATE (automatic test equipment). after a conversion tool converts the format of a file to be tested, the test tool can directly test the file to be tested, and after the file to be tested is modified, the modified part can be directly converted, and the test tool can test the converted file in real time, so that the time for converting the file is greatly saved.
In order to achieve the above object, the present invention provides an ATE-based functional test tool, which includes a conversion tool and a test tool, wherein the conversion tool and the test tool are integrated into a whole, the conversion tool performs format conversion on a file to be tested, and the test tool can test the file converted by the conversion tool and feed back a test result in real time.
Optionally, in the functional test tool, the conversion tool is connected to the test tool through a GPIB line.
Optionally, in the functional test tool, the test tool further has a red light and a green light.
The invention also provides an ATE-based functional test method for testing a circuit file formed by EDA or ATPG, which comprises the following steps:
the conversion tool converts the format of the file to be tested into a format which can be tested by the test tool so as to form a test text;
the test tool tests the test text and feeds back a test result;
modifying part of parameters of the file to be tested, directly converting the modified part of parameters by a conversion tool to form a new test text, and testing the new test text by the test tool on line and feeding back a test result in real time.
Optionally, in the function testing method, the format of the file to be tested includes: the. VCD format,. EVCD format,. WGL format, and. sting format.
Optionally, in the functional test method, the format in which the test tool can test includes: PAT format and. BINL format.
Optionally, in the functional test method, the method for converting the format of the file to be tested into the format capable of being tested by the test tool by the conversion tool includes:
converting the format of the file to be tested in the VCD format into the PAT format;
converting the format of the file to be tested in the VCD format into a BINL format;
converting the format of the file to be tested in the EVCD format into a PAT format;
converting the format of the file to be tested in the EVCD format into a BINL format;
converting the format of the file to be tested in the WGL format into a PAT format;
converting the format of the file to be tested in the WGL format into a BINL format;
converting the format of the file to be tested in the STIL format into a PAT format;
alternatively, the file format to be tested in the STIL format is converted into the BINL format.
Optionally, in the functional test method, the test text is transmitted to the test tool through a GPIB line.
Optionally, in the function testing method, the testing tool is further provided with a red light and a green light, and when the testing tool tests the test text successfully, the green light is turned on.
Optionally, in the function test method, when the test tool fails to test the test text, the red light is turned on.
In the ATE-based function testing method and the ATE-based function testing tool, after the format of the file to be tested is converted by the conversion tool, the file to be tested can be directly tested by the testing tool, the modified part can be directly converted after the file to be tested is modified, the converted file can be tested by the testing tool in real time, and a large amount of time for converting the file is saved.
Drawings
FIG. 1 is a flow chart of an ATE-based functional test method according to an embodiment of the invention.
Detailed Description
The following describes in more detail embodiments of the present invention with reference to the schematic drawings. The advantages and features of the present invention will become more apparent from the following description. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is merely for the purpose of facilitating and distinctly claiming the embodiments of the present invention.
In the following, the terms "first," "second," and the like are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the terms so used are interchangeable under appropriate circumstances. Similarly, if the method described herein comprises a series of steps, the order in which these steps are presented herein is not necessarily the only order in which these steps may be performed, and some of the described steps may be omitted and/or some other steps not described herein may be added to the method.
The invention provides an ATE-based functional test tool, which comprises: the conversion tool and the test tool are integrated, the conversion tool performs format conversion on a file to be tested, and the test tool can test the file converted by the conversion tool and feed back a test result in real time.
Further, the conversion tool is connected to the test tool through a GPIB line. The GPIB wire is a very small connecting tool, so that the conversion tool and the test tool are equivalently integrated, the file converted by the conversion tool can be transmitted to the test tool in real time, and can be directly converted and transmitted to the test tool after part of parameters of the file to be tested are changed, and the test tool is not required to be taken out for testing after the file to be tested is converted on the conversion tool alone.
Further, the test tool is provided with a red light and a green light.
Referring to fig. 1, the present invention further provides an ATE-based functional test method for testing a circuit file formed by EDA or ATPG, including:
s11: the conversion tool converts the format of the file to be tested into a format which can be tested by the test tool so as to form a test text;
s12: the test tool tests the test text and feeds back a test result;
s13: modifying part of parameters of the file to be tested, directly converting the modified part of parameters by a conversion tool to form a new test text, and testing the new test text by the test tool on line and feeding back a test result in real time.
Further, the file format to be tested comprises: the. VCD format,. EVCD format,. WGL format, and. sting format. Currently, during VLSI design, simulation files are typically generated from EDA or ATPG. However, the simulation files generated by EDA and ATPG cannot be directly used by ATE in general, and need to be converted to be test files that can be recognized by ATE; the test file in the general sense includes that the test timing (timing) and the test vector (vector) are periodic results, and the format is related to the test platform. Different ATE, the test vector format is generally different, even if ATE of the same brand is used, the test vector format may not be completely the same; common simulation files are mainly in the VCD,. EVCD,. WGL or. sting format, generally depending on the EDA software used. The simulation based on the functional test generally outputs files in VCD/EVCD format, and the simulation based on the structural test generally outputs files in WGL format. The VCD file is a simulation file most widely used in the development process of the test program at the present stage, and it takes zero time as a starting point and time as a horizontal axis, and mainly includes an event set of level signals of 0, 1, x, z, and the like. Each signal keeps the previous state before the next state jump, and the internal part of each signal contains rich time sequence information. WGL (wave Generation language), which is a data descriptive language describing scan structures and states, and timing and values of test pattern parts, enables Generation of hardware scan structures and test programs within a device, allows variable definition and inline equation expressions, and can replace graphic data representation in ASCII code with binary format. The main syntax structure of the WGL includes a waveform block, a timing block, a signal block, a subroutine block, a scan chain block, and the like. The STIL (Standard Test Interface Language) is an interactive Language between a digital Test vector generation tool and a Test device, and is also a file format based on ASCII (American Standard code for information interchange) codes. The STIL file has a periodic type and an event-triggered type description mode, and is a perfect combination of a VCD file and a WGL file. The data structure of the STIL language is in units of blocks, and each specific data type is defined within a data structure block of the same type. The data format mainly comprises a file description block, a signal chunk, a signal block, a time timing group, a test pattern block, a signal group and signal relation block, a signal and timing relation block and a test vector and timing relation block.
Further, the format that the test tool can test includes: PAT format and. BINL format.
Further, the method for converting the format of the file to be tested into the format capable of being tested by the testing tool by the conversion tool comprises the following steps: converting the format of the file to be tested in the VCD format into the PAT format; converting the format of the file to be tested in the VCD format into a BINL format; converting the format of the file to be tested in the EVCD format into a PAT format; converting the format of the file to be tested in the EVCD format into a BINL format; converting the format of the file to be tested in the WGL format into a PAT format; converting the format of the file to be tested in the WGL format into a BINL format; converting the format of the file to be tested in the STIL format into a PAT format; alternatively, the file format to be tested in the STIL format is converted into the BINL format. That is, the text to be tested provided by the inventor is any one of the formats of VCD, EVCD, WGL and STIL, and the test tool can only test the files of PAT and BINL, so that a plurality of conversion methods are possible, and the conversion tool provided by the present invention can convert the formats of four texts to be tested into the formats of the two test texts.
Further, the test text is transmitted to the test tool through a GPIB line. The test text is transmitted to the test tool as data through a GPIB line, the GPIB line integrates the two test tools on one device, and the GPIB line can transmit the test text as data to the test tool in real time and efficiently. The relative positions of the conversion tool and the test tool are not limited, and the conversion tool and the test tool can be even made into one tool. Whether the test text is passed as data to the test tool via the GPIB line or the conversion tool and test work are used as one tool, the additional conversion tool is reduced. The additional conversion tools in the prior art often occupy a certain area and have a certain cost, and of course, the most important is that the conversion tools in the prior art cannot communicate with the testing tool in real time, so that format conversion needs to be carried out again every time the text to be tested in turn is modified, and too much time is wasted.
Further, when the test tool successfully tests the test text, the green light is turned on.
Further, when the test tool fails to test the test text, the red light is on. The green light and the red light are only used to indicate the test result, and in other embodiments of the present invention, the test result may be indicated by other phenomena, for example, a buzzer, and if the test result is successful, the buzzer does not sound, and if the test result is failed, the buzzer sounds. The test result is represented by a visual or audible phenomenon, and the test result can be known to the inventor or tester in time. And if the test failure can be found in time in the test process, the text to be tested can be modified in time so as to ensure the test to be successful. At this moment, the simulation test method of the embodiment of the invention is particularly important, the test text can be directly and manually modified in the test text, then the conversion is carried out through the conversion tool, and the test is carried out by the test tool immediately. More conversion time is not wasted, and more waiting time is not required for the test tool, so that the whole test efficiency is improved.
The text to be tested provided by the inventor is generally in a VCD format, an EVCD format, a WGL format or a STIL format, but a file testing tool in such a format cannot be tested, so that conversion is required by a conversion tool, and the conversion tool in the prior art is separated from the testing tool, namely the conversion tool and the testing tool are two different devices. Typical conversion tools include the Test instrumentation TDL (Tester Data Link) conversion tool, while Test software typically includes ATE Test software. Wherein: the TDL software mainly comprises a VCD2STIL part and an ATEGen part, wherein the VCD2STIL converts event-based test formats of a VCD and an EVCD into an STIL periodic format, and a conversion path from a simulation file to a standard test description language STIL is realized; the ATEGen converts the STIL generated by the VCD2STIL into a program file used by the ATE, so that a complete conversion flow from the simulation file to the ATE test program is realized. However, the original text to be tested has more data, which may result in a longer format conversion time, and some conversion times may even reach two hours. And transferring the test text to an ATE machine for testing after the conversion is successful. However, if the inventor decides to modify a certain parameter or a certain part of parameters in the text to be tested at this time, some data and programs need to be manually modified in the text to be tested, and after the modification is completed, the new text to be tested is converted by the conversion tool. Therefore, much conversion time is wasted, and if the number of times of modification is large, the whole test flow is affected.
In summary, in the ATE-based functional testing method and tool provided in the embodiments of the present invention, after the conversion tool converts the format of the file to be tested, the testing tool may directly test the file to be tested, and after the file to be tested is modified, the modified part may be directly converted, and the testing tool may test the converted file in real time, so as to save a lot of time for converting the file.
The above description is only a preferred embodiment of the present invention, and does not limit the present invention in any way. It will be understood by those skilled in the art that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the invention as defined by the appended claims.
Claims (10)
1. The ATE-based functional test tool is characterized by comprising a conversion tool and a test tool, wherein the conversion tool and the test tool are integrated, the conversion tool performs format conversion on a file to be tested, and the test tool can test the file converted by the conversion tool and feed back a test result in real time.
2. The functional test tool of claim 1, wherein the conversion tool is coupled to the test tool via a GPIB line.
3. The functional test kit of claim 1, further comprising red and green lights on the test kit.
4. An ATE-based functional test method for testing a circuit file formed of EDA or ATPG using an ATE-based functional test tool according to any one of claims 1 to 3, comprising:
the conversion tool converts the format of the file to be tested into a format which can be tested by the test tool so as to form a test text;
the test tool tests the test text and feeds back a test result;
modifying part of parameters of the file to be tested, directly converting the modified part of parameters by a conversion tool to form a new test text, and testing the new test text by the test tool on line and feeding back a test result in real time.
5. The functional testing method of claim 4, wherein the file format to be tested comprises: the. VCD format,. EVCD format,. WGL format, and. sting format.
6. The functional test method of claim 5, wherein the test tool testable format comprises: PAT format and. BINL format.
7. The functional testing method of claim 6, wherein the method for the conversion tool to convert the format of the file to be tested into a format that can be tested by the testing tool comprises:
converting the format of the file to be tested in the VCD format into the PAT format;
converting the format of the file to be tested in the VCD format into a BINL format;
converting the format of the file to be tested in the EVCD format into a PAT format;
converting the format of the file to be tested in the EVCD format into a BINL format;
converting the format of the file to be tested in the WGL format into a PAT format;
converting the format of the file to be tested in the WGL format into a BINL format;
converting the format of the file to be tested in the STIL format into a PAT format;
alternatively, the file format to be tested in the STIL format is converted into the BINL format.
8. The functional test method of claim 4, wherein the test text is passed to the test tool via a GPIB line.
9. The functional test method of claim 4, wherein the test tool further comprises a red light and a green light, and the green light is turned on when the test tool successfully tests the test text.
10. The functional test method of claim 9, wherein a red light is lit when the test tool fails to test the test text.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113533936A (en) * | 2021-07-13 | 2021-10-22 | 上海矽昌微电子有限公司 | Chip scan chain test method and system |
Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5974248A (en) * | 1996-12-23 | 1999-10-26 | Lsi Logic Corporation | Intermediate test file conversion and comparison |
| US6978410B1 (en) * | 1999-09-25 | 2005-12-20 | Advantest Corp. | Test language conversion method |
| CN102608517A (en) * | 2012-02-16 | 2012-07-25 | 工业和信息化部电子第五研究所 | Method for rapidly creating integrated circuit test program package |
| CN102855331A (en) * | 2012-09-24 | 2013-01-02 | 芮齐平 | Method of converting EDA (Electronic Document Authorization) files to ATE (Automatic Test Equipment) machine station format files |
| CN104732001A (en) * | 2013-12-20 | 2015-06-24 | 爱德万测试公司 | Online design validation for electronic devices |
| CN105158673A (en) * | 2015-08-27 | 2015-12-16 | 青岛海信信芯科技有限公司 | ATE machine table file generation method and device |
| US20180180667A1 (en) * | 2016-12-25 | 2018-06-28 | Nuvoton Technology Corporation | Resolving automated test equipment (ate) timing constraint violations |
| CN110632499A (en) * | 2019-09-23 | 2019-12-31 | 珠海格力电器股份有限公司 | Test vector generation method based on test object and storage medium |
-
2020
- 2020-12-22 CN CN202011527950.1A patent/CN112710947A/en active Pending
Patent Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5974248A (en) * | 1996-12-23 | 1999-10-26 | Lsi Logic Corporation | Intermediate test file conversion and comparison |
| US6978410B1 (en) * | 1999-09-25 | 2005-12-20 | Advantest Corp. | Test language conversion method |
| CN102608517A (en) * | 2012-02-16 | 2012-07-25 | 工业和信息化部电子第五研究所 | Method for rapidly creating integrated circuit test program package |
| CN102855331A (en) * | 2012-09-24 | 2013-01-02 | 芮齐平 | Method of converting EDA (Electronic Document Authorization) files to ATE (Automatic Test Equipment) machine station format files |
| CN104732001A (en) * | 2013-12-20 | 2015-06-24 | 爱德万测试公司 | Online design validation for electronic devices |
| CN105158673A (en) * | 2015-08-27 | 2015-12-16 | 青岛海信信芯科技有限公司 | ATE machine table file generation method and device |
| US20180180667A1 (en) * | 2016-12-25 | 2018-06-28 | Nuvoton Technology Corporation | Resolving automated test equipment (ate) timing constraint violations |
| CN110632499A (en) * | 2019-09-23 | 2019-12-31 | 珠海格力电器股份有限公司 | Test vector generation method based on test object and storage medium |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113533936A (en) * | 2021-07-13 | 2021-10-22 | 上海矽昌微电子有限公司 | Chip scan chain test method and system |
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