CN102842561A - WLCSP (Wafer Level Chip Size Packaging) single-chip package and packaging method thereof - Google Patents
WLCSP (Wafer Level Chip Size Packaging) single-chip package and packaging method thereof Download PDFInfo
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- CN102842561A CN102842561A CN201210306611XA CN201210306611A CN102842561A CN 102842561 A CN102842561 A CN 102842561A CN 201210306611X A CN201210306611X A CN 201210306611XA CN 201210306611 A CN201210306611 A CN 201210306611A CN 102842561 A CN102842561 A CN 102842561A
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- chip
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- salient point
- tin layer
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16245—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
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- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
Abstract
The invention relates to a WLCSP (Wafer Level Chip Size Packaging) single-chip package and a packaging method thereof and belongs to the technical field of packaging of an integrated circuit. Tin layers are plated in regions on a substrate, which are welded with metal bumps; the metal bumps are plated on the surface of a pressing region of an IC (Integrated Circuit) chip; the metal bumps and the tin layers on the substrate are welded together by welding flux in a mode of inversely mounting the chip; the tin layers, the welding flux, the metal bumps and the IC chip are sequentially arranged on the substrate; the substrate, the tin layers, the welding flux, the metal bumps and the IC chip are surrounded by the package to form the integral circuit; and a power supply and signal channel of the circuit is formed by the IC chip, the metal bumps, the welding flux, the tin layers and the substrate. According to the invention, the plated metal bumps different from conventional metal bumps are adopted; meanwhile, the chip and a frame pin are welded by the welding flux; the conduction and the interconnection between the chip and the pin are directly completed without routing; and the WLCSP single-chip package has the characteristics of low cost and high efficiency.
Description
Technical field
The present invention relates to a kind of WLCSP single-chip package part and plastic packaging method thereof, WLCSP single-chip package part is coated with Au or Cu metal salient point and tin layer, belongs to integrated circuit encapsulation technology field.
Background technology
The fast development of microelectric technique; The increase of integrated circuit complexity; The most function of an electronic system all possibly be integrated in (being SOC(system on a chip)) in the single-chip, and this just correspondingly requires microelectronics Packaging to have higher performance, more lead-in wire, closeer intraconnections, littler size or bigger chip chamber, bigger heat dissipation function, better electrical property, higher reliability, lower single lead-in wire cost etc.Chip package process is changed to wafer level packaging by Chip Packaging one by one, and wafer chip level chip encapsulation technology---WLCSP has just in time satisfied these requirements, has formed noticeable WLCSP technology.
Wafer chip level chip-scale package (Wafer Level Chip Scale Packaging; Be called for short WLCSP), promptly the wafer stage chip packaged type is different from (the envelope survey again of cutting earlier of traditional Chip Packaging mode; And increase the volume of former chip 20% after the encapsulation at least); This kind state-of-the-art technology is on the full wafer wafer, to carry out packaging and testing earlier, just cut into IC particle one by one then, so volume after being encapsulated promptly is equal to the life size of the naked crystalline substance of IC.The packaged type of WLCSP, shorten product sizes significantly not only, and meet the high density demand of running gear for the body space; In the performance of usefulness, more promoted the speed and stability of transfer of data on the other hand.In traditional WLCSP technology, adopt sputter, photoetching, electroplating technology or silk screen printing on wafer, to carry out the mint-mark of circuit.Following flow process is the operating procedure of the wafer of accomplishing preceding road technology being carried out the WLCSP encapsulation:
(1) separator flow process (Isolation Layer)
(2) contact hole flow process (Contact Hole)
(3) pad lower metal layer flow process (UBM Layer)
(4) for electroplating the photoetching flow process (Photolithography for Plating) of preparing
(5) electroplate flow process (Plating)
(6) flow process (Resist Romoval) is removed on the barrier layer
Tradition WLCSP complex manufacturing process, high to the accuracy requirement of plating and photoetching, and cost is higher.
Summary of the invention
The present invention be directed to above-mentioned existing WLCSP defective workmanship; Propose a kind of WLCSP single-chip package part and plastic packaging method thereof, WLCSP single-chip package part is coated with Au or Cu metal salient point and tin layer, adopts the mode of the pressure welding of chemical plating metal salient point, sputter, photoetching, plating or silk-screen printing technique different from the past to generate metal salient point at chip nip metal A l or Cu surface; Simultaneously; Utilize scolder with each salient point of chip and the welding of framework pin, during pressure welding, without routing; Directly accomplished conducting, interconnection between chip and pin, this single-chip package part has low cost, high-efficiency characteristics.
The technical scheme that the present invention adopts: a kind of WLCSP single-chip package part, be coated with Au or Cu metal salient point 4 and tin layer 2, comprise tin layer 2 on substrate 1, the substrate, scolder 3, metal salient point 4, IC chip 5, plastic-sealed body 6; Be coated with tin layer 2 with the metal salient point welding region on the substrate 1; The nip plating metal on surface salient point 4 of IC chip 5; Tin layer 2 adopts the mode of flip-chips to weld together with scolder 3 on metal salient point 4 and the substrate; Be to be to be to be IC chip 5 on metal salient point 4, the metal salient point 4 on scolder 3, the scolder 3 on tin layer 2, the tin layer 2 on the substrate 1; Plastic-sealed body 6 that IC chip 5 has been played support and protective effect has surrounded the integral body that substrate 1, tin layer 2, scolder 3, metal salient point 4, IC chip 5 have constituted circuit, and IC chip 5, metal salient point 4, scolder 3, tin layer 2, substrate 1 have constituted the power supply and the signalling channel of circuit.
A kind of method for packing of WLCSP single-chip package part: metal salient point → scribing → framework corresponding region tin coating → upward core → Reflow Soldering → plastic packaging → back curing → tinization → printing → product separation → check → packing → warehouse-in is planted in wafer attenuate → pressure welding.
The first step, wafer attenuate;
The thickness of wafer attenuate is 50 μ m～200 μ m, roughness Ra 0.10mm～0.30mm;
Second step, plating salient point;
Chip nip metal A u or Cu surface plating 2～50um metal salient point 4 on the full wafer wafer;
The 3rd step, scribing;
The above wafer of 150 μ m adopts common scribing process; The wafer of thickness below 150 μ m adopts double-pole scribing machine and technology thereof;
The 4th step, the framework corresponding region is zinc-plated;
The PAD corresponding region plates the tin layer 2 of one deck 2～50um on substrate 1;
The 5th goes on foot, goes up core;
Turn IC chip 5 around, adopt the technology of Flip-Chip, the metal salient point on the IC chip 54 is welded on the framework;
The 6th step, Reflow Soldering;
Adopt SMT reflow soldering process afterwards, handle, weld together bonding wire on IC chip 5 nips and substrate 1 through melting tin;
The 7th step, plastic packaging, back curing, printing, product separation, check, packing etc. are all identical with common process;
The 8th step, tinization.
Described framework adopts the NiPdAu framework then need not carry out the tin processing.
Beneficial effect of the present invention:
(1) adopt the plating salient point, chemical plating metal salient point, sputter, photoetching, plating or silk-screen printing technique different from the past have low cost, high-efficiency characteristics.
(2) technology of employing Flip-Chip does not use the DAF film bonding, but adopts scolder with each salient point of chip and the welding of framework pin, during pressure welding, without routing, in last core, has just accomplished conducting, interconnection between chip and pin.
Description of drawings
Fig. 1 is a structural representation of the present invention;
Among the figure: tin layer, 3-scolder, 4-metal salient point, 5-IC chip, 6-plastic-sealed body on 1-substrate, the 2-substrate.
Embodiment
Below in conjunction with accompanying drawing and embodiment the present invention is further specified, understand to make things convenient for the technical staff.
As shown in Figure 1: a kind of WLCSP single-chip package part, be coated with Au or Cu metal salient point 4 and tin layer 2, comprise tin layer 2 on substrate 1, the substrate, scolder 3, metal salient point 4, IC chip 5, plastic-sealed body 6; Be coated with tin layer 2 with the metal salient point welding region on the substrate 1; The nip plating metal on surface salient point 4 of IC chip 5; Tin layer 2 adopts the mode of flip-chips to weld together with scolder 3 on metal salient point 4 and the substrate; Be to be to be to be IC chip 5 on metal salient point 4, the metal salient point 4 on scolder 3, the scolder 3 on tin layer 2, the tin layer 2 on the substrate 1; Plastic-sealed body 6 that IC chip 5 has been played support and protective effect has surrounded the integral body that substrate 1, tin layer 2, scolder 3, metal salient point 4, IC chip 5 have constituted circuit, and IC chip 5, metal salient point 4, scolder 3, tin layer 2, substrate 1 have constituted the power supply and the signalling channel of circuit.
A kind of WLCSP single-chip package part is coated with Au or Cu metal salient point 4 and tin layer 2, its method for packing: carry out according to following step:
The first step, wafer attenuate;
The thickness of wafer attenuate is 50 μ m, roughness Ra 0.10mmmm;
Second step, plating salient point;
Chip nip metal A u plating metal on surface salient point 4 on the full wafer wafer;
The 3rd step, scribing;
The wafer of thickness below 150 μ m adopts double-pole scribing machine and technology thereof;
The 4th step, the framework corresponding region is zinc-plated;
The PAD corresponding region plates the tin layer 2 of one deck 2um on substrate 1;
The 5th goes on foot, goes up core;
Turn IC chip 5 around, adopt the technology of Flip-Chip, the metal salient point on the IC chip 54 is welded on the framework;
The 6th step, Reflow Soldering;
Adopt SMT reflow soldering process afterwards, handle, weld together bonding wire on IC chip 5 nips and substrate 1 through melting tin;
The 7th step, plastic packaging, back curing, printing, product separation, check, packing etc. are all identical with common process;
The 8th step, tinization.
A kind of WLCSP single-chip package part is coated with Cu metal salient point 4 and tin layer 2, its method for packing: carry out according to following step:
The first step, wafer attenuate;
The thickness of wafer attenuate is 130 μ m, roughness Ra 0.20mm;
Second step, plating salient point;
Chip nip metal Cu plating metal on surface salient point 4 on the full wafer wafer;
The 3rd step, scribing;
The wafer of thickness below 150 μ m adopts double-pole scribing machine and technology thereof;
The 4th step, the framework corresponding region is zinc-plated;
The PAD corresponding region plates the tin layer 2 of one deck 25um on substrate 1;
The 5th goes on foot, goes up core;
The 6th step, Reflow Soldering;
Adopt SMT reflow soldering process afterwards, handle, weld together bonding wire on IC chip 5 nips and substrate 1 through melting tin;
The 7th step, plastic packaging, back curing, printing, product separation, check, packing etc. are all identical with common process;
The 8th step, tinization.
A kind of WLCSP single-chip package part is coated with Au or Cu metal salient point 4 and tin layer 2, its method for packing: carry out according to following step:
The first step, wafer attenuate;
The thickness of wafer attenuate is 200 μ m, roughness Ra 0.30mm;
Second step, plating salient point;
Chip nip metal A l or Cu plating metal on surface salient point 4 on the full wafer wafer;
The 3rd step, scribing;
The above wafer of 150 μ m adopts common scribing process;
The 4th step, the framework corresponding region is zinc-plated;
The PAD corresponding region plates the tin layer 2 of one deck 50um on substrate 1;
The 5th goes on foot, goes up core;
The 6th step, Reflow Soldering;
Adopt SMT reflow soldering process afterwards, handle, weld together bonding wire on IC chip 5 nips and substrate 1 through melting tin;
The 7th step, plastic packaging, back curing, printing, product separation, check, packing etc. are all identical with common process;
The 8th step, tinization.
A kind of WLCSP single-chip package part is coated with Au or Cu metal salient point 4 and tin layer 2, if then it goes without doing the tin processing of NiPdAu framework.
Claims (3)
1. a WLCSP single-chip package part is characterized in that: comprise tin layer on substrate, the substrate, scolder, metal salient point, IC chip, plastic-sealed body; Be coated with the tin layer with the metal salient point welding region on the substrate; The nip plating metal on surface salient point of IC chip; The tin layer adopts the mode of flip-chip to weld together with scolder on metal salient point and the substrate; Be to be to be to be the IC chip on metal salient point, the metal salient point on scolder, the scolder on tin layer, the tin layer on the substrate; Plastic-sealed body that the IC chip has been played support and protective effect has surrounded the integral body that substrate, tin layer, scolder, metal salient point, IC chip have constituted circuit, and IC chip, metal salient point, scolder, tin layer, substrate have constituted the power supply and the signalling channel of circuit.
2. the method for packing of a WLCSP single-chip package part, it is characterized in that: method for packing specifically carries out according to following step;
The first step, wafer attenuate;
The thickness of wafer attenuate is 50 μ m～200 μ m, roughness Ra 0.10mm～0.30mm;
Second step, plating salient point;
Chip nip metal A u or Cu surface plating 2～50um metal salient point on the full wafer wafer;
The 3rd step, scribing;
The above wafer of 150 μ m adopts common scribing process; The wafer of thickness below 150 μ m adopts double-pole scribing machine and technology thereof;
The 4th step, the framework corresponding region is zinc-plated;
The PAD corresponding region plates the tin layer of one deck 2～50um on substrate;
The 5th goes on foot, goes up core;
Turn the IC chip around, adopt the technology of Flip-Chip, the metal salient point on the IC chip is welded on the framework;
The 6th step, Reflow Soldering;
Adopt SMT reflow soldering process afterwards, handle, weld together bonding wire and substrate on the IC chip nip through melting tin;
The 7th step, plastic packaging, back curing, printing, product separation, check, packing etc. are all identical with common process;
The 8th step, tinization.
3. the method for packing of a kind of WLCSP single-chip package part based on substrate according to claim 2 is characterized in that: adopt the NiPdAu framework need not do the tin processing.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210306611XA CN102842561A (en) | 2012-08-21 | 2012-08-21 | WLCSP (Wafer Level Chip Size Packaging) single-chip package and packaging method thereof |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201210306611XA CN102842561A (en) | 2012-08-21 | 2012-08-21 | WLCSP (Wafer Level Chip Size Packaging) single-chip package and packaging method thereof |
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| CN102842561A true CN102842561A (en) | 2012-12-26 |
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2004119801A (en) * | 2002-09-27 | 2004-04-15 | Alps Electric Co Ltd | Method for forming solder bump |
| CN102263070A (en) * | 2011-06-13 | 2011-11-30 | 西安天胜电子有限公司 | Wafer level chip scale packaging (WLCSP) piece based on substrate packaging |
| CN102263078A (en) * | 2011-06-13 | 2011-11-30 | 西安天胜电子有限公司 | WLCSP (Wafer Level Chip Scale Package) packaging component |
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2012
- 2012-08-21 CN CN201210306611XA patent/CN102842561A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2004119801A (en) * | 2002-09-27 | 2004-04-15 | Alps Electric Co Ltd | Method for forming solder bump |
| CN102263070A (en) * | 2011-06-13 | 2011-11-30 | 西安天胜电子有限公司 | Wafer level chip scale packaging (WLCSP) piece based on substrate packaging |
| CN102263078A (en) * | 2011-06-13 | 2011-11-30 | 西安天胜电子有限公司 | WLCSP (Wafer Level Chip Scale Package) packaging component |
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| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20121226 |
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| RJ01 | Rejection of invention patent application after publication |