CN102789999A - Defect detecting method for utilizing graphic features to scan and manufacturing method of semiconductor chip - Google Patents
Defect detecting method for utilizing graphic features to scan and manufacturing method of semiconductor chip Download PDFInfo
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- CN102789999A CN102789999A CN2012102933983A CN201210293398A CN102789999A CN 102789999 A CN102789999 A CN 102789999A CN 2012102933983 A CN2012102933983 A CN 2012102933983A CN 201210293398 A CN201210293398 A CN 201210293398A CN 102789999 A CN102789999 A CN 102789999A
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Abstract
The invention provides a defect detecting method for utilizing graphic features to scan and a manufacturing method of a semiconductor chip. The defect detecting method for utilizing graphic features to scan according to the invention comprises the following steps: 1) defining a repeated unit structure according to a semiconductor structure; 2) inputting a data graph of the repeated unit structure defined in the step 1) to a defect detecting program; 3) inputting a physical repeated structure of the semiconductor structure on the chip to the defect detecting program; 4) comparing the graphic features of the physical repeated structure and the data graph in the defect detecting program; and 5) detecting a defect position according to the compared difference from the step 4). The invention provides a high-precision and high-flexibility defect detecting method for detecting the defects in a same position on the repeated unit structure, such as a memory.
Description
Technical field
The present invention relates to field of semiconductor manufacture; More particularly; The present invention relates to a kind of defect inspection method that utilizes graphic feature scanning, in addition, the invention still further relates to a kind of manufacturing method for semiconductor chips that has adopted this to utilize the defect inspection method of graphic feature scanning.
Background technology
Along with the technology of integrated circuit constantly promotes; Number of devices on the unit are chip is also more and more; Particularly the semiconductor regions such as memory area is the highest place of device integrated level on the chip, so the slight change on the device architecture all can cause the inefficacy of final electrical property.
In order to pinpoint the problems timely in process of production and to take appropriate measures, in manufacture process, all can dispose the optics of some and the defects detection equipment of electronics at present.And the operation principle of defects detection is that the optical imagery on the chip is converted into the data image that can be represented by the bright dull gray of difference rank; Fig. 1 representes be exactly with a light microscope down image P1 is converted into the process of data image characteristic P2; Relatively detect the position of defective again through the data on the adjacent chips; What represent like Fig. 2 is the comparison of the adjacent chips of X1 in the horizontal direction, and what Fig. 3 represented is the comparison in the adjacent chips of vertical direction X2.
But; Because the regular duplicate devices such as memory all is the unit of repetition on physical structure, as shown above, A and B are two identical minimized memory repetitives; The place that the figure upward arrow is pointed out is the position that has defective; But, be to detect this problem (that is " same position of each repetitive all has same defect to exist " this problem) that exists on the chip with conventional detection in all defective existence of the same position of each repetitive.
Therefore, hope can provide a kind of and can detect the high accuracy of the defective of same position on the repeat unit structure such as memory and defect inspection method flexibly.
Summary of the invention
Technical problem to be solved by this invention is to having above-mentioned defective in the prior art, provides a kind of and can detect the high accuracy of the defective of same position on the repeat unit structure such as memory and defect inspection method flexibly.
According to a first aspect of the invention, a kind of defect inspection method that utilizes graphic feature scanning is provided, it comprises: first step: according to semiconductor structure definition repeat unit structure; Second step: the datagraphic of the repeat unit structure that will be defined by said first step is input to the defects detection program; Third step: the program that the physics repetitive structure of the said semiconductor structure on the chip is input to said defects detection; The 4th step: in the defects detection program, physics repetitive structure and datagraphic are carried out the comparison of graphic feature; The 5th step: the position of detecting defective according to the difference of the 4th step comparison.
Preferably, in the above-mentioned defect inspection method that utilizes graphic feature scanning, in said the 5th step, defective locations is confirmed as in the position that there are differences between said physics repetitive structure and the said datagraphic.
Preferably, in the above-mentioned defect inspection method that utilizes graphic feature scanning, in said first step, according to memory construction definition repeat unit structure.
Preferably, in the above-mentioned defect inspection method that utilizes graphic feature scanning, in said first step, define minimum repetitive.
Preferably, in the above-mentioned defect inspection method that utilizes graphic feature scanning, in said third step, the physics repetitive structure of the memory on the chip is input to the defects detection program.
Preferably, in the above-mentioned defect inspection method that utilizes graphic feature scanning, in said the 4th step, the physics repetitive structure and the datagraphic of memory carried out the comparison of graphic feature
According to a second aspect of the invention, a kind of described according to a first aspect of the invention manufacturing method for semiconductor chips that utilizes the defect inspection method of graphic feature scanning that adopted is provided.
According to the present invention, provide a kind of and can detect the high accuracy of the defective of same position on the repeat unit structure such as memory and defect inspection method flexibly.
Description of drawings
In conjunction with accompanying drawing, and, will more easily more complete understanding be arranged and more easily understand its attendant advantages and characteristic the present invention through with reference to following detailed, wherein:
Fig. 1 schematically shows the sketch map that the circuit optical imagery is converted into the data gray scale image.
Fig. 2 schematically shows the sketch map of horizontal direction defects detection.
Fig. 3 schematically shows the sketch map of vertical direction defects detection.
Fig. 4 schematically shows the defective of repetitive.
Fig. 5 schematically shows the domain definition reservoir repeat unit structure sketch map according to the embodiment of the invention.
Fig. 6 schematically shows the flow chart according to the defect inspection method that utilizes graphic feature scanning of the embodiment of the invention.
Need to prove that accompanying drawing is used to explain the present invention, and unrestricted the present invention.Notice that the accompanying drawing of expression structure possibly not be to draw in proportion.And in the accompanying drawing, identical or similar elements indicates identical or similar label.
Embodiment
In order to make content of the present invention clear more and understandable, content of the present invention is described in detail below in conjunction with specific embodiment and accompanying drawing.
Inventor of the present invention advantageously finds; Because it all is the unit of repetition on physical structure that the rule such as memory repeats semiconductor device; So when defects detection, can obtain the minimum structure that periodically repeats that has, thereby find the position of defective through the comparison that repetitive structure carries out data in level or vertical direction at the memory area of chip.
Know-why of the present invention is repetitive cell1, cell2, cell3 and the cell4 that on the layout file of chip, defines the semiconductor device such as memory through a terminal; As shown in Figure 5; Again this file (repetitive) is imported in the program of defects detection; Equipment extracts the highest actual physics cellular construction of matching degree automatically according to the repetitive that defines on chip; The graphic data image of this memory construction is input in the program of defects detection; Actual storage cellular construction in the actual detected process on each chip is all handled with the comparison that the structure of above-mentioned definition is made the figure characteristic, so just can solve the difficult problem that the same position defective can't be to be detected on the memory repetitive structure, thereby realizes a kind of high accuracy and defect inspection method flexibly.
Utilize technology of the present invention; Equipment finds the highest physical structure of matching degree automatically according to the good cellular construction of circuit layout document definition; When actual defects detected, repetitive on the wafer (for example memory repetitive) and said structure were done the comparison of figure, just can detect the defective that is present in same position on the memory repeat unit structure; Avoid existing detection technique blind spot on this problem, realize high Precision Detection memory area.
In the production of reality; The minimum repetitive structure of the memory that will on domain, define is input in the trace routine; In the defect inspection process of reality; Equipment finds the highest physical location structure of matching degree and its figure optical signalling is converted into data-signal through the image comparison, and each memory construction to be detected all through doing the figure comparison with the structure of above-mentioned definition, just can detect the defective on the memory shown in Figure 4 apace.
Thus, Fig. 6 schematically shows the flow chart according to the defect inspection method that utilizes graphic feature scanning of the embodiment of the invention.As shown in Figure 6, can comprise the steps: according to the defect inspection method that utilizes graphic feature scanning of the embodiment of the invention
First step S1:, for example, define repeat unit structure according to memory construction for the situation of memory according to semiconductor structure definition repeat unit structure.In addition, preferably define minimum repetitive; In other words, scope of the present invention is not limited to define the minimum repetitive of semiconductor structure, and for example, repeat unit structure can comprise two or more minimum repetitives, and this definition also falls into protection scope of the present invention.Certainly, preferably, preferably define minimum repetitive to improve precision of the present invention.
The second step S2: the datagraphic of the repeat unit structure that will be defined by first step S1 is input to the defects detection program; For example, for the situation of memory, can the datagraphic of the repeat unit structure of memory be input to the defects detection program;
Third step S3: the program that the physics repetitive structure of the semiconductor structure on the chip is input to defects detection; For example, for the situation of memory, the physics repetitive structure of the memory on the chip is input to the defects detection program;
The 4th step S4: in the defects detection program, physics repetitive structure and datagraphic are carried out the comparison of graphic feature; For example, for the situation of memory, can the physics repetitive structure and the datagraphic of memory be carried out the comparison of graphic feature;
The 5th step S5: the position of detecting defective according to the difference of the 4th step S4 comparison.
More particularly, in the 5th step S5, defective locations is confirmed as in the position that there are differences between physics repetitive structure and the datagraphic, i.e. the position of the defective of same position on the repeat unit structure.
Thus, the embodiment of the invention provides a kind of and can detect the high accuracy of the defective of same position on the repeat unit structure such as memory and defect inspection method flexibly.
According to another preferred embodiment of the invention, the present invention also provides a kind of above-mentioned manufacturing method for semiconductor chips that utilizes the defect inspection method of graphic feature scanning that adopted.
It is understandable that though the present invention with the preferred embodiment disclosure as above, yet the foregoing description is not in order to limit the present invention.For any those of ordinary skill in the art; Do not breaking away under the technical scheme scope situation of the present invention; All the technology contents of above-mentioned announcement capable of using is made many possible changes and modification to technical scheme of the present invention, or is revised as the equivalent embodiment of equivalent variations.Therefore, every content that does not break away from technical scheme of the present invention, all still belongs in the scope of technical scheme protection of the present invention any simple modification, equivalent variations and modification that above embodiment did according to technical spirit of the present invention.
Claims (7)
1. defect inspection method that utilizes graphic feature scanning is characterized in that comprising:
First step: according to semiconductor structure definition repeat unit structure;
Second step: the datagraphic of the repeat unit structure that will be defined by said first step is input to the defects detection program;
Third step: the program that the physics repetitive structure of the said semiconductor structure on the chip is input to said defects detection;
The 4th step: in the defects detection program, physics repetitive structure and datagraphic are carried out the comparison of graphic feature;
The 5th step: the position of detecting defective according to the difference of the 4th step comparison.
2. the defect inspection method that utilizes graphic feature scanning according to claim 1 is characterized in that, in said the 5th step, defective locations is confirmed as in the position that there are differences between said physics repetitive structure and the said datagraphic.
3. the defect inspection method that utilizes graphic feature scanning according to claim 1 and 2 is characterized in that, in said first step, according to memory construction definition repeat unit structure.
4. the defect inspection method that utilizes graphic feature scanning according to claim 1 and 2 is characterized in that, in said first step, defines minimum repetitive.
5. the defect inspection method that utilizes graphic feature scanning according to claim 1 and 2 is characterized in that, in said third step, the physics repetitive structure of the memory on the chip is input to the defects detection program.
6. the defect inspection method that utilizes graphic feature scanning according to claim 1 and 2 is characterized in that, in said the 4th step, the physics repetitive structure and the datagraphic of memory is carried out the comparison of graphic feature.
7. one kind has been adopted according to the described manufacturing method for semiconductor chips that utilizes the defect inspection method of graphic feature scanning of one of claim 1 to 6.
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Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103915361A (en) * | 2014-04-08 | 2014-07-09 | 上海华力微电子有限公司 | Method for detecting chip defects |
| CN104103541A (en) * | 2014-08-01 | 2014-10-15 | 上海华力微电子有限公司 | Selective detection method for defect |
| CN104157586A (en) * | 2014-08-08 | 2014-11-19 | 上海华力微电子有限公司 | Method of precisely positioning and analyzing repeated structure defects found by electron beam defect detection |
| CN104362082A (en) * | 2014-11-10 | 2015-02-18 | 上海华力微电子有限公司 | Method of determining suspicious process steps according to peeling defect of special circuit structures |
| CN104425302A (en) * | 2013-09-04 | 2015-03-18 | 中芯国际集成电路制造(上海)有限公司 | Defect detection method and device of semiconductor device |
| CN107967401A (en) * | 2017-12-21 | 2018-04-27 | 上海华力微电子有限公司 | A kind of domain repetitive unit matching inspection method and system |
| CN109604191A (en) * | 2017-10-04 | 2019-04-12 | 三菱电机株式会社 | Semiconductor device sorting system and semiconductor device |
| CN112444526A (en) * | 2019-09-05 | 2021-03-05 | 中芯国际集成电路制造(上海)有限公司 | Defect detection method and defect detection system |
| CN114090462A (en) * | 2021-12-07 | 2022-02-25 | 上海复深蓝软件股份有限公司 | Software repeated defect identification method and device, computer equipment and storage medium |
| CN114358168A (en) * | 2021-12-29 | 2022-04-15 | 苏州赛美特科技有限公司 | Data comparison method, device equipment and storage medium |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20020113234A1 (en) * | 2001-02-21 | 2002-08-22 | Hirohito Okuda | Method and system for inspecting electronic circuit pattern |
| US20040105578A1 (en) * | 2002-08-21 | 2004-06-03 | Hideo Tsuchiya | Pattern inspection apparatus |
| CN101026113A (en) * | 2006-02-21 | 2007-08-29 | 台湾积体电路制造股份有限公司 | Recognition method and system |
| CN100582754C (en) * | 2002-12-19 | 2010-01-20 | 飞思卡尔半导体公司 | System and method for detecting wafer defect |
| CN102623368A (en) * | 2012-03-31 | 2012-08-01 | 上海集成电路研发中心有限公司 | Wafer defect detection method |
-
2012
- 2012-08-16 CN CN2012102933983A patent/CN102789999A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20020113234A1 (en) * | 2001-02-21 | 2002-08-22 | Hirohito Okuda | Method and system for inspecting electronic circuit pattern |
| US20040105578A1 (en) * | 2002-08-21 | 2004-06-03 | Hideo Tsuchiya | Pattern inspection apparatus |
| CN100582754C (en) * | 2002-12-19 | 2010-01-20 | 飞思卡尔半导体公司 | System and method for detecting wafer defect |
| CN101026113A (en) * | 2006-02-21 | 2007-08-29 | 台湾积体电路制造股份有限公司 | Recognition method and system |
| CN102623368A (en) * | 2012-03-31 | 2012-08-01 | 上海集成电路研发中心有限公司 | Wafer defect detection method |
Cited By (15)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104425302B (en) * | 2013-09-04 | 2017-09-22 | 中芯国际集成电路制造(上海)有限公司 | The defect inspection method and device of semiconductor devices |
| CN104425302A (en) * | 2013-09-04 | 2015-03-18 | 中芯国际集成电路制造(上海)有限公司 | Defect detection method and device of semiconductor device |
| CN103915361A (en) * | 2014-04-08 | 2014-07-09 | 上海华力微电子有限公司 | Method for detecting chip defects |
| CN104103541A (en) * | 2014-08-01 | 2014-10-15 | 上海华力微电子有限公司 | Selective detection method for defect |
| CN104103541B (en) * | 2014-08-01 | 2019-07-09 | 上海华力微电子有限公司 | The method that a kind of pair of defect carries out selective enumeration method |
| CN104157586A (en) * | 2014-08-08 | 2014-11-19 | 上海华力微电子有限公司 | Method of precisely positioning and analyzing repeated structure defects found by electron beam defect detection |
| CN104157586B (en) * | 2014-08-08 | 2017-03-08 | 上海华力微电子有限公司 | The method being accurately positioned the repetitive structure defect that analysis electron beam defects detection finds |
| CN104362082B (en) * | 2014-11-10 | 2017-03-08 | 上海华力微电子有限公司 | Come off the method that defect determines suspicious processing step according to special circuit structure |
| CN104362082A (en) * | 2014-11-10 | 2015-02-18 | 上海华力微电子有限公司 | Method of determining suspicious process steps according to peeling defect of special circuit structures |
| CN109604191A (en) * | 2017-10-04 | 2019-04-12 | 三菱电机株式会社 | Semiconductor device sorting system and semiconductor device |
| CN107967401A (en) * | 2017-12-21 | 2018-04-27 | 上海华力微电子有限公司 | A kind of domain repetitive unit matching inspection method and system |
| CN107967401B (en) * | 2017-12-21 | 2021-07-16 | 上海华力微电子有限公司 | Layout repeat unit matching performance checking method and system |
| CN112444526A (en) * | 2019-09-05 | 2021-03-05 | 中芯国际集成电路制造(上海)有限公司 | Defect detection method and defect detection system |
| CN114090462A (en) * | 2021-12-07 | 2022-02-25 | 上海复深蓝软件股份有限公司 | Software repeated defect identification method and device, computer equipment and storage medium |
| CN114358168A (en) * | 2021-12-29 | 2022-04-15 | 苏州赛美特科技有限公司 | Data comparison method, device equipment and storage medium |
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Application publication date: 20121121 |