CN102754211B - Ldmos power device - Google Patents
Ldmos power device Download PDFInfo
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- CN102754211B CN102754211B CN201080052919.5A CN201080052919A CN102754211B CN 102754211 B CN102754211 B CN 102754211B CN 201080052919 A CN201080052919 A CN 201080052919A CN 102754211 B CN102754211 B CN 102754211B
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- 239000000758 substrate Substances 0.000 claims abstract description 33
- 230000005611 electricity Effects 0.000 claims description 20
- 239000004065 semiconductor Substances 0.000 claims description 3
- 239000003990 capacitor Substances 0.000 abstract description 7
- 230000000694 effects Effects 0.000 description 2
- 238000005728 strengthening Methods 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
- H01L29/7835—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
- H01L29/41725—Source or drain electrodes for field effect devices
- H01L29/4175—Source or drain electrodes for field effect devices for lateral devices where the connection to the source or drain region is done through at least one part of the semiconductor substrate thickness, e.g. with connecting sink or with via-hole
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
- H01L29/41725—Source or drain electrodes for field effect devices
- H01L29/41766—Source or drain electrodes for field effect devices with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/402—Field plates
Abstract
The invention discloses a kind of LDMOS power device, comprise the first conductive type epitaxial layer on substrate, substrate and be formed at source area and the drain region on the first conductive type epitaxial layer, described source area and substrate conduction is connected, and described substrate is and the second conductivity type substrate of the first conductivity type opposite. The present invention need not reduce under the prerequisite of other parameter index, has reduced grid to the capacitor C gs of source electrode and the capacitor C ds of drain-to-source, has realized device high-gain and high efficiency work under radio frequency conditions.
Description
Technical field
The present invention relates to a kind of LDMOS power device.
Background technology
Existing LDMOS power device (radio-frequency power device) structural design as shown in Figure 1, is wrappedDraw together on P type epitaxial layer on P type heavy doping substrate, P type heavy doping substrate and P type epitaxial layerSource area and drain region, wherein source area is connected with doped substrate conduction in P type, source area and drain electrodeBetween district, be provided with channel region, the top of channel region is provided with grid. LDMOS power device is in the time of high-frequencyPerformance be mainly limited to grid to the capacitor C gs of source electrode and the capacitor C ds of drain-to-source. CgsSize mainly decided by grid length and thickness of grid oxide layer, these two parameters are also controlled simultaneouslyDevice transconductance parameters gm. The reliability that reduction Cgs will sacrifice gm or device (for example increases narrowChannelling effect), otherwise be difficult to reduce Cgs. Cds is decided by the size in light doping section (LDD district),LDD district has also determined the size of opening resistor Rdson and breakdown voltage BVdss. Once optimizeLDD district realizes best Rdson and BVdss, reduce Cds simultaneously and also be difficult to.
Summary of the invention
The object of the invention is to provide a kind of LDMOS power device, need not reduce other parameter indexPrerequisite under, reduced grid to the capacitor C gs of source electrode and the capacitor C ds of drain-to-source, realizeDevice high-gain and high efficiency work under radio frequency conditions.
Technical scheme of the present invention is: a kind of LDMOS power device, comprises on substrate, substrateThe first conductive type epitaxial layer and be formed at source area and the drain electrode on the first conductive type epitaxial layerDistrict, described source area is connected with substrate conduction, and described substrate is and second of the first conductivity type oppositeConductivity type substrate. Wherein the first conduction type and the second conduction type refer to P type or N-type,In the time that the first conduction type is P type, the second conduction type is N-type; When the second conduction type is PWhen type, the first conduction type is N-type. LDMOS device for high voltage and high-breakdown-voltage shouldWith, owing to existing between a knot and exhausting between the first conductive type epitaxial layer and the second conductivity type substrateDistrict, the present invention the first conductive type epitaxial layer is compared has the first conductivity type substrate conventionallyLDMOS power device is thick.
Further, described source area is connected in the second conductivity type substrate by conductive trench, orDescribed in person, source area is connected to the second conductivity type substrate bottom, described source area by conducting electricity full via holeSurface is provided with the ohmic contact regions, source being connected with conductive trench or the full hole-through conductive that conducts electricity.
Further, ohmic contact regions, described source is extended to conductive trench or is conducted electricity complete by source area surfaceVia hole top is also directly connected with conductive trench or the full via hole that conducts electricity, and makes source area ground connection.
Or further, described LDMOS power device semiconductor surface is provided with oxide layer, described inIn oxide layer, be provided with conductive layer, described conductive layer (or is led with ohmic contact regions, source and conductive trench respectivelyThe full via hole of electricity) conduction connection, make source area ground connection.
Further, on described the first conductive type epitaxial layer also in conductive trench or conduct electricity full via hole weekBe arranged with the second conduction type heavy doping being connected with substrate and connect groove, be used for strengthening the conduction of ground connectionProperty.
Advantage of the present invention is:
1, the present invention arranges the first conductive type epitaxial layer in the second conductivity type substrate, makesBetween one conductive type epitaxial layer and the second conductivity type substrate, produce an electric capacity, this electric capacity and CgsWith Cds series connection, thereby reduced Cgs and Cds, realized under radio frequency conditions device high-gain andHigh efficiency work. The present invention can make Cgs and Cds reduce at least 20%, thereby makes LDMOSThe improving gain of power device at least 1dB, efficiency improves at least 2%.
2, when the first conduction type is P type, when the second conduction type is N-type, work of the present inventionIn journey, only have electron stream to pass through conductive trench (or conduct electricity full via hole) and the heavily doped connection raceway groove of N-type ground connection,Do not have gap stream, and traditional LDMOS power device is at the heavily doped connection raceway groove of P type and P type weightMix between substrate and have gap stream, so the present invention only has the device design of electron stream to have higherEfficiency.
Brief description of the drawings
Fig. 1 is the structural representation of prior art LDMOS power device;
Fig. 2 is the structural representation of the specific embodiment of the invention one;
Fig. 3 is the structural representation of the specific embodiment of the invention two;
Fig. 4 is the structural representation of the specific embodiment of the invention three.
Wherein: 1 substrate; 1a the second conductivity type substrate; 2 first conductive type epitaxial layers; 3 sourcesOhmic contact regions; 4 conductive trench; The full via hole of 5 conduction; 6 oxide layers; 7 conductive layers; 8 second leadThe heavy doping of electricity type connects groove; 9 first conduction type doped channel regions; 10 second conduction type weightsDoped drain; 11 second conduction type drift regions; 12 grid; 13 second conduction type heavy doping source regions;14 first conduction type heavy doping source regions; 15 field plates; 16 leak ohmic contact regions.
Detailed description of the invention
Below in conjunction with drawings and Examples, the invention will be further described:
Embodiment: as shown in Figures 2 to 4, a kind of LDMOS power device, comprises the second conductionThe first conductive type epitaxial layer 2 and shape on type substrates 1a, the second conductivity type substrate 1aBe formed in source area and drain region on the first conductive type epitaxial layer 2, described source area and substrate 1 are ledElectrical connection. Between described source area and drain region, be also provided with the first conduction type doped channel regions 9. InstituteStating drain region comprises the second conduction type heavy doping drain region 10 and is isolated in the first conduction type dopingThe second conduction type drift region 11 between channel region 9 and the second conduction type heavy doping drain region 10,Wherein the surface in the second conduction type heavy doping drain region 10 is provided with Lou ohmic contact regions 16. LDMOSThe grid 12 of power device are located in the oxide layer 6 of 9 tops, the first conduction type doped channel regions, thisOuter LDMOS power device can also be provided for the field plate 15 of ground connection in oxide layer 6.
Described source area comprises the second conduction type heavy doping source region 13 and the first conduction type heavy dopingSource region 14, as shown in Figures 2 and 3. Now the second conduction type heavy doping source region 13 is positioned at firstOn conduction type heavy doping source region 14 and the first conduction type doped channel regions 9. Described source areaCan also only include the second conduction type heavy doping source region 13, as shown in Figure 4, now the first conduction classType doped channel regions 9 stretches out and surrounds the second conduction type heavy doping source region 13.
In the present embodiment, the first conduction type is P type, and the second conduction type is N-type.
It is upper that described source area is connected to the second conductivity type substrate 1a by conductive trench 4, or instituteState source area and be connected to the second conductivity type substrate 1a bottom ground connection, (Fig. 2 by conducting electricity full via hole 5Show to conductive trench in Fig. 44 and the full via hole 5 of conduction simultaneously, but in the time that reality is used, twoPerson only has one) described source area surface is provided with conductive trench 4 or the full via hole 5 that conducts electricity and conducts electricityThe ohmic contact regions, source 3 connecting. Source area is connected and ground connection with substrate 1.
Wherein, ohmic contact regions, described source 3 is extended to conductive trench 4 or is conducted electricity complete by source area surfaceVia hole 5 tops are also directly connected with conductive trench 4 or the full via hole 5 that conducts electricity, as shown in Figure 2. This realityExecute in example the second conduction type heavy doping source region 13 can also stretch out as shown in phantom in Figure 2 withConductive trench 4 or the full via hole 5 that conducts electricity directly connect, enhanced grounding effect. Or, described LDMOSPower device semiconductor surface is provided with oxide layer 6, in described oxide layer 6, is provided with conductive layer 7, described inConductive layer 7 connects with ohmic contact regions, source 3 and conductive trench 4 (or conduct electricity full via hole 5) conduction respectivelyConnect, as shown in Figure 3 and Figure 4.
On described the first conductive type epitaxial layer 2, also around go back in conductive trench 4 or the full via hole 5 that conducts electricityCan be provided with the second conduction type heavy doping being connected with substrate 1 and connect groove 8. This second conduction classType heavy doping connects groove 8 can be used for strengthening the electric conductivity of ground connection.
Between the first conduction type doped region and grounding parts outside the second conduction type heavy doping source region 13Keep the distance of at least 4 microns. Wherein above-mentioned the first conduction type doped region is institute in Fig. 2 and Fig. 3The first conduction type doped channel shown in the first conduction type heavy doping source region 14 or the Fig. 4 showingDistrict 9; Grounding parts is conductive trench 4 or conducts electricity full via hole 5 and/or the second conduction type heavy doping and connectGroove 8. Concrete: Fig. 2 is connected groove 8 and first with the second conduction type heavy doping in Fig. 3Distance a between conduction type heavy doping source region 14 is at least 4 microns; In Fig. 4 second conductionThe distance b that type heavy doping connects between groove 8 and the first conduction type doped channel regions 9 is at least4 microns.
The present invention need not reduce under the prerequisite of other parameter index, has reduced the electric capacity of grid to source electrodeThe capacitor C ds of Cgs and drain-to-source, has realized device high-gain and high efficiency under radio frequency conditionsWork.
Claims (3)
1. a LDMOS power device, comprises the first conductive type epitaxial layer on substrate, substrateAnd be formed at source area and the drain region on the first conductive type epitaxial layer (2), described source (2)Polar region is connected with substrate conduction, it is characterized in that: described substrate is and second of the first conductivity type oppositeConductivity type substrate (1a); Described source area is connected to the second conduction type lining by conductive trench (4)The end (1a), is upper, or described source area is connected to the second conduction type lining by the full via hole of conduction (5)Bottom, the end (1a), described source area surface is provided with conductive trench (4) or the full via hole (5) that conducts electricity and leadsThe ohmic contact regions, source (3) of electrical connection; On described the first conductive type epitaxial layer (2) also in conduction ditchGroove (4) or the full via hole (5) that conducts electricity be around provided be connected with the second conductivity type substrate (1a) secondConduction type heavy doping connects groove (8), and the first conduction type doping source region or the first conduction type are mixedThe distance that assorted channel region and the second conduction type heavy doping are connected between groove (8) is at least 4 microns.
2. LDMOS power device according to claim 1, is characterized in that: Europe, described sourceNurse contact zone (3) extends to conductive trench (4) by source area surface or conducts electricity full via hole (5) topAnd be directly connected with conductive trench (4) or the full via hole (5) that conducts electricity.
3. LDMOS power device according to claim 1, is characterized in that: described LDMOSPower device semiconductor surface is provided with oxide layer (6), is provided with conductive layer (7) in described oxide layer (6),Described conductive layer (7) respectively with ohmic contact regions, source (3) and conductive trench (4) or the full via hole that conducts electricity(5) conduction connects.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201080052919.5A CN102754211B (en) | 2009-11-19 | 2010-11-02 | Ldmos power device |
Applications Claiming Priority (5)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN200910246051A CN101699630A (en) | 2009-11-19 | 2009-11-19 | Ldmos power device |
| CN2009102460511 | 2009-11-19 | ||
| CN200910246051.1 | 2009-11-19 | ||
| PCT/CN2010/078346 WO2011060686A1 (en) | 2009-11-19 | 2010-11-02 | Ldmos power device |
| CN201080052919.5A CN102754211B (en) | 2009-11-19 | 2010-11-02 | Ldmos power device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN102754211A CN102754211A (en) | 2012-10-24 |
| CN102754211B true CN102754211B (en) | 2016-05-11 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN200910246051A Pending CN101699630A (en) | 2009-11-19 | 2009-11-19 | Ldmos power device |
| CN201080052919.5A Active CN102754211B (en) | 2009-11-19 | 2010-11-02 | Ldmos power device |
Family Applications Before (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN200910246051A Pending CN101699630A (en) | 2009-11-19 | 2009-11-19 | Ldmos power device |
Country Status (2)
| Country | Link |
|---|---|
| CN (2) | CN101699630A (en) |
| WO (1) | WO2011060686A1 (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101699630A (en) * | 2009-11-19 | 2010-04-28 | 苏州远创达科技有限公司 | Ldmos power device |
| CN102760771B (en) * | 2012-07-30 | 2016-03-16 | 昆山华太电子技术有限公司 | For the novel grid structure of RF-LDMOS device |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5869875A (en) * | 1997-06-10 | 1999-02-09 | Spectrian | Lateral diffused MOS transistor with trench source contact |
| CN1707809A (en) * | 2004-06-08 | 2005-12-14 | Nec化合物半导体器件株式会社 | Semiconductor device |
| CN2836241Y (en) * | 2005-10-14 | 2006-11-08 | 西安电子科技大学 | Integrated high-voltage P-type LDMOS transistor structure |
| CN101699630A (en) * | 2009-11-19 | 2010-04-28 | 苏州远创达科技有限公司 | Ldmos power device |
| CN201549512U (en) * | 2009-11-19 | 2010-08-11 | 苏州远创达科技有限公司 | Ldmos power device |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP5114927B2 (en) * | 2006-11-15 | 2013-01-09 | 株式会社デンソー | Horizontal MOS transistor |
-
2009
- 2009-11-19 CN CN200910246051A patent/CN101699630A/en active Pending
-
2010
- 2010-11-02 CN CN201080052919.5A patent/CN102754211B/en active Active
- 2010-11-02 WO PCT/CN2010/078346 patent/WO2011060686A1/en active Application Filing
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5869875A (en) * | 1997-06-10 | 1999-02-09 | Spectrian | Lateral diffused MOS transistor with trench source contact |
| CN1707809A (en) * | 2004-06-08 | 2005-12-14 | Nec化合物半导体器件株式会社 | Semiconductor device |
| CN2836241Y (en) * | 2005-10-14 | 2006-11-08 | 西安电子科技大学 | Integrated high-voltage P-type LDMOS transistor structure |
| CN101699630A (en) * | 2009-11-19 | 2010-04-28 | 苏州远创达科技有限公司 | Ldmos power device |
| CN201549512U (en) * | 2009-11-19 | 2010-08-11 | 苏州远创达科技有限公司 | Ldmos power device |
Also Published As
| Publication number | Publication date |
|---|---|
| CN101699630A (en) | 2010-04-28 |
| CN102754211A (en) | 2012-10-24 |
| WO2011060686A1 (en) | 2011-05-26 |
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