JP5114927B2 - Horizontal MOS transistor - Google Patents

Description

  The present invention relates to a lateral MOS transistor (LDMOS, Lateral Diffused Metal Oxide Semiconductor) in which striped source regions and drain regions are alternately arranged on a surface layer portion of a semiconductor substrate.

  For example, Japanese Patent Application Laid-Open No. 2002-299463 (Patent Document 1) and Japanese Patent Application Laid-Open No. 8-255909 (Patent Document 1) have disclosed lateral MOS transistors in which stripe-shaped source regions and drain regions are alternately arranged on the surface layer portion of a semiconductor substrate. Document 2).

  FIG. 5 is an example of a conventional lateral MOS transistor in which stripe-like source regions and drain regions are alternately arranged on the surface layer portion of a semiconductor substrate. FIG. 5 is a schematic top view showing an arrangement relationship of main parts of the lateral MOS transistor 90. FIG. FIG. 6 is a schematic cross-sectional view taken along the two-dot chain line AA in FIG. In FIG. 5, each region divided in a grid pattern by orthogonal one-dot chain lines is a virtual unit cell used for simulation or the like in the design of the horizontal MOS transistor 90. Accordingly, FIG. 6 corresponds to a cross section of the unit cell.

  The lateral MOS transistor 90 shown in FIG. 5 is an N-channel lateral MOS transistor, and is a lateral MOS transistor in which striped source regions S and drain regions D are alternately arranged on the surface layer portion of the semiconductor substrate 10. As shown in FIG. 6, the semiconductor substrate 10 is an SOI (Silicon On Insulator) substrate having a buried oxide film 3, and below the buried oxide film 3 is a support substrate 2 of P conductivity type (p). The N conductivity type (n−) layer 1 a in the SOI layer 1 on the film 3 is used as a formation layer of the lateral MOS transistor 90.

As shown in FIG. 5, striped source lines Ls and drain lines Ld indicated by thick solid lines are formed on the source region S and the drain region D, respectively. The source line Ls and the drain line Ld are connected to the source region S and the drain region D by a large number of contacts Cs and Cd indicated by thick broken lines, respectively. The contacts Cs and Cd have the same contact area and are arranged on the source region S and the drain region D at the same pitch cp as the unit cells. Further, the source wirings Ls and the drain wirings Ld are connected by connecting portions Js and Jd, respectively. Usually, the drain pad Pd is connected to the power supply side and the source pad Ps is connected to the ground side. 5 and 6, reference numeral 4 denotes a LOCOS (Local Oxidation of Silicon) oxide film, and reference numeral G denotes a gate electrode formed on a gate insulating film (not shown).
JP 2002-299463 A JP-A-8-255909

  The lateral MOS transistor 90 shown in FIG. 5 has a configuration in which a large number of LDMOS unit cells are connected in parallel. In particular, in a power MOS transistor for power, normally, several hundred to several thousand LDMOS unit cells are connected in parallel, and these are operated simultaneously.

  In an integrated circuit such as the lateral MOS transistor 90 of FIG. 5, a protection element such as a diode is usually inserted on the power supply side in order to prevent a circuit failure due to a surge such as ESD (Electro Static Discharge). However, in order to reduce the cost, it is desirable to improve the resistance of the lateral MOS transistor 90 itself against ESD or the like and eliminate the protection element such as a diode. Further, even when a protective element is used, it is difficult to completely absorb a surge such as ESD by the protective element. In this case as well, the resistance of the lateral MOS transistor 90 itself to ESD or the like is improved as much as possible. Is preferred.

  Therefore, the present invention is a lateral MOS transistor in which striped source regions and drain regions are alternately arranged on the surface layer portion of a semiconductor substrate, and has high resistance to surges such as ESD without increasing the manufacturing cost. It is an object of the present invention to provide a lateral MOS transistor having

The lateral MOS transistor according to claim 1 is a lateral MOS transistor in which striped source regions and drain regions are alternately arranged on a surface layer portion of a semiconductor substrate, and is formed on each region of the source region and the drain region. Striped source wirings and drain wirings are formed, respectively, and the source wirings and the drain wirings are respectively connected to each of the source region and the drain region by three or more contacts, The source lines and the drain lines are connected to each other, and in the drain region, the first drain contact, the first drain contact, in the order closer to the connecting part that connects the drain lines among the three or more contacts. As the second drain contact and the third drain contact, the first drain contact The contact resistance of the transfected R1, contact resistance of the second drain contact R2, when the contact resistance of the third drain contact was R3, R1>R2> Ri Na is set to R3, the first drain contact, The second drain contact and the third drain contact have a rectangular shape, and the lengths of one side of the rectangular first drain contact, the second drain contact, and the third drain contact are set to be equal, and the rectangular shape The first drain contact, the second drain contact, and the third drain contact are equal so that the other sides of the first drain contact, the second drain contact, and the third drain contact are along the stripe of the drain region. It features a Rukoto such are arranged at a pitch .

  In the lateral MOS transistor, when a surge such as ESD is applied to the drain pad on the power supply side, the surge propagates to each drain wiring through the connecting portion. The surge propagated to each drain wiring propagates to a virtual LDMOS unit cell divided between adjacent contacts in the order of the first drain contact, the second drain contact, and the third drain contact close to the connecting portion.

  Here, when the contact resistance R1 of the first drain contact, the contact resistance R2 of the second drain contact, and the contact resistance R3 of the third drain contact are all equal R1 = R2 = R3, the connecting portion where the surge first propagates Surge current flows in a concentrated manner into the LDMOS unit cell defined by the first drain contact closest to. For this reason, the LDMOS unit cell defined by the first drain contact is more easily destroyed than the other unit cells, and the lateral MOS transistor as a whole is less resistant to surge.

  On the other hand, in the lateral MOS transistor, the contact resistance R1 of the first drain contact, the contact resistance R2 of the second drain contact, and the contact resistance R3 of the third drain contact are set to R1> R2> R3. Therefore, a surge current that flows into the LDMOS unit cell defined by each contact by contact resistances R1, R2, and R3 with respect to a surge that propagates in the order of the first drain contact, the second drain contact, and the third drain contact. Can be constrained to be reduced in reverse to the propagation order. As a result, the surge current flowing into the LDMOS unit cell defined by each contact can be balanced, and the overall resistance to surge of the lateral MOS transistor can be enhanced.

In the lateral MOS transistor, the first drain contact close to the connecting portion, even when any number of three or more contacts are formed for each of the source region and the drain region, By simply setting the contact resistances R1, R2, and R3 of the second drain contact and the third drain contact such that R1>R2> R3, it is possible to increase the overall resistance to surge of the lateral MOS transistor. The contact resistances R1, R2, and R3 in the lateral MOS transistor can be set only by appropriately setting the contact area. Therefore, this does not increase the manufacturing cost.
Further, in the lateral MOS transistor, the first drain contact, the second drain contact, and the third drain contact are rectangular, and one of the rectangular first drain contact, second drain contact, and third drain contact is formed. And the other side of the rectangular first drain contact, the second drain contact, and the third drain contact is along the stripe of the drain region. The contacts, the second drain contact, and the third drain contact are arranged at an equal pitch.
Thus, the LDMOS unit cell defined by each contact flows into the LDMOS unit cell without changing the characteristics of the LDMOS unit cell defined by the first drain contact, the second drain contact, and the third drain contact as the lateral MOS transistor. By balancing the surge current, the lateral MOS transistor as a whole can be improved in resistance to the surge.

  As described above, the lateral MOS transistor is a lateral MOS transistor in which striped source regions and drain regions are alternately arranged on a surface layer portion of a semiconductor substrate, and does not increase the manufacturing cost. Thus, a lateral MOS transistor having high resistance to the surge can be obtained.

  According to the simulation result, in the lateral MOS transistor, it is preferable that the contact resistances R1, R2, and R3 are set to R1-R2 = R2-R3 as described in claim 2. As a result, the surge current flowing into the LDMOS unit cell defined by the first drain contact, the second drain contact and the third drain contact can be substantially balanced, and the lateral MOS transistor as a whole can withstand the surge. Can be increased.

  Further, as described in claim 3, it is more preferable that the contact resistances R1, R2, and R3 are set such that R1-R2> R2-R3. According to this, the surge current flowing into the LDMOS unit cell defined by each contact of the first drain contact, the second drain contact, and the third drain contact can be balanced more precisely, and as a whole of the lateral MOS transistor The resistance to surges can be further increased.

In the lateral MOS transistor, as described in claim 4 , the semiconductor substrate may be an SOI substrate having a buried oxide film.

  Compared with a normal bulk single crystal substrate, an SOI substrate having a buried oxide film cannot release a surge such as ESD applied to a drain pad on the power supply side from the support substrate side under the buried oxide film to the ground. For this reason, the lateral MOS transistor formed on the SOI substrate can increase the speed, but it is disadvantageous against surges such as ESD. As described above, even if the SOI substrate is disadvantageous against the surge, the horizontal MOS transistor has a surge current flowing into the LDMOS unit cell defined by the first drain contact, the second drain contact, and the third drain contact. By balancing the above, it is possible to increase the resistance to surge as a whole of the lateral MOS transistor.

According to a fifth aspect of the present invention , the lateral MOS transistor is suitable as a lateral MOS transistor for power.

  In a horizontal MOS transistor for power, normally, hundreds to thousands of LDMOS unit cells defined by each contact are connected in parallel, and these are operated simultaneously. Even in such a lateral MOS transistor for power, as described above, the contact resistances R1, R2, and R3 of the first drain contact, the second drain contact, and the third drain contact close to the connecting portion are set as appropriate. Thus, it is possible to increase the resistance to surge as a whole of the lateral MOS transistor.

According to a sixth aspect of the present invention , the lateral MOS transistor is suitable as an in-vehicle lateral MOS transistor that is required to have high resistance against surges such as ESD.

  The best mode for carrying out the present invention will be described below with reference to the drawings.

  FIG. 1 is an example of a lateral MOS transistor (LDMOS, Lateral Diffused Metal Oxide Semiconductor) according to the present invention, and is a schematic top view showing an arrangement relationship of main parts of a lateral MOS transistor 100. In the lateral MOS transistor 100 shown in FIG. 1, the same reference numerals are given to the same parts as those of the lateral MOS transistor 100 shown in FIG. Further, a schematic cross-sectional view taken along a two-dot chain line BB in FIG. 1 is the same as FIG. 6, and FIG. 6 is referred to in the following description. Also in FIG. 1, each region divided in a grid pattern by an alternate long and short dash line is a virtual unit cell used for simulation or the like in designing the lateral MOS transistor 100.

  A lateral MOS transistor 100 shown in FIG. 1 is an N-channel lateral MOS transistor, similar to the lateral MOS transistor 90 shown in FIG. 5, and the striped source region S and drain region D are formed on the surface layer portion of the semiconductor substrate 10. The lateral MOS transistors are alternately arranged. As shown in FIG. 6, the semiconductor substrate 10 is an SOI (Silicon On Insulator) substrate having a buried oxide film 3, and below the buried oxide film 3 is a support substrate 2 of P conductivity type (p). The N conductivity type (n−) layer 1 a in the SOI layer 1 on the film 3 is used as a formation layer of the lateral MOS transistor 100.

  In the lateral MOS transistor 100 of FIG. 1, as in the lateral MOS transistor 90 of FIG. 5, striped source wirings Ls and drain wirings Ld indicated by thick solid lines are respectively formed on the source region S and the drain region D. Is formed. The source line Ls and the drain line Ld are connected to the source region S and the drain region D by a large number of contacts Cs and Cd indicated by thick broken lines, respectively. Further, the source wirings Ls and the drain wirings Ld are connected by connecting portions Js and Jd, respectively. Usually, the drain pad Pd is connected to the power supply side and the source pad Ps is connected to the ground side.

  On the other hand, in the lateral MOS transistor 90 shown in FIG. 5, the contacts Cs and Cd have the same contact area and are arranged on the source region S and the drain region D at the same pitch cp as the unit cells. In contrast, in the lateral MOS transistor 100 shown in FIG. 1, in the drain region D, the first drain contact Cd1, the second drain contact Cd2, and the third drain contact in the order close to the connecting portion Jd that connects the drain wirings Ld. Each contact area of Cd3 is set smaller as it is closer to the connecting portion Jd. In other words, since the contact area and the contact resistance are inversely proportional, in the lateral MOS transistor 100, the contact resistance of the first drain contact Cd1 is R1, the contact resistance of the second drain contact is R2, and the contact resistance of the third drain contact Cd3 is R3. In this case, R1> R2> R3 is set.

  In the lateral MOS transistors 100 and 90 of FIGS. 1 and 5, when a surge such as ESD is applied to the drain pad Pd on the power supply side, the surge propagates to each drain wiring Ld through the connecting portion Jd. The surge propagated to each drain line Ld is a virtual line that is delimited by a one-dot chain line in the drawing between adjacent contacts in the order of the first drain contact Cd1, the second drain contact Cd2, and the third drain contact Cd3 close to the connecting portion Jd. Propagated to typical LDMOS unit cells U1, U2 and U3.

  Here, when the contact resistances of the contacts Cd connected to the drain region D are all equal as in the lateral MOS transistor 90 shown in FIG. 5, the first drain closest to the connecting portion Jd through which the surge first propagates. A surge current concentrates in the LDMOS unit cell defined by the contact. For this reason, the LDMOS unit cell defined by the first drain contact is more likely to be destroyed than the other unit cells, and the lateral MOS transistor 90 as a whole is less resistant to surge.

  On the other hand, in the lateral MOS transistor 100 of FIG. 1, the contact resistance R1 of the first drain contact Cd1, the contact resistance R2 of the second drain contact Cd2, and the contact resistance R3 of the third drain contact Cd3 are set to R1> R2> R3. Has been. Accordingly, the surges that propagate in the order of the first drain contact Cd1, the second drain contact Cd2, and the third drain contact Cd3 are defined by the contacts Cd1, Cd2, and Cd3 by the contact resistances R1, R2, and R3. The surge current flowing into the LDMOS unit cells U1, U2, and U3 can be limited so as to be reduced in the reverse order of propagation. As a result, the surge current flowing into the LDMOS unit cells U1, U2, and U3 defined by the contacts Cd1, Cd2, and Cd3 can be balanced, and the overall resistance of the lateral MOS transistor 100 to the surge can be enhanced.

  In the lateral MOS transistor 100 of FIG. 1, any number of contacts Cs and Cd of three or more are formed for each of the regions S and D of the source region S and the drain region D. However, the entire lateral MOS transistor can be obtained simply by setting the contact resistances R1, R2 and R3 of the first drain contact Cd1, the second drain contact Cd2 and the third drain contact Cd3 close to the connecting portion Jd to R1> R2> R3. The resistance to surge can be increased. Further, the contact resistances R1, R2, and R3 in the lateral MOS transistor 100 can be set only by appropriately setting the contact area as shown in FIG. Therefore, this does not increase the manufacturing cost.

  Next, simulation results regarding surge resistance of the lateral MOS transistor 100 of FIG. 1 will be described.

  FIG. 2 is a model diagram of simulation. FIG. 2A is a diagram showing components of a lateral MOS transistor 100m that models the lateral MOS transistor 100 of FIG. 1, and FIG. 2B is a diagram showing components of a surge generation circuit. In the lateral MOS transistor 100m that is the simulation model of FIG. 2A, the same reference numerals are given to the same portions as those of the lateral MOS transistor 100 of FIG.

A lateral MOS transistor 100m shown in FIG. 2A is an N-channel LDMOS with a withstand voltage of 80 V, and has a striped source region S and drain region D that are uniform in the longitudinal direction, and each contact connected to the drain region D. It is composed of three unit cells defined by Cd1, Cd2 and Cd3. As for the size of the unit cell, the width in the SD direction is 11.5 μm and the length in the longitudinal direction is 10 μm. In the simulation, the contact resistances R1, R2, and R3 of the contacts Cd1, Cd2, and Cd3 are used as parameters, and the resistance of the drain wiring Ld is set to a sufficiently small value compared to the contact resistances R1, R2, and R3. Further, charging / discharging is performed by the parallel CR shown in FIG. 2B, and a surge of 10 kV per 1 mm ^{2 of} the chip area is applied to the drain pad Pd.

  3 and 4 are examples of the simulation results.

  FIG. 3A is a model corresponding to the lateral MOS transistor 90 of FIG. 5, and the contact resistances R1, R2, and R3 of the first drain contact Cd1, the second drain contact Cd2, and the third drain contact Cd3 are all equal. In this case, R1 = R2 = R3 = 0.02Ω. FIG. 3B is a model corresponding to the lateral MOS transistor 100 of FIG. 1, and the contact resistances R1, R2, and R3 of the first drain contact Cd1, the second drain contact Cd2, and the third drain contact Cd3 are respectively R1. = 0.03Ω, R2 = 0.02Ω, and R3 = 0.01Ω. In other words, the contact resistances R1, R2, and R3 in FIG. 3B are set to R1-R2 = R2-R3 = 0.01Ω.

  According to the simulation result of FIG. 3, when all the contact resistances R1, R2, and R3 shown in FIG. 3A are set equal, the surge current that flows into the LDMOS unit cell U1 defined by the first drain contact Cd1. Id1 is the maximum, and the peak value indicated by the alternate long and short dash line in the figure is 5.7 mA. Further, the surge current Id3 flowing into the LDMOS unit cell U3 defined by the third drain contact Cd3 is minimized, and the peak value indicated by a two-dot chain line in the drawing is 3.0 mA. Therefore, the difference between the two is 2.7 mA.

  On the other hand, when the contact resistances R1, R2, and R3 shown in FIG. 3B are set to R1-R2 = R2-R3 = 0.01Ω, the first drain as in FIG. The surge current Id1 flowing into the LDMOS unit cell U1 defined by the contact Cd1 is maximized, but the peak value is reduced to 4.8 mA. The surge current Id2 flowing into the LDMOS unit cell U2 defined by the second drain contact Cd2 and the surge current Id3 flowing into the LDMOS unit cell U3 defined by the third drain contact Cd3 are substantially equal, and the minimum peak value is 3. 9 mA. Therefore, the difference between the two is 0.9 mA.

  FIGS. 4A and 4B are also models corresponding to the lateral MOS transistor 100 of FIG. 1, and FIG. 4A shows that the contact resistances R1, R2, and R3 are R1 = 0.035Ω and R2 = This is the case when 0.02Ω and R3 = 0.005Ω. Each contact resistance R1, R2, R3 in FIG. 4A is R1-R2 = R2-R3 = 0.015Ω, which is compared with R1-R2 = R2-R3 = 0.01Ω in FIG. The difference between adjacent contact resistances is set large. FIG. 4B shows the case where the contact resistances R1, R2, and R3 are R1 = 0.035Ω, R2 = 0.02Ω, and R3 = 0.01Ω, respectively. In other words, the contact resistances R1, R2, and R3 in FIG. 4B are set such that R1-R2 = 0.015Ω> R2-R3 = 0.01Ω.

  A surge that flows into the LDMOS unit cell U1 defined by the first drain contact Cd1 even when the contact resistances R1, R2, and R3 shown in FIG. 4A are set to R1-R2 = R2-R3 = 0.015Ω. The current Id1 becomes maximum, and the peak value decreases to 4.6 mA. Similarly to the case of FIG. 3B, the surge current Id2 flowing into the LDMOS unit cell U2 defined by the second drain contact Cd2 and the surge current Id3 flowing into the LDMOS unit cell U3 defined by the third drain contact Cd3. Are approximately equal and the minimum peak value increases to 4.1 mA. Therefore, compared with the case of FIG.3 (b), both difference becomes still smaller and becomes 0.5 mA.

  The LDMOS unit cell defined by the first drain contact Cd1 even when the contact resistances R1, R2 and R3 shown in FIG. 4B are set such that R1-R2 = 0.015Ω> R2-R3 = 0.01Ω. The surge current Id1 flowing into U1 becomes maximum, and the peak value further decreases to 4.4 mA. Further, the surge current Id2 flowing into the LDMOS unit cell U2 defined by the second drain contact Cd2 and the surge current Id3 flowing into the LDMOS unit cell U3 defined by the third drain contact Cd3 are more equal, and the minimum peak value is 4. It goes up to 2mA. Therefore, compared with the case of FIG. 4A, the difference between the two is further reduced to 0.2 mA.

  3 and 4 are summarized as follows. In the lateral MOS transistor 100 of FIG. 1, as shown in FIGS. 3B and 4A, each contact resistance R1, R2, R3 is R1-R2 = R2-R3 is preferable. As a result, the surge current flowing into the LDMOS unit cells U1, U2, U3 defined by the first drain contact Cd1, the second drain contact Cd2 and the third drain contact Cd3 can be substantially balanced, and the lateral MOS The resistance to surge as a whole of the transistor 100 can be increased.

  Further, as shown in FIG. 4B, it is more preferable that the contact resistances R1, R2, and R3 are set such that R1-R2> R2-R3. According to this, the surge current flowing into the LDMOS unit cells U1, U2, U3 defined by the respective contacts of the first drain contact Cd1, the second drain contact Cd2, and the third drain contact Cd3 can be balanced more precisely. In addition, the overall resistance of the horizontal MOS transistor 100 to surge can be further increased.

  As described above, the lateral MOS transistor 100 of FIG. 1 is a lateral MOS transistor in which the stripe-shaped source regions S and drain regions D are alternately arranged on the surface layer portion of the semiconductor substrate 10, and the manufacturing cost increases. Therefore, a lateral MOS transistor having high resistance against surges such as ESD can be obtained.

  In the lateral MOS transistor 100 of FIG. 1, the first drain contact Cd1, the second drain contact Cd2, and the third drain contact Cd3 are rectangular, and the rectangular first drain contact Cd1, second drain contact Cd2, and second drain contact Cd2 The length (width in the SD direction) of one side of the 3 drain contact Cd3 was set equal. In addition, the other side (longitudinal direction) of the rectangular first drain contact Cd1, second drain contact Cd2, and third drain contact Cd3 is along the stripe of the drain region D, and the first drain contact Cd1, The two drain contacts Cd2 and the third drain contact Cd3 are arranged with an equal pitch cp.

According to this, without changing the characteristics of the LDMOS unit cells U1, U2, U3 defined by the first drain contact Cd1, the second drain contact Cd2 and the third drain contact Cd3 as the lateral MOS transistors, the respective characteristics are changed. The surge current flowing into the LDMOS unit cells U1, U2, and U3 defined by the contacts Cd1, Cd2, and Cd3 can be balanced to increase the overall resistance to surge of the lateral MOS transistor. However, not limited to this, first drain contact Cd1, second drain contact Cd2 and third drain contact Cd3 may be, for example, an elliptical shape. Further, the first drain contact Cd1, the second drain contact Cd2, and the third drain contact Cd3 may be arranged at different pitches.

  In the lateral MOS transistor 100 of FIG. 1, the SOI substrate 10 having the buried oxide film 3 is used. The semiconductor substrate on which the lateral MOS transistor 100 is formed is not limited to the SOI substrate 10 having the buried oxide film 3 but may be a normal bulk single crystal substrate.

  The SOI substrate 10 having the buried oxide film 3 causes a surge such as ESD applied to the drain pad Pd on the power source side from the support substrate 2 side under the buried oxide film 3 to the ground as compared with a normal bulk single crystal substrate. I can't miss it. For this reason, the lateral MOS transistor 100 formed on the SOI substrate 10 can be increased in speed, but is disadvantageous for surges such as ESD. As described above, even if the SOI substrate 10 is disadvantageous against surge, the lateral MOS transistor 100 shown in FIG. 1 is defined by the first drain contact Cd1, the second drain contact Cd2, and the third drain contact Cd3. By balancing the surge current flowing into the LDMOS unit cells U1, U2, U3, the overall resistance of the lateral MOS transistor 100 to surge can be enhanced.

  The lateral MOS transistor 100 shown in FIG. 1 is suitable as a power lateral MOS transistor.

  In a horizontal MOS transistor for power, normally, hundreds to thousands of LDMOS unit cells defined by each contact are connected in parallel, and these are operated simultaneously. Even in such a horizontal MOS transistor for power, as described above, the contact resistances R1, R2 of the first drain contact Cd1, the second drain contact Cd2, and the third drain contact Cd3 close to the connecting portion Jd in FIG. , R3 can be set appropriately, and the resistance to surge as a whole of the lateral MOS transistor 100 can be enhanced.

  Further, the lateral MOS transistor 100 shown in FIG. 1 is suitable as an in-vehicle lateral MOS transistor that is required to have high resistance against surges such as ESD.

FIG. 2 is a schematic top view showing an arrangement relationship of main parts of a lateral MOS transistor 100 as an example of the lateral MOS transistor of the present invention. In the simulation model diagram, (a) is a diagram showing components of the lateral MOS transistor 100m, and (b) is a diagram showing components of the surge generating circuit. In an example of the simulation result, (a) shows a case where each contact resistance R1, R2, R3 is all equal R1 = R2 = R3 = 0.02Ω, and (b) shows that the contact resistances R1, R2, R3 are , R1 = 0.03Ω, R2 = 0.02Ω, and R3 = 0.01Ω, respectively. An example of simulation results is shown in FIG. 5A, where the contact resistances R1, R2, and R3 are R1 = 0.035Ω, R2 = 0.02Ω, and R3 = 0.005Ω, respectively. (B) is a case where the contact resistances R1, R2, and R3 are R1 = 0.035Ω, R2 = 0.02Ω, and R3 = 0.01Ω, respectively. FIG. 10 is a schematic top view showing an arrangement relationship of main parts of a horizontal MOS transistor 90 as an example of a conventional horizontal MOS transistor. It is typical sectional drawing in the dashed-two dotted line AA in FIG.

Explanation of symbols

90, 100 Lateral MOS transistor S Source region D Drain region G Gate electrode Ls Source wiring Ld Drain wiring Js, Jd Connection Ps Source pad Pd Drain pad Cs, Cd contact Cd1 First drain contact Cd2 Second drain contact Cd3 Third drain Contact R1, R2, R3 Contact resistance U1, U2, U3 LDMOS unit cell cp pitch 10 Semiconductor substrate (SOI substrate)
DESCRIPTION OF SYMBOLS 1 SOI layer 1a N conductivity type (n-) layer 2 Support substrate 3 Embedded oxide film 4 LOCOS oxide film

Claims (6)

A horizontal MOS transistor in which stripe-shaped source regions and drain regions are alternately arranged on a surface layer portion of a semiconductor substrate,
Striped source wirings and drain wirings are formed on the source region and the drain region, respectively.
The source wiring and the drain wiring are connected to each of the source region and the drain region by three or more contacts, respectively, and the source wiring and the drain wiring are connected to each other. And
In the drain region,
Among the three or more contacts, a first drain contact, a second drain contact, and a third drain contact are arranged in order from the connection part that connects the drain wirings, and the contact resistance of the first drain contact is R1, When the contact resistance of the 2 drain contact is R2, and the contact resistance of the third drain contact is R3,
R1>R2> R3
Ri name is set to,
The first drain contact, the second drain contact, and the third drain contact are rectangular;
The lengths of one side of the rectangular first drain contact, the second drain contact, and the third drain contact are set equal,
The other side of the rectangular first drain contact, second drain contact, and third drain contact is along the stripe of the drain region,
It said first drain contact, second drain contact and the third drain contacts, lateral MOS transistor, wherein Rukoto such are arranged at equal pitches. The contact resistances R1, R2, R3 are
R1-R2 = R2-R3
2. The lateral MOS transistor according to claim 1, wherein the lateral MOS transistor is set as follows. The contact resistances R1, R2, R3 are
R1-R2> R2-R3
2. The lateral MOS transistor according to claim 1, wherein the lateral MOS transistor is set as follows. 4. The lateral MOS transistor according to claim 1 , wherein the semiconductor substrate is an SOI substrate having a buried oxide film . 5. 5. The lateral MOS transistor according to claim 1 , wherein the lateral MOS transistor is a power lateral MOS transistor. 6. The lateral MOS transistor according to claim 1 , wherein the lateral MOS transistor is an in-vehicle lateral MOS transistor.

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