CN102751410A - LED (Light Emitting Diode) chip provided with stepped current blocking structure and fabricating method thereof - Google Patents
LED (Light Emitting Diode) chip provided with stepped current blocking structure and fabricating method thereof Download PDFInfo
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- CN102751410A CN102751410A CN2012102434383A CN201210243438A CN102751410A CN 102751410 A CN102751410 A CN 102751410A CN 2012102434383 A CN2012102434383 A CN 2012102434383A CN 201210243438 A CN201210243438 A CN 201210243438A CN 102751410 A CN102751410 A CN 102751410A
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Abstract
The invention provides an LED (Light Emitting Diode) chip provided with a stepped current blocking structure and a fabricating method thereof. The fabricating method comprises the steps of: providing at least one LED epitaxial wafer comprising a substrate and a light emitting epitaxial structure on the LED epitaxial wafer; fabricating the stepped current blocking structure on the surface of the LED epitaxial wafer vertical to a region of a first electrode correspondingly prefabricated; and fabricating transparent conductive layers on the surfaces of the LED epitaxial wafer and the stepped current blocking structure, and then fabricating a first electrode, a second electrode and a protective layer correspondingly. According to the LED chip provided with a stepped current blocking structure and the fabricating method of the LED chip provided with the stepped current blocking structure provided by the invention, the gradient at the edge of the stepped current blocking structure is slowed so that the contact area of the transparent conductive layer and the stepped current blocking structure is increased, the situation that the transparent conductive layer (ITO) on the side wall (at the step) at the edge of the current blocking structure becomes thinner and even breaks can be avoided, the step covering capacity of the transparent conductive layer is improved, the current spreading capacity of the transparent conductive layer is further improved, the electro-optical conversion efficiency of the LED chip is increased, and the brightness of the LED chip is enhanced.
Description
Technical field
The present invention relates to a kind of led chip and preparation method thereof, particularly relate to a kind of led chip and preparation method thereof with staged current blocking structures.
Background technology
LED (Light Emitting Diode) chip is also referred to as the LED luminescence chip, is the core component of LED lamp, is a kind of solid-state semiconductor device, and it can directly be converted into luminous energy to electric energy.Led chip mainly is made up of two parts, and a part is a P type semiconductor, and the hole accounts for and is majority carrier, and another part is a N type semiconductor, and electronics is a majority carrier, when two kinds of semiconductors couple together, forms the P-N knot.When electric current acts on this chip through lead; Electronics will be pushed to the P district, and (like quantum well region) electronics will send energy with the form of photon then with hole-recombination in the P-N land; The luminous principle of led chip that Here it is; Wherein, the color of sending light depends on optical wavelength, and determine by the material that forms the P-N knot.LED adds " mercury " in process of production, does not also need inflation, does not need glass shell, good impact resistance, and shock resistance is good, is difficult for fragmentation, is convenient to transportation, and very environmental protection is called as " green energy resource ".
Initial LED is as the indication light source of instrument and meter, and various afterwards photochromic LED have obtained extensive use in traffic lights and large tracts of land display screen, produced good economic benefits and social benefit.Automobile signal light also is the key areas that led light source is used.Progress along with semiconductor science and technology; Led chip has now possessed the output of high brightness; Add that led chip has that power saving, volume are little, low voltage drive, life-span grow advantages such as (generally between 50,000 to 100,000 hours) very much; Therefore, led chip has been widely used in fields such as display and illumination.
Because led chip is a kind of electroluminescent device, therefore need make electrode on the luminescent material surface, come the driving LED chip light emitting from the electrode injection current.The area of electrode is big more, and it is easy more that electric current injects, and CURRENT DISTRIBUTION can be accomplished more even; Operating voltage also can reduce, and helps improving electro-optical efficiency, but because electrode all is a light absorbent; The more big shading face of its area is also big more, thereby causes the decline of electro-optical efficiency.In order to solve this contradiction; Industry has been proposed in LED and goes up the method for making current barrier layer and transparency conducting layer; Promptly the position of certain depth makes insulating material and stops the electric current in this piece zone to pass through under apart from electrode, and at current barrier layer and luminescent material surface attachment transparency conducting layer, so just can not be luminous under electrode; So electrode does not in fact just have or seldom shading; Simultaneously, transparency conducting layer makes electric current be scattered in LED luminescent material surface more uniformly, thereby improves the electro-optical efficiency of LED.
But; Because the gradient coating performance as the ITO (indium tin oxide semiconductor) of transparency conducting layer is not good; As shown in Figure 8; Tend to cause transparency conducting layer 3 ' (ITO film) the thickness attenuation that covers current barrier layer 2 ' edge side-walls (ladder place), even the phenomenon of disconnection occurs, thereby cause impedance increase, the increase of forward operating voltage, the electric current diffusivity of transparency conducting layer 3 ' (ITO film) to reduce; The electro-optical efficiency of led chip is reduced, cause the brightness of led chip to reduce.
Summary of the invention
The shortcoming of prior art in view of the above; The object of the present invention is to provide a kind of led chip and preparation method thereof, be used for solving the problem that the electro-optical efficiency of the not good led chip that causes of prior art transparency conducting layer gradient coating performance reduces with staged current blocking structures.
For realizing above-mentioned purpose and other relevant purposes, the present invention provides a kind of manufacture method with led chip of staged current blocking structures, and said manufacture method comprises at least:
1) a LED epitaxial wafer is provided; Said LED epitaxial wafer comprises substrate at least and is positioned at the epitaxial light emission structure of said substrate surface; Wherein, said epitaxial light emission structure comprises first conductive type epitaxial layer, active layer from top to bottom successively, reaches second conductive type epitaxial layer;
2) make the staged current blocking structures in the zone that is positioned at said epitaxial light emission structure surface, vertical corresponding prefabricated work first electrode;
3) make transparency conducting layer at said epitaxial light emission structure and staged current blocking structures surface; Then make second electrode that is connected in said second conductive type epitaxial layer, and on said layer at transparent layer, make first electrode with the vertical corresponding zone of said staged current blocking structures;
4) form protective layer at said transparency conducting layer and epitaxial light emission structure surface, then grind, draw and split the led chip making that has the staged current blocking structures with completion.
Alternatively; Said step 2) in before making the staged current blocking structures; Earlier form a current barrier layer in its corresponding zone; Said current barrier layer is single layer structure or laminated construction, and said single layer structure wherein or the material of each layer in the said laminated construction are any one in silica, silicon nitride and the silicon oxynitride.
Alternatively, said current barrier layer is a sandwich construction, and said sandwich construction from top to bottom the etch rate of layers of material successively reduce.
Alternatively; Said current barrier layer is alternately adopted dry etching and oxygen plasma ashing; Said current barrier layer is made as said staged current blocking structures, wherein, said dry etching comprises reactive ion etching or inductively coupled plasma etching at least.
Alternatively, utilize the said current barrier layer of buffer oxide layer etching solution or hf etching, said current barrier layer is made as said staged current blocking structures.
Alternatively, said LED epitaxial wafer also comprises resilient coating or the reflector between said extension ray structure and said substrate.
The present invention also provides a kind of led chip with staged current blocking structures, and said led chip comprises at least:
The LED epitaxial wafer comprises substrate at least and is positioned at the epitaxial light emission structure of said substrate surface, and wherein, said epitaxial light emission structure comprises first conductive type epitaxial layer, active layer, and second conductive type epitaxial layer from top to bottom successively;
The staged current blocking structures is positioned at said epitaxial light emission structure surface, is positioned at the epitaxial light emission structure under it with directly vertical injection of block current, forces electric current distribution extending transversely;
Transparency conducting layer is covered in said epitaxial light emission structure and staged current blocking structures surface, by said staged current blocking structures, further makes electric current be uniformly distributed in said epitaxial light emission structure;
First electrode is positioned at said layer at transparent layer, and vertical corresponding with said staged current blocking structures;
Second electrode is connected in said second conductive type epitaxial layer;
Protective layer is positioned at said transparency conducting layer and epitaxial light emission structure surface.
Alternatively, said staged current blocking structures is single layer structure or laminated construction, and said single layer structure wherein or the material of each layer in the said laminated construction are any one in silica, silicon nitride and the silicon oxynitride.
Alternatively, the sandwich construction that successively reduces for layers of material etch rate from top to bottom of said staged current blocking structures.
Alternatively, said LED epitaxial wafer also comprises resilient coating or the reflector between said extension ray structure and said substrate.
As stated, led chip with staged current blocking structures of the present invention and preparation method thereof has following beneficial effect: compare with the conventional current barrier layer; The gradient at the staged current blocking structures edge that the present invention adopts slows down; Increased the contact area of transparency conducting layer and staged current blocking structures, avoided transparency conducting layer (ITO) side-walls (ladder place) thickness attenuation, even the phenomenon of disconnection occurred at the edge of current blocking structures; Promoted the gradient coating performance of transparency conducting layer; And then improved the electric current diffusivity of transparency conducting layer, increased the electro-optical efficiency of led chip, the brightness that has improved led chip.
Description of drawings
Fig. 1 to Fig. 6 is shown as led chip and preparation method thereof the structural representation in embodiment one that the present invention has the staged current blocking structures.
Fig. 7 is shown as led chip and preparation method thereof the structural representation in embodiment two that the present invention has the staged current blocking structures.
Fig. 8 is shown as the structural representation of transparency conducting layer ITO film side-walls thickness attenuation at the edge of current barrier layer in the prior art.
Embodiment
Below through specific instantiation execution mode of the present invention is described, those skilled in the art can understand other advantages of the present invention and effect easily by the content that this specification disclosed.The present invention can also implement or use through other different embodiment, and each item details in this specification also can be based on different viewpoints and application, carries out various modifications or change under the spirit of the present invention not deviating from.
See also Fig. 1 to Fig. 7.Need to prove; The diagram that is provided in the following specific embodiment is only explained basic conception of the present invention in a schematic way; Satisfy only show in graphic with the present invention in relevant assembly but not component count, shape and plotted when implementing according to reality; Kenel, quantity and the ratio of each assembly can be a kind of random change during its actual enforcement, and its assembly layout kenel also maybe be more complicated.
Because it is not good to the gradient coating performance of current barrier layer in the led chip as the ITO (indium tin oxide semiconductor) of transparency conducting layer; Tend to cause the ITO film thickness attenuation that covers current barrier layer edge (ladder place); Even the phenomenon of appearance disconnection; Thereby cause the electro-optical efficiency of led chip to reduce, cause the brightness of led chip to reduce.
Given this; The present invention provides a kind of led chip with staged current blocking structures and preparation method thereof, because the gradient at staged current blocking structures edge slows down, has therefore increased the contact area of transparency conducting layer and staged current blocking structures; Promoted the gradient coating performance of transparency conducting layer; And then improved the electric current diffusivity of transparency conducting layer, increased the electro-optical efficiency of led chip, the brightness that has improved led chip.
Embodiment one
To shown in Figure 4, the present invention provides a kind of manufacture method with led chip of staged current blocking structures like Fig. 1, and said manufacture method comprises at least:
As shown in Figure 1; At first execution in step 1); One LED epitaxial wafer 1 is provided; Said LED epitaxial wafer 1 comprises substrate 11 at least and is positioned at the epitaxial light emission structure 12 of said substrate surface, and wherein, said epitaxial light emission structure 12 comprises first conductive type epitaxial layer 121, active layer 122, and second conductive type epitaxial layer 123 from top to bottom successively.
It is pointed out that said substrate 11 materials comprise Al at least
2O
3A kind of arbitrarily among (sapphire), GaAs, Si, SiC, GaN, GaP, InP, ZnO and the Ge; Adopt metal organic chemical vapor deposition, molecular beam epitaxy or hydride gas-phase epitaxy on said substrate 11, to form said epitaxial light emission structure 12; Said active layer 122 is single quantum or multi-quantum pit structure, quantum-dot structure or quantum wire structure; Said first conductive type epitaxial layer 121 and second conductive type epitaxial layer 123 are the III-V group iii v compound semiconductor material, comprise Al at least
xGa
yIn
(1-x-y)N or Al
xGa
yIn
(1-x-y)P, wherein, 0≤x≤1,0≤y≤1, and 0≤x+y≤1, for example, compound semiconductor can contain GaN, AlN, AlGaN, GaInN, InN, AlGaInN, GaP, AlP, AlGaP, GaInP, InP, and AlGaInP in any one.
Need to prove that said LED epitaxial wafer 1 also comprises resilient coating or the reflector between said extension ray structure 12 and said substrate 11, for example, when substrate is Al
2O
3When (sapphire), exist epitaxially grown u-GaN layer between said extension ray structure 12 and the said substrate 11 as resilient coating; When substrate is GaAs, exist between said extension ray structure 12 and the said substrate 11 Bragg reflecting layer (Distributed Bragg Reflector, DBR); When substrate is Si, exist metal as the reflector between said extension ray structure 12 and the said substrate 11, not shown relevant resilient coating or reflector among the figure of present embodiment one.
In present embodiment one; First conduction type is the P type; Second conduction type is the N type; P type alloy such as Mg and Zn can be used as the first conduction type alloy, can be used as the second conduction type alloy such as the N type alloy of Si, Ge, Sn, Se and Te, and first conductive type epitaxial layer 121 is P type Al
xGa
yIn
(1-x-y)N, second conductive type epitaxial layer 123 is N type Al
xGa
yIn
(1-x-y)N; Substrate 11 is Al
2O
3(sapphire); Adopt reactive ion etching (RIE) or inductively coupled plasma etching (ICP) to remove part active layer 122 and part first conductive type epitaxial layer 121; To expose second conductive type epitaxial layer 123; And make 123 formation of said second conductive type epitaxial layer have the portion of topping bar and the step-like structure of the portion of getting out of a predicament or an embarrassing situation, as shown in Figure 2.Follow execution in step 2).
Shown in Fig. 3 a; In step 2) in form current barrier layers 2 being positioned at said epitaxial light emission structure 12 surfaces, said current barrier layer 2 be single layer structure or laminated construction, said single layer structure wherein or the material of each layer in the said laminated construction are for insulating and the material of printing opacity; Like in silica, silicon nitride and the silicon oxynitride any one; Preferably, in the present embodiment one, said current barrier layer 2 is the silicon oxynitride of single layer structure; Then, shown in Fig. 3 b to 3f, said current barrier layer 2 is alternately adopted dry etching and oxygen plasma ashing method (O
2Plasma Ash); Promptly adopt multistage staggered form lithographic method; Zone at vertical corresponding prefabricated work first electrode; Said current barrier layer 2 is made as the staged current blocking structures (current barrier layer) 2 that comprises the two-stage step at least, and wherein, said dry etching comprises reactive ion etching (RIE) or inductively coupled plasma etching (ICP) at least.
Need to prove; In another embodiment; Elder generation's using plasma strengthens the said current barrier layer 2 (not shown) that chemical vapour deposition technique (PECVD) forms sandwich construction; And make said sandwich construction from top to bottom the etch rate of layers of material successively reduce, have different etching selection ratio with the sandwich construction that guarantee to form, then utilize buffer oxide layer etching solution (Buffered Oxide Etch; BOE) or the said current barrier layer 2 of hf etching, be made as said staged current blocking structures 2 with current barrier layer 2 with said sandwich construction.
What need further specify is; There is the situation of same material and different materials in the layers of material of sandwich construction; Wherein, When each layer of said sandwich construction was same material, for guaranteeing that the etch rate of layers of material successively reduces from top to bottom, can form the sandwich construction that density successively increases this moment.Particularly; In one embodiment, said sandwich construction is the three-decker of same material, and its orlop is that the highest silicon oxide layer of density, intermediate layer are that next silicon oxide layer, the superiors of density are the minimum silicon oxide layer of density; Therefore; BOE or hydrofluoric acid have different etching to each layer and select ratio, and wherein finer and close layer (orlop silicon oxide layer) etching is slow more, is made as said staged current blocking structures 2 with the current barrier layer 2 with said sandwich construction.In addition, in other embodiments, said sandwich construction is the three-decker of different materials; Particularly; The superiors are that the fastest silicon oxide layer of etch rate, intermediate layer are that next silicon oxynitride layer, orlop of etch rate is the slowest silicon nitride layer of etch rate and since sandwich construction from top to bottom the etch rate of layers of material successively reduce, guaranteed that sandwich construction has different etching selection ratio; Therefore; (Buffered Oxide Etch BOE) or the said current barrier layer 2 of hf etching, is made as said staged current blocking structures 2 with the current barrier layer 2 with said sandwich construction to buffer oxide layer etching solution capable of using.The number of plies that it is pointed out that said sandwich construction is not limited to three layers, can select the number of plies of said sandwich construction according to the prefabricated step progression of making the staged current blocking structures, does not give unnecessary details one by one at this.
What need special instruction is; Said staged current blocking structures 2 edges are greater than about 0.5 ~ 3 μ m of edges of regions of its corresponding prefabricated work first electrode; And the thickness of the orlop ladder of said staged current blocking structures 2 can stop the electric current of its region to pass through greater than 20nm to guarantee staged current blocking structures 2, is positioned at the epitaxial light emission structure 12 under it with directly vertical injection of block current; Force electric current distribution extending transversely; And then guarantee prefabricated work first electrode under not luminous, first electrode of prefabricated work is not had or seldom shading, with the purpose of the electro-optical efficiency that reaches the led chip that improves prefabricated work.What need further specify is that compared to the original current barrier layer that does not form ladder 2, the gradient at the edge of the said staged current blocking structures 2 of formation slows down.
Particularly, substrate is Al in the present embodiment one
2O
3(sapphire) shown in Fig. 3 a, is being positioned at said epitaxial light emission structure 12 surface formation one current barrier layer 2; Shown in Fig. 3 b; Vertical corresponding and apply photoresist 6 greater than the location of prefabricated work first electrode; And carry out reactive ion etching (RIE) as mask with this; With vertical corresponding and greater than the zone of prefabricated work first electrode, form staged current blocking structures 2 with two-stage step, simultaneously attenuate all the other do not make the current barrier layer 2 of mask process; Then, shown in Fig. 3 c, adopt oxygen plasma ashing method (O
2Plasma Ash) removes part photoresist 6, to form the smaller photoresist 6 of area as mask; Afterwards; Shown in Fig. 3 d; Said staged current blocking structures 2 with two-stage step is carried out reactive ion etching (RIE) once more; Form the staged current blocking structures 2 with three grades of steps in zone vertical corresponding and that be a bit larger tham prefabricated work first electrode, the current barrier layer 2 of not making mask process is thinned simultaneously; Then, shown in Fig. 3 e, adopt oxygen plasma ashing method (O once more
2Plasma Ash) remove part photoresist 6, with the photoresist 6 that forms small size more as mask; Then; Shown in Fig. 3 f; Said staged current blocking structures 2 with three grades of steps is carried out reactive ion etching (RIE) again; Be etched away to expose the surface of said epitaxial light emission structure 12 until said orlop step with staged current blocking structures 2 of three grades of steps; Expose vertical correspondence simultaneously this moment and be slightly larger than the surface of the epitaxial light emission structure 12 beyond the zone of prefabricated work first electrode, go out said photoresist 6 at last, to form the staged current blocking structures 2 that has three grades of steps in the present embodiment one; Said staged current blocking structures 2 with three grades of steps is corresponding with the regions perpendicular of prefabricated work first electrode, and the former edge is slightly larger than the latter's edge.
It is to be noted; The step progression of said staged current blocking structures 2 is not limited to three grades of steps in the present embodiment one, can only form the staged current blocking structures 2 with two-stage step as required; Perhaps recycle said multistage staggered form lithographic method; Further increase the step progression of staged current blocking structures, thereby the gradient of slowing down said current barrier layer 2 is not given unnecessary details one by one at this.Need further be pointed out that; In other embodiments; When said current barrier layer 2 when having the different materials sandwich construction; At least the dry etching that comprises reactive ion etching (RIE) or inductively coupled plasma etching (ICP) has different etching selection ratio for different layers, more is prone to form said staged current blocking structures 2.Follow execution in step 3).
As shown in Figure 4; In step 3); Make transparency conducting layers 3 on said epitaxial light emission structure 12 and staged current blocking structures 2 surfaces, wherein, the postpone surface configuration of staged current blocking structures 2 of said transparency conducting layer 3; Be staged and be covered in said staged current blocking structures 2 surfaces, said transparency conducting layer comprises ITO (indium tin oxide semiconductor) at least; Then adopt sputtering method or evaporation to make transparency electrode; I.e. first electrode 41 and second electrode 42; Wherein, Said first electrode 41 is positioned at that said transparency conducting layer 3 surfaces are gone up and is vertical corresponding with said staged current blocking structures 2, and makes its edge be slightly less than about 0.5 ~ 3 μ m in edge of said staged current blocking structures 2, and said second electrode 42 is connected in said second conductive type epitaxial layer 123.Said first electrode 41 or second electrode 42 are ITO or Ni/Au.
Particularly; Do not form transparency conducting layer 3 on present embodiment one said second conductive type epitaxial layer 123 surfaces shown in Figure 4; And said second electrode 42 is directly connected in said second conductive type epitaxial layer 123 surfaces; But be not limited thereto, in another embodiment, can have transparency conducting layer 3 between described second electrode 42 and second conductive type epitaxial layer 123.
It is to be noted; Transparency conducting layer 3 (ITO) shown in Figure 4 all covers the upper surface of first conductive type epitaxial layer 121 in the described epitaxial light emission structure 12 in the present embodiment one; But be not limited thereto, in another embodiment, said transparency conducting layer 3 (ITO) can partly cover the upper surface of first conductive type epitaxial layer 121; Be completing steps 3) making the time, the upper surface portion of said first conductive type epitaxial layer 121 is not capped transparency conducting layer 3 (ITO).
Need to prove; Because the gradient at said staged current blocking structures 2 edges slows down; Increased the contact area of transparency conducting layer 3, avoided transparency conducting layer 3 (ITO) side-walls (ladder place) thickness attenuation, even the phenomenon of disconnection occurred at the edge of current blocking structures 2 with staged current blocking structures 2; Promote the gradient coating performance of transparency conducting layer 3 (ITO), and then improved the electric current diffusivity of transparency conducting layer 3.Follow execution in step 4).
In step 4), the using plasma chemical gaseous phase depositing process forms protective layer 5 at said transparency conducting layer and epitaxial light emission structure surface; Then grind, draw and split the led chip making that has the staged current blocking structures with completion; Wherein, said protective layer 5 is silica, silicon nitride or silicon oxynitride, and aqueous vapor and pollutant are reduced the influence of led chip; For the led chip of GaN base, the problem of PN junction short circuit in the time of can also reducing packaging and routing (PN short).Particularly, in present embodiment one, said protective layer 5 is covered in the surface of said epitaxial light emission structure 12 and transparency conducting layer 3 as shown in Figure 5, wherein, because substrate 11 is Al
2O
3(sapphire), the surface of said epitaxial light emission structure 12 comprise the side of first conductive type epitaxial layer 121, the side of active layer 122, the portion of the topping bar side that reaches second conductive type epitaxial layer 123 and the surface of the portion of getting out of a predicament or an embarrassing situation.
Need to prove; In another embodiment; The surface of said epitaxial light emission structure 12 also comprises not the upper surface of part first conductive type epitaxial layer 121 that is covered by said transparency conducting layer 3 (ITO), so the upper surface of this part that is not capped first conductive type epitaxial layer 121 also is formed with protective layer 5 (not shown).
What need further specify is that as shown in Figure 6, in another embodiment, said protective layer 5 also is present in the sidewall or the part surface of first electrode 41 and second electrode 42, promptly forms window type protective layer 5 at said first electrode 41 and second electrode, 42 surfaces.
It is pointed out that the electric current diffusivity owing to transparency conducting layer 3 in the step 3) improves, and then increased the electro-optical efficiency of led chip, improved the brightness of led chip.
Compare with the conventional current barrier layer, have the manufacture method of the led chip of staged current blocking structures in the present embodiment one, adopt the staged current blocking structures of single or multiple lift structure; The gradient at its edge is slowed down; Increased the contact area of transparency conducting layer and staged current blocking structures, avoided transparency conducting layer (ITO) side-walls (ladder place) thickness attenuation, even the phenomenon of disconnection occurred at the edge of current blocking structures; Promoted the gradient coating performance of transparency conducting layer; And then improved the electric current diffusivity of transparency conducting layer, increased the electro-optical efficiency of led chip, the brightness that has improved led chip.
Embodiment two
As shown in Figure 7, the present invention also provides a kind of led chip with staged current blocking structures, and said led chip comprises at least: LED epitaxial wafer 1, staged current blocking structures 2, transparency conducting layer 3, first electrode 41, second electrode 42, protective layer 5.
Said LED epitaxial wafer 1 comprises substrate 11 at least and is positioned at the epitaxial light emission structure 12 on said substrate 11 surfaces; Wherein, said epitaxial light emission structure 12 comprises first conductive type epitaxial layer 121, active layer 122, and second conductive type epitaxial layer 123 from top to bottom successively.
Wherein, said substrate 11 materials comprise Al at least
2O
3A kind of arbitrarily among (sapphire), GaAs, Si, SiC, GaN, GaP, InP, ZnO and the Ge; Said active layer 122 is single quantum or multi-quantum pit structure, quantum-dot structure or quantum wire structure; Said first conductive type epitaxial layer 121 and second conductive type epitaxial layer 123 are the III-V group iii v compound semiconductor material, comprise Al at least
xGa
yIn
(1-x-y)N or Al
xGa
yIn
(1-x-y)P, wherein, 0≤x≤1,0≤y≤1, and 0≤x+y≤1, for example, compound semiconductor can contain GaN, AlN, AlGaN, GaInN, InN, AlGaInN, GaP, AlP, AlGaP, GaInP, InP, and AlGaInP in any one.
Need to prove that said LED epitaxial wafer 1 also comprises resilient coating or the reflector between said extension ray structure 12 and said substrate 11, for example, when substrate is Al
2O
3When (sapphire), exist the u-GaN layer as resilient coating between said extension ray structure 12 and the said substrate 11; When substrate is GaAs, exist between said extension ray structure 12 and the said substrate 11 Bragg reflecting layer (Distributed Bragg Reflector, DBR); When substrate is Si, exist metal as the reflector between said extension ray structure 12 and the said substrate 11, not shown relevant resilient coating or reflector among Fig. 7 of present embodiment two.
In present embodiment two; First conduction type is the P type; Second conduction type is the N type; P type alloy such as Mg and Zn can be used as the first conduction type alloy, can be used as the second conduction type alloy such as the N type alloy of Si, Ge, Sn, Se and Te, and first conductive type epitaxial layer 121 is P type Al
xGa
yIn
(1-x-y)P, second conductive type epitaxial layer 123 is N type Al
xGa
yIn
(1-x-y)P; Substrate 11 is GaAs.
Said staged current blocking structures 2 is positioned at said epitaxial light emission structure 12 surfaces, comprises the two-stage step at least, and is vertical corresponding with said staged current blocking structures 2.Wherein, said staged current blocking structures 2 is single layer structure or laminated construction, and said single layer structure wherein or the material of each layer in the said laminated construction are the insulation and the material of printing opacity, like in silica, silicon nitride and the silicon oxynitride any one.Further; The sandwich construction that said staged current blocking structures 2 successively reduces for layers of material etch rate from top to bottom; Wherein, there is the situation of same material and different materials in the layers of material of said sandwich construction, when each layer of said sandwich construction is same material; For guaranteeing that the etch rate of layers of material successively reduces from top to bottom, can form the sandwich construction that density successively increases this moment.Particularly; In the present embodiment two; Said sandwich construction is the three-decker of different materials; Its superiors are that the fastest silicon oxide layer of etch rate, intermediate layer are that next silicon oxynitride layer, orlop of etch rate is the slowest silicon nitride layer of etch rate, but specifically do not illustrate each layer among Fig. 7, only with said staged current blocking structures 2 whole this three-deckers of representing.The step progression that it is pointed out that said staged current blocking structures 2 is not limited to three grades of steps in the present embodiment two, can select the step progression of said staged current blocking structures 2 as required, does not give unnecessary details one by one at this.
Need to prove; Said staged current blocking structures 2 edges are greater than about 0.5 ~ 3 μ m of edges of regions of its first corresponding electrode; And the thickness of the orlop ladder of said staged current blocking structures 2 can stop the electric current of its region to pass through greater than 20nm to guarantee staged current blocking structures 2, is positioned at the epitaxial light emission structure 12 under it with directly vertical injection of block current; Force electric current distribution extending transversely; And then guarantee vertical corresponding first electrode 41 of said and said staged current blocking structures 2 under not luminous, said first electrode 41 is not had or seldom shading, to reach the purpose of the electro-optical efficiency that improves LED.What need further specify is that compared to the original current barrier layer that does not form ladder 2, the gradient at the edge of the said staged current blocking structures 2 of formation slows down.
Said transparency conducting layer 3 is covered in said epitaxial light emission structure 12 and staged current blocking structures 2 surfaces; The postpone surface configuration of staged current blocking structures 2 of said transparency conducting layer 3; Be staged and be covered in said staged current blocking structures 2 surfaces; And, further make electric current be uniformly distributed in said epitaxial light emission structure 1 by said staged current blocking structures.Said transparency conducting layer 3 comprises ITO (indium tin oxide semiconductor) at least.
Need to prove; Because the gradient at said staged current blocking structures 2 edges slows down; Increased the contact area of transparency conducting layer 3, avoided transparency conducting layer 3 (ITO) side-walls (ladder place) thickness attenuation, even the phenomenon of disconnection occurred at the edge of current blocking structures 2 with staged current blocking structures 2; Promote the gradient coating performance of transparency conducting layer 3 (ITO), and then improved the electric current diffusivity of transparency conducting layer 3.
Said first electrode 41 is for being positioned at the transparency electrode of said layer at transparent layer; Vertical corresponding with said staged current blocking structures 2; And make its edge be slightly less than about 0.5 ~ 3 μ m in edge of said staged current blocking structures 2, and can stop the electric current of its region to pass through to guarantee said staged current blocking structures 2, be positioned at the epitaxial light emission structure 12 under it with directly vertical injection of block current; Force electric current distribution extending transversely; And then guarantee said first electrode 41 under not luminous, first electrode is not had or seldom shading, to reach the purpose of the electro-optical efficiency that improves LED.Wherein, said first electrode 41 is ITO or Ni/Au.
Said second electrode 42 is connected in said second conductive type epitaxial layer 123.Wherein, said second electrode 42 is ITO or Ni/Au.In present embodiment two, said substrate 11 is GaAs, is electric conducting material, and therefore said second electrode 42 is connected in said second conductive type epitaxial layer 123 through GaAs substrate 11.
Said protective layer 5 is positioned at said transparency conducting layer 3 and epitaxial light emission structure 12 surfaces, and aqueous vapor and pollutant are reduced the influence of led chip, for the led chip of GaN base, and the problem of PN junction short circuit in the time of can also reducing packaging and routing (PN short).Wherein, said protective layer 5 is silica, silicon nitride or silicon oxynitride.
Need to prove; In another embodiment; The surface of said epitaxial light emission structure 12 also comprises not the upper surface of part first conductive type epitaxial layer 121 that is covered by said transparency conducting layer 3 (ITO), so also there is protective layer 5 in the upper surface of this part that is not capped first conductive type epitaxial layer 121.
What need further specify is that in another embodiment, said protective layer 5 also is present in the sidewall or the part surface of first electrode 41 and second electrode 42, promptly forms window type protective layer 5 (not shown) at said first electrode 41 and second electrode, 42 surfaces.
In sum; The present invention has led chip of staged current blocking structures and preparation method thereof, adopts the staged current blocking structures that the gradient at its edge is slowed down, and has increased the contact area of transparency conducting layer and staged current blocking structures; Avoided transparency conducting layer (ITO) side-walls (ladder place) thickness attenuation at the edge of current blocking structures; Even the phenomenon of appearance disconnection, promote the gradient coating performance of transparency conducting layer, and then improved the electric current diffusivity of transparency conducting layer; Increase the electro-optical efficiency of led chip, improved the brightness of led chip.So the present invention has effectively overcome various shortcoming of the prior art and the tool high industrial utilization.
The foregoing description is illustrative principle of the present invention and effect thereof only, but not is used to limit the present invention.Any be familiar with this technological personage all can be under spirit of the present invention and category, the foregoing description is modified or is changed.Therefore, have common knowledge the knowledgeable in the affiliated such as technical field, must contain by claim of the present invention not breaking away from all equivalence modifications of being accomplished under disclosed spirit and the technological thought or changing.
Claims (10)
1. the manufacture method with led chip of staged current blocking structures is characterized in that, said manufacture method comprises at least:
1) a LED epitaxial wafer is provided; Said LED epitaxial wafer comprises substrate at least and is positioned at the epitaxial light emission structure of said substrate surface; Wherein, said epitaxial light emission structure comprises first conductive type epitaxial layer, active layer from top to bottom successively, reaches second conductive type epitaxial layer;
2) make the staged current blocking structures in the zone that is positioned at said epitaxial light emission structure surface, vertical corresponding prefabricated work first electrode;
3) make transparency conducting layer at said epitaxial light emission structure and staged current blocking structures surface; Then make second electrode that is connected in said second conductive type epitaxial layer, and on said layer at transparent layer, make first electrode with the vertical corresponding zone of said staged current blocking structures;
4) form protective layer at said transparency conducting layer and epitaxial light emission structure surface, then grind, draw and split the led chip making that has the staged current blocking structures with completion.
2. the manufacture method with led chip of staged current blocking structures according to claim 1; It is characterized in that: said step 2) before making the staged current blocking structures; Earlier form a current barrier layer in its corresponding zone; Said current barrier layer is single layer structure or laminated construction, and said single layer structure wherein or the material of each layer in the said laminated construction are any one in silica, silicon nitride and the silicon oxynitride.
3. the manufacture method with led chip of staged current blocking structures according to claim 2 is characterized in that: said current barrier layer is a sandwich construction, and said sandwich construction from top to bottom the etch rate of layers of material successively reduce.
4. according to claim 2 or 3 described manufacture methods with led chip of staged current blocking structures; It is characterized in that: said current barrier layer is alternately adopted dry etching and oxygen plasma ashing; Said current barrier layer is made as said staged current blocking structures; Wherein, said dry etching comprises reactive ion etching or inductively coupled plasma etching at least.
5. the manufacture method with led chip of staged current blocking structures according to claim 3; It is characterized in that: utilize the said current barrier layer of buffer oxide layer etching solution or hf etching, said current barrier layer is made as said staged current blocking structures.
6. the manufacture method with led chip of staged current blocking structures according to claim 1 is characterized in that: said LED epitaxial wafer also comprises resilient coating or the reflector between said extension ray structure and said substrate.
7. the led chip with staged current blocking structures is characterized in that, said led chip comprises at least:
The LED epitaxial wafer comprises substrate at least and is positioned at the epitaxial light emission structure of said substrate surface, and wherein, said epitaxial light emission structure comprises first conductive type epitaxial layer, active layer, and second conductive type epitaxial layer from top to bottom successively;
The staged current blocking structures is positioned at said epitaxial light emission structure surface, is positioned at the epitaxial light emission structure under it with directly vertical injection of block current, forces electric current distribution extending transversely;
Transparency conducting layer is covered in said epitaxial light emission structure and staged current blocking structures surface, by said staged current blocking structures, further makes electric current be uniformly distributed in said epitaxial light emission structure;
First electrode is positioned at said layer at transparent layer, and vertical corresponding with said staged current blocking structures;
Second electrode is connected in said second conductive type epitaxial layer;
Protective layer is positioned at said transparency conducting layer and epitaxial light emission structure surface.
8. the led chip with staged current blocking structures according to claim 7; It is characterized in that: said staged current blocking structures is single layer structure or laminated construction, and said single layer structure wherein or the material of each layer in the said laminated construction are any one in silica, silicon nitride and the silicon oxynitride.
9. the led chip with staged current blocking structures according to claim 8 is characterized in that: the sandwich construction that said staged current blocking structures successively reduces for layers of material etch rate from top to bottom.
10. the led chip with staged current blocking structures according to claim 7 is characterized in that: said LED epitaxial wafer also comprises resilient coating or the reflector between said extension ray structure and said substrate.
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Effective date of registration: 20210304 Address after: Room 110-7, building 3, 290 Xingci 1st Road, Hangzhou Bay New District, Ningbo City, Zhejiang Province, 315336 Patentee after: Ningbo anxinmei Semiconductor Co.,Ltd. Address before: 230011 Hefei Xinzhan Industrial Park, Hefei City, Anhui Province Patentee before: HEFEI IRICO EPILIGHT TECHNOLOGY Co.,Ltd. |