CN102751282A - Strain BiCMOS (Bipolar Complementary Metal-Oxide-Semiconductor Transistor) integrated device based on crystal face selection and preparation method thereof - Google Patents

Strain BiCMOS (Bipolar Complementary Metal-Oxide-Semiconductor Transistor) integrated device based on crystal face selection and preparation method thereof Download PDF

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CN102751282A
CN102751282A CN2012102441387A CN201210244138A CN102751282A CN 102751282 A CN102751282 A CN 102751282A CN 2012102441387 A CN2012102441387 A CN 2012102441387A CN 201210244138 A CN201210244138 A CN 201210244138A CN 102751282 A CN102751282 A CN 102751282A
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CN102751282B (en
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张鹤鸣
吕懿
胡辉勇
李妤晨
舒斌
宣荣喜
宋建军
郝跃
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Xidian University
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Abstract

The invention discloses a strain BiCMOS (Bipolar Complementary Metal-Oxide-Semiconductor Transistor) integrated device based on crystal face selection and a preparation method thereof. The preparation method comprises the steps of: preparing an SOI (Silicon On Insulator) substrate, wherein the lower base body is (110) crystal face and the upper base body is (100) crystal face; continuously growing an N-Si layer, a P-SiGe layer and an N-Si layer on the surface of the substrate, and depositing a dielectric layer to prepare a collecting region, a base region and an emitting region, forming a collecting electrode contact region, a base electrode contact region and an emitting electrode contact region, forming a SiGe HBT (Heterojunction Bipolar Transistor) device, and preparing a deep trench isolation region; etching the deep trench in an NMOS (N-channel Metal Oxide Semiconductor) device region, selectively growing an active region of the NMOS device with the crystal face (100), and preparing a strain Si channel NMOS device; in a PMOS (P-channel Metal Oxide Semiconductor) device region, selectively growing a Si epitaxial layer with the crystal face (110), preparing a strain Si channel PMOS device on the layer; and forming the strain BiCMOS integrated device based on crystal face selection and a circuit. According to the strain BiCMOS integrated device based on crystal face selection and the preparation method of the strain BiCMOS integrated device based on crystal face selection, a performance-enhanced strain BiCMOS integrated circuit based on crystal face selection is prepared by means of characteristics that the electronic mobility of the strain Si material is higher than that of the body strain Si material and the hole mobility of the compression strain Si material is higher than that of the body strain Si material and the mobility is anisotropic adequately.

Description

A kind of strain BiCMOS integrated device and preparation method based on crystal face selection
Technical field
The invention belongs to the semiconductor integrated circuit technical field, relate in particular to strain BiCMOS integrated device and preparation method based on crystal face selection.
Background technology
The integrated circuit that occurred in 1958 is one of invention of tool influence of 20th century.The microelectronics that is born based on this invention has become the basis of existing modern technologies, quickens changing more educated, the IT application process of human society, has also changed the human mode of thinking simultaneously.It not only is the human instrument that strong nature remodeling is provided, but also has opened up a wide development space.
Semiconductor integrated circuit has become the basis of electronics industry, and people impel the development in this field very rapid to the great demand of electronics industry.In decades in the past, the fast development of electronics industry has produced tremendous influence to social development and national economy.At present, electronics industry has become worldwide largest industry, and in occupation of very big share, the output value has surpassed 10,000 hundred million dollars in the world market.
Silicon materials are used as semi-conducting material and have been experienced more than 50 year; Traditional Si CMOS and BiCMOS technology with advantages such as its low-power consumption, low noise, high input impedance, high integration, good reliabilitys in integrated circuit fields in occupation of leading position, and constantly advance according to Moore's Law.At present, in the semi-conductor market in the whole world 90%, all be that the Si basis set becomes circuit.
But along with device feature size reduces, the enhancing of integrated level and complexity, a series of new problems that relate to aspects such as material, device physics, device architecture and technology have appearred.Particularly when IC chip features size entering nanoscale; See from device angles; Problems such as the influence of the short channel effect in the nanoscale devices, high-field effect, quantum effect, parasitic parameter, technological parameter fluctuation are more and more outstanding to Effect on Performance such as device leakage electric current, subthreshold characteristic, ON state/off-state currents; The contradiction of circuit speed and power consumption will be more serious also, on the other hand, and along with the develop rapidly of wireless mobile communications; Performance to device and circuit; Have higher requirement like frequency characteristic, noise characteristic, package area, power consumption and cost etc., the device of traditional silica-based prepared and integrated circuit are especially simulated and composite signal integrated circuits, more and more can't satisfy demand novel, the high-velocity electrons system.
In order to improve the performance of device and integrated circuit, the researcher by novel semi-conducting material like GaAs, InP etc., obtaining to be suitable for the high speed device and the integrated circuit of wireless mobile communications development.Although GaAs and InP based compound device frequency excellent, its preparation technology is higher than Si complex process, cost, and the major diameter single crystal preparation is difficult, mechanical strength is low, and heat dispersion is bad, resembles SiO with Si difficult technique compatibility and shortage 2Such effects limit such as passivation layer its extensive use and development.
Because Si material carrier material transition rate is lower, so the performance of integrated circuits, the especially frequency performance that adopt Si BiCMOS technology to make have received great restriction; And for SiGe BiCMOS technology, though bipolar transistor has adopted SiGe HBT, the unipolar device that promotes for restriction BiCMOS integrated circuit frequency characteristic still adopts Si CMOS, further promotes so these all limit BiCMOS performance of integrated circuits ground.
For this reason; Will be under the situation of the mobility of charge carrier rate that does not reduce a kind of types of devices; Improve the mobility of charge carrier rate of another kind of types of devices; This patent proposes a kind of strain gauge technique that utilizes and prepares BiCMOS, promptly based on the preparation of the mixing crystal face strain BiCMOS integrated device of three polycrystal SiGe HBT.
Summary of the invention
The object of the present invention is to provide a kind of strain BiCMOS integrated device and preparation method based on crystal face selection; To realize utilizing tensile strain Si material electronics mobility to be higher than body Si material, prepare the strain BiCMOS integrated device and the circuit based on crystal face selection of performance enhancing with compressive strain Si material hole mobility is higher than body Si material and the anisotropic characteristics of mobility.
The object of the present invention is to provide a kind of strain BiCMOS integrated device based on crystal face selection, nmos device and PMOS device are strain Si MOS device, and bipolar device is a SiGe HBT device.
Further, the conducting channel of nmos device is strain Si material, the conducting channel of nmos device is a tensile strain Si material, the conducting channel of nmos device is a planar channeling.
Further, the conducting channel of PMOS device is strain Si material, the conducting channel of PMOS device is a compressive strain Si material, the conducting channel of PMOS device is a vertical-channel.
Further, nmos device is prepared in crystal face on the SOI substrate of (100), the PMOS device is prepared in crystal face on the substrate of (110).
Further, the base of SiGe HBT device is the strain SiGe material.
Further, SiGe HBT device is a planar structure.
Another object of the present invention is to provide a kind of preparation method of the strain BiCMOS integrated device based on crystal face selection, comprise the steps:
The first step, choose the Si sheet that two N types mix, wherein a slice crystal face is (110), and a slice crystal face is (100), and two doping contents are 1 ~ 5 * 10 15Cm -3, oxidation is carried out on two Si sheet surfaces, oxidated layer thickness is 0.5 ~ 1 μ m; With crystal face is the basis material of a slice of (100) as the upper strata, and in this basis material, injects hydrogen, is the basis material of a slice of (110) as lower floor with crystal face; Adopt chemico-mechanical polishing (CMP) technology that two oxide layer surfaces are polished;
Second goes on foot, two Si sheet oxide layers is opposite in the ultra-high vacuum environment mutually under 350～480 ℃ temperature, realizes bonding; Si sheet temperature behind the bonding is raise 100～200 ℃; Make the upper strata basis material in the hydrogen place fracture of injecting, the part that the upper strata basis material is unnecessary is peeled off, keep the Si material of 100 ~ 200nm; And carry out chemico-mechanical polishing (CMP) at its break surface, form the SOI substrate;
The 3rd step, utilizing the method for chemical vapor deposition (CVD), at 600～750 ℃, is the N type Si epitaxial loayer of 2～3 μ m at the substrate layer thickness of growing, and as collector region, this layer doping content is 1 * 10 16～1 * 10 17Cm -3
The 4th goes on foot, utilizes the method for chemical vapor deposition (CVD), and at 600～750 ℃, growth one layer thickness is the SiGe layer of 20 ~ 60nm on substrate, and as the base, this layer Ge component is 15 ~ 25%, and doping content is 5 * 10 18~ 5 * 10 19Cm -3
The 5th goes on foot, utilizes the method for chemical vapor deposition (CVD), and at 600～750 ℃, growth one layer thickness is the N type Si layer of 100～200nm on substrate, and as the emitter region, this layer doping content is 1 * 10 17～5 * 10 17Cm -3
The 6th goes on foot, falls with wet etching the SiO on surface 2With the SiN layer, utilize the method for chemical vapor deposition (CVD), at 600～800 ℃, be the SiO of 200 ~ 300nm at substrate surface deposit one layer thickness 2A layer and a layer thickness are the SiN layer of 100 ~ 200nm; Photoetching collector region shallow trench isolation areas goes out the shallow slot that the degree of depth is 180 ~ 300nm at the shallow trench isolation areas dry etching, utilizes chemical vapor deposition (CVD) method, at 600～800 ℃, in shallow slot, fills SiO 2
The 7th goes on foot, falls with wet etching the SiO on surface 2With the SiN layer, utilize the method for chemical vapor deposition (CVD), at 600～800 ℃, be the SiO of 200 ~ 300nm at substrate surface deposit one layer thickness 2A layer and a layer thickness are the SiN layer of 100 ~ 200nm; Photoetching base shallow trench isolation areas goes out the shallow slot that the degree of depth is 105 ~ 205nm at the shallow trench isolation areas dry etching, utilizes chemical vapor deposition (CVD) method, at 600～800 ℃, in shallow slot, fills SiO 2
The 8th goes on foot, falls with wet etching the SiO on surface 2With the SiN layer, utilize the method for chemical vapor deposition (CVD), at 600～800 ℃, be the SiO of 300 ~ 500nm at substrate surface deposit one layer thickness 2Layer; The photoetching collector region is carried out N type impurity to this zone and is injected, and making collector electrode contact zone doping content is 1 * 10 19～1 * 10 20Cm -3, form collector contact area;
The 9th step, photoetching base region carry out p type impurity to this zone and inject, and making base stage contact zone doping content is 1 * 10 19～1 * 10 20Cm -3, form the base stage contact area, and to substrate under 950～1100 ℃ of temperature, annealing 15～120s carries out impurity activation, forms SiGe HBT; Utilize the method for chemical vapor deposition (CVD) at substrate surface, at 600～800 ℃, deposit one SiO 2Layer;
The tenth step, be the SiO of 300～500nm at substrate surface thermal oxidation one layer thickness 2Layer, the photoetching area of isolation utilizes dry etch process, etches the deep trouth that the degree of depth is 3 ~ 5 μ m in the deep trench isolation zone; Utilize the method for chemical vapor deposition (CVD),, in deep trouth, fill SiO at 600～800 ℃ 2, with chemico-mechanical polishing (CMP) method, remove the unnecessary oxide layer in surface, form deep trench isolation;
The 11 step, photoetching PMOS device active region at the PMOS device active region, utilize dry etching, etch the deep trouth that the degree of depth is 3.4～5.8 μ m, the oxide layer of centre is carved pass through; Utilize chemical vapor deposition (CVD) method; At 600～750 ℃, selective epitaxial growth seven layer materials on the PMOS device active region of (110) crystal face substrate: ground floor is a N type Si resilient coating, and thickness is 1.5～2.5 μ m; This layer fills up deep trouth, and doping content is 1～5 * 10 15Cm -3The second layer is that thickness is the N type SiGe graded bedding of 1.5～2.5 μ m, and bottom Ge component is 0%, and top Ge component is 15～25%, and doping content is 1～5 * 10 15Cm -3The 3rd layer is that the Ge component is 15～25%, and thickness is the P type SiGe layer of 200～400nm, and doping content is 5～10 * 10 20Cm -3, as the drain region of PMOS device; The 4th layer is that thickness is 3 ~ 5nmP type strain Si layer, and doping content is 1～5 * 10 18Cm -3, as a P type lightly-doped source drain structure (P-LDD) layer; Layer 5 be thickness be the N type strain Si of 22～45nm as channel region, doping content is 5 * 10 16～5 * 10 17Cm -3Layer 6 is that thickness is the P type strain Si layer of 3 ~ 5nm, and doping content is 1～5 * 10 18Cm -3, as the 2nd P type lightly-doped source drain structure (P-LDD) layer; Layer 7 is that the Ge component is 15～25%, and thickness is the P type SiGe of 200～400nm, and doping content is 5～10 * 10 19Cm -3, as the source region of PMOS device;
The 12 step, photoetching nmos device active area; At the nmos device active area, utilize dry etching, etch the deep trouth that the degree of depth is 1.9～2.8 μ m; Utilize chemical vapor deposition (CVD) method; At 600～750 ℃, selective epitaxial growth four layer materials on the nmos device active area of (100) crystal face substrate: ground floor is that thickness is the P type Si resilient coating of 200～400nm, and doping content is 1～5 * 10 15Cm -3The second layer is that thickness is the P type SiGe graded bedding of 1.5～2 μ m, and bottom Ge component is 0, and top Ge component is 15～25%, and doping content is 1～5 * 10 15Cm -3The 3rd layer is that the Ge component is 15～25%, and thickness is the P type SiGe layer of 200～400nm, and doping content is 1～5 * 10 16Cm -3The 4th layer is that thickness is the N type strain Si layer of 15～20nm, and doping content is 5 * 10 16～5 * 10 17Cm -3, as the raceway groove of nmos device;
The 13 the step, utilize chemical vapor deposition (CVD) method at substrate surface, at 600～800 ℃, deposit one deck SiO 2Resilient coating and layer of sin etch leakage trench openings, utilize dry etch process, and etching the degree of depth at PMOS device drain region is that 0.3～0.7 μ m leaks groove; Utilize chemical vapor deposition (CVD) method, at 600～800 ℃, at substrate surface deposit one deck SiO 2, form the PMOS device and leak the trenched side-wall isolation; Utilize dry etching to remove the SiO on plane 2Layer only keeps the PMOS device and leaks trenched side-wall SiO 2Layer; Utilizing chemical vapor deposition (CVD) method, at 600～800 ℃, is 1～5 * 10 in substrate surface deposit doping content 20Cm -3P type Poly-Si, the PMOS device is leaked groove fills up, get rid of the PMOS device again and leak the Poly-SiGe beyond the flute surfaces, form and leak the bonding pad;
The 14 the step, utilize dry etch process, etching the degree of depth in PMOS device gate region is 0.5～0.9 μ m gate groove; Utilizing atomic layer chemical vapour deposition (ALCVD) method, at 300～400 ℃, is the HfO of the high-k of 6～10nm at the substrate surface deposition thickness 2Layer is as PMOS device gate dielectric layer; Utilizing chemical vapor deposition (CVD) method, at 600～800 ℃, is 1～5 * 10 in substrate surface deposit doping content 20Cm -3P type Poly-SiGe, the Ge component is 10～30%, and PMOS device gate groove is filled up, and gets rid of Poly-SiGe and SiO beyond the PMOS device gate groove surface again 2Layer forms the PMOS device as the grid region;
The 15 the step, etch the nmos device active area, utilize atomic layer chemical vapour deposition (ALCVD) method, at 300～400 ℃, be the HfO of the high-k of 6～10nm at the substrate surface deposition thickness 2Layer is as the nmos device gate dielectric layer; Deposit one deck intrinsic Poly-SiGe again, thickness is 100～300nm, the Ge component is 10～30%, etching N MOS device grids; Photoetching nmos device active area carries out N type ion to nmos device and injects, and forming doping content is 1～5 * 10 18Cm -3N type lightly-doped source drain structure (N-LDD); At entire substrate deposit one thickness is the SiO of 3～5nm 2Layer, dry etching falls this layer SiO 2,, form the nmos device grid as the nmos device grid curb wall;
The 16 step, carry out N type phosphonium ion at the nmos device active area and inject, autoregistration generates the source region and the drain region of nmos device, makes source region and drain region doping content reach 1～5 * 10 20Cm -3
The 17 goes on foot, makes by lithography source, leakage and the grid lead window of PMOS device, sputter layer of metal titanium (Ti) on entire substrate, and alloy, autoregistration forms metal silicide, and the metal that clean surface is unnecessary forms Metal Contact; With chemical vapor deposition (CVD) method, at 600～800 ℃, SiO grows on substrate 2Layer, photoetching lead-in wire window, splash-proofing sputtering metal, the photoetching lead-in wire, constituting conducting channel is the mixing crystal face strain BiCMOS integrated device based on three polycrystal SiGe HBT of 22～45nm.
Further, the PMOS device channel length according to the N type strain Si of the 12 step deposit layer by layer thickness confirm that get 22～45nm, the nmos device channel length is controlled by photoetching process.
Further, related maximum temperature is according to the 4th chemical vapor deposition (CVD) the technological temperature decision that go on foot in the 17 step among this preparation method, maximum temperature is smaller or equal to 800 ℃.
Further, base thickness according to the 5th the step SiGe epitaxy layer thickness decide, get 20～60nm.
Another object of the present invention is to provide a kind of preparation method of the strain BiCMOS integrated circuit based on crystal face selection, comprise the steps:
Step 1, the implementation method of SOI backing material preparation is:
(1a) choosing N type doping content is 1 * 10 15Cm -3The Si sheet, crystal face is (100), and oxidation is carried out on its surface, oxidated layer thickness is 0.5 μ m, as the upper strata basis material, and in this basis material, injects hydrogen;
(1b) choosing N type doping content is 1 * 10 15Cm -3The Si sheet, crystal face is (110), and oxidation is carried out on its surface, oxidated layer thickness is 0.5 μ m, as lower floor's basis material;
(1c) adopt chemico-mechanical polishing (CMP) technology, respectively the upper strata substrate material surface behind lower floor and the injection hydrogen is carried out polishing;
(1d) lower floor after the polishing and upper strata substrate material surface oxide layer are close to relatively, are placed ultra-high vacuum environment under 350 ℃ of temperature, to realize bonding;
(1e) substrate temperature behind the bonding is raise 200 ℃; Make the upper strata basis material in the hydrogen place fracture of injecting, the part that the upper strata basis material is unnecessary is peeled off, keep the Si material of 100nm; And carry out chemico-mechanical polishing (CMP) at this break surface, form soi structure;
Step 2, the implementation method of bipolar device active area preparation is:
(2a) growth one layer thickness is the N type epitaxy Si layer of 2 μ m on substrate, and as collector region, this layer doping content is 1 * 10 16Cm -3
(2b) utilize the method for chemical vapor deposition (CVD), at 600 ℃, growth one layer thickness is the SiGe layer of 20nm on substrate, and as the base, this layer Ge component is 15%, and doping content is 5 * 10 18Cm -3
(2c) utilize the method for chemical vapor deposition (CVD), at 600 ℃, growth one layer thickness is the N type Si layer of 100nm on substrate, and as the emitter region, this layer doping content is 1 * 10 17Cm -3
Step 3, the implementation method of collector electrode shallow-trench isolation preparation is:
(5a) fall surperficial SiO with wet etching 2With the SiN layer;
(3b) utilizing the method for chemical vapor deposition (CVD), at 600 ℃, is the SiO of 200nm at substrate surface deposit one layer thickness 2Layer;
(3c) utilizing the method for chemical vapor deposition (CVD), at 600 ℃, is the SiN layer of 100nm at substrate surface deposit one layer thickness;
(3d) photoetching collector electrode shallow trench isolation areas goes out the shallow slot that the degree of depth is 180nm at the shallow trench isolation areas dry etching;
(3e) utilize chemical vapor deposition (CVD) method,, in shallow slot, fill SiO at 600 ℃ 2, form the collector electrode shallow-trench isolation;
Step 4, the implementation method of base stage shallow-trench isolation preparation is:
(4a) fall surperficial SiO with wet etching 2With the SiN layer;
(4b) utilizing the method for chemical vapor deposition (CVD), at 600 ℃, is the SiO of 200nm at substrate surface deposit one layer thickness 2Layer;
(4c) utilizing the method for chemical vapor deposition (CVD), at 600 ℃, is the SiN layer of 100nm at substrate surface deposit one layer thickness;
(4d) photoetching base stage shallow trench isolation areas goes out the shallow slot that the degree of depth is 105nm at the shallow trench isolation areas dry etching;
(4e) utilize chemical vapor deposition (CVD) method,, in shallow slot, fill SiO at 600 ℃ 2, form the base stage shallow-trench isolation;
Step 5, the implementation method that SiGe HBT forms is:
(5a) fall surperficial SiO with wet etching 2With the SiN layer;
(5b) utilizing the method for chemical vapor deposition (CVD), at 600 ℃, is the SiO of 300nm at substrate surface deposit one layer thickness 2Layer;
(5c) photoetching collector region is carried out N type impurity to this zone and is injected, and making collector electrode contact zone doping content is 1 * 10 19Cm -3, form collector electrode;
(5d) photoetching base region carries out p type impurity to this zone and injects, and making base stage contact zone doping content is 1 * 10 19Cm -3, form base stage;
(5e) to substrate under 950 ℃ of temperature, annealing 120s carries out impurity activation, forms SiGe HBT;
(5f) utilize the method for chemical vapor deposition (CVD) at substrate surface, at 600 ℃, deposit one SiO 2Layer;
Step 6, the implementation method of deep trench isolation district preparation is:
Be the SiO of 300nm (6a) at substrate surface thermal oxidation one layer thickness 2Layer;
(6b) the photoetching area of isolation utilizes dry etch process, etches the deep trouth that the degree of depth is 3 μ m in the deep trench isolation zone;
(6c) utilize chemical vapor deposition (CVD) method,, in deep trouth, fill SiO at 600 ℃ 2
(6d) with chemico-mechanical polishing (CMP) method, remove the unnecessary oxide layer in surface, form deep trench isolation;
Step 7, the implementation method of PMOS device active region preparation is:
(7a) photoetching PMOS device active region at the PMOS device active region, utilizes dry etching, etches the deep trouth that the degree of depth is 3.4 μ m, oxide layer is carved pass through;
(7b) utilizing the method for chemical vapor deposition (CVD), at 600 ℃, is the N type Si resilient coating of 1.5 μ m along (110) crystal face layer thickness of growing in deep trouth, and doping content is 1 * 10 15Cm -3
(7c) utilize the method for chemical vapor deposition (CVD), at 600 ℃, growth one layer thickness is the SiGe of the N type Ge component trapezoidal profile of 1.5 μ m on the Si resilient coating, and bottom Ge component is 0%, and the top is 15%, and doping content is 1 * 10 15Cm -3
(7d) utilize the method for chemical vapor deposition (CVD), at 600 ℃, growth one layer thickness is the P type SiGe layer of 200nm on the SiGe layer of Ge component trapezoidal profile, and the Ge component is 15%, and doping content is 5 * 10 19Cm -3, as the drain region of PMOS device;
(7e) utilize the method for chemical vapor deposition (CVD), at 600 ℃, growth thickness is the P type strain Si layer of 3nm on substrate, and doping content is 1 * 10 18Cm -3, as a P type lightly-doped source drain structure (P-LDD) layer;
(7f) utilize chemical vapor deposition (CVD) method, at 600 ℃, growth one layer thickness is the N type strain Si layer of 22nm on the drain region, and doping content is 5 * 10 16Cm -3, as the raceway groove of PMOS device;
(7g) utilize the method for chemical vapor deposition (CVD), at 600 ℃, growth thickness is the P type strain Si layer of 3nm on substrate, and doping content is 1 * 10 18Cm -3, as the 2nd P type lightly-doped source drain structure (P-LDD) layer;
(7h) utilize chemical vapor deposition (CVD) method, at 600 ℃, growth one layer thickness is the P type SiGe layer of 200nm on strain Si layer, and the Ge component is 15%, and doping content is 5 * 10 19Cm -3, as the source region of PMOS device;
Step 8, the implementation method of nmos device active area preparation is:
(8a) photoetching nmos device active area at the nmos device active area, utilizes dry etching, etches the deep trouth that the degree of depth is 1.9 μ m;
(8b) utilizing the method for chemical vapor deposition (CVD), at 600 ℃, is the P type Si resilient coating of 200nm at nmos device active area (100) the crystal face layer thickness of growing, and doping content is 1 * 10 15Cm -3
(8c) utilize the method for chemical vapor deposition (CVD), at 600 ℃, growth one layer thickness is the SiGe of the P type Ge component trapezoidal profile of 1.5 μ m on the Si resilient coating, and bottom Ge component is 0%, and the top is 15%, and doping content is 1 * 10 15Cm -3
(8d) utilize the method for chemical vapor deposition (CVD), at 600 ℃, growth one layer thickness is the P type SiGe layer of 200nm on the SiGe layer of Ge component trapezoidal profile, and the Ge component is 15%, and doping content is 1 * 10 16Cm -3
(8e) utilize chemical vapor deposition (CVD) method, at 600 ℃, regrowth one layer thickness is the P type strain Si layer of 15nm, and doping content is 5 * 10 16Cm -3, as the raceway groove of nmos device;
The implementation method that step 9, PMOS device are leaked the bonding pad preparation is:
(9a) utilize chemical vapor deposition (CVD) method, at 600 ℃, at substrate surface consecutive deposition one deck SiO 2And layer of sin;
(9b) etch the PMOS device and leak trench openings, utilize dry etch process, etching the degree of depth at PMOS device drain region is that 0.3 μ m leaks groove;
(9c) utilize chemical vapor deposition (CVD) method, at 600 ℃, at substrate surface deposit one deck SiO 2, utilize dry etching to remove the SiO on plane 2Layer only keeps the PMOS device and leaks trenched side-wall SiO 2Layer forms the PMOS device and leaks the trenched side-wall isolation;
(9d) utilizing chemical vapor deposition (CVD) method, at 600 ℃, is 1 * 10 in substrate surface deposit doping content 20Cm -3P type Poly-Si, the PMOS device is leaked groove fills up, get rid of the PMOS device again and leak the Poly-Si beyond the flute surfaces, form and leak the bonding pad;
Step 10, the implementation method of P mos gate bonding pad preparation is:
(10a) utilize dry etch process, etching the degree of depth in PMOS device drain-gate zone is 0.5 μ m gate groove;
(10b) utilizing atomic layer chemical vapour deposition (ALCVD) method, at 300 ℃, is the HfO of the high-k of 6nm at the substrate surface deposition thickness 2Layer is as PMOS device gate dielectric layer;
(10c) utilizing chemical vapor deposition (CVD) method, at 600 ℃, is 1 * 10 in substrate surface deposit doping content 20Cm -3P type Poly-SiGe, the Ge component is 10%, and PMOS device gate groove is filled up, and gets rid of Poly-SiGe and SiO beyond the PMOS device gate groove surface again 2Layer forms the PMOS device as the grid region;
Step 11, the implementation method of nmos device preparation is:
(11a) etching the nmos device active area, utilize atomic layer chemical vapour deposition (ALCVD) method, at 300 ℃, is the HfO of the high-k of 6nm at the substrate surface deposition thickness 2Layer is as the nmos device gate dielectric layer;
(11b) utilize chemical vapor deposition (CVD) method, at 600 ℃, deposit one deck Poly-SiGe on gate dielectric layer, thickness is 100nm, the Ge component is 10%;
(11c) etching Poly-SiGe, HfO 2Layer forms grid;
(11d) photoetching nmos device active area carries out N type ion to nmos device and injects, and forming doping content is 1 * 10 18Cm -3N type lightly-doped source drain structure (N-LDD);
(11e) utilize chemical vapor deposition (CVD) method, at 600 ℃, deposit one thickness is the SiO of 3nm on entire substrate 2Layer, dry etching falls this layer SiO 2, keep the nmos device grid curb wall, form the nmos device grid;
(11f) carry out N type phosphonium ion at the nmos device active area and inject, autoregistration generates the source region and the drain region of nmos device, makes source region and drain region doping content reach 1 * 10 20Cm -3, form nmos device;
Step 12, the implementation method that constitutes the preparation of BiCMOS integrated circuit is:
(12a) photoetching lead-in wire window;
(12b) sputter layer of metal titanium (Ti) on entire substrate, alloy, autoregistration forms metal silicide, and the metal that clean surface is unnecessary forms Metal Contact;
(12c) splash-proofing sputtering metal; The photoetching lead-in wire; Form leakage, source, the gate electrode of source, grid, drain electrode and the PMOS device of nmos device respectively; Bipolar transistor emitter, base stage, collector electrode metal lead-in wire, finally constituting the CMOS conducting channel is strain BiCMOS integrated device and the circuit based on crystal face selection of 22nm.
The present invention has following advantage:
1. the strain BiCMOS integrated device based on crystal face selection of the present invention's preparation has adopted mixing crystal face substrate technology; Promptly on same substrate slice, be distributed with (100) and (110) these two kinds of crystal faces; On (110) crystal face, be compressive strain for strain Si PMOS device; The mobility in its hole is higher than body Si material, and on (100) crystal face, is tensile strain for strain Si nmos device, and the mobility of its electronics also is higher than body Si material; Therefore, electric properties such as this device frequency and current driving ability are higher than unidimensional body Si cmos device;
2. the strain BiCMOS integrated device based on crystal face selection of the present invention preparation; Employing selective epitaxial technology; At nmos device and PMOS device active region selective growth strain Si material, the flexibility that has improved designs has strengthened BiCMOS device and integrated circuit electric property respectively;
3. in the mixing crystal face strain BiCMOS integrated device technology of the present invention's preparation based on three polycrystal SiGe HBT; Adopt the Poly-SiGe material as grid; Its work function changes with the variation of Ge component, and through regulating Ge component in the Poly-SiGe grid, realization CMOS threshold voltage can be adjusted continuously; Reduce processing step, reduced technology difficulty;
4. the maximum temperature that relates in the strain BiCMOS integrated device process based on crystal face selection of the present invention's preparation is 800 ℃; Be lower than the technological temperature that causes strained Si channel stress relaxation; Therefore this preparation method can keep strained Si channel stress effectively, improves the performance of integrated circuit;
5. the raceway groove based on PMOS device in the strain BiCMOS integrated device of crystal face selection of the present invention's preparation is back type; Promptly grid can be controlled raceway groove on four sides in groove; Therefore, this device has increased the width of raceway groove in limited zone, thereby has improved the current driving ability of device; Increase the integrated level of integrated circuit, reduced the manufacturing cost of lsi unit area;
6. in the strain BiCMOS integrated device based on crystal face selection of the present invention's preparation, in the MOS device architecture,, introduce lightly-doped source and leak (LDD) technology, improved device performance in order effectively to suppress short-channel effect;
7. in the strain BiCMOS integrated device spare structure based on crystal face selection of the present invention's preparation, adopted the HfO of high K value 2As gate medium, improved the grid-control ability of device, strengthened the electric property of device.
Description of drawings
Fig. 1 is provided by the invention based on the strain BiCMOS integrated device of crystal face selection and circuit preparation method's realization flow figure.
Embodiment
In order to make the object of the invention, technical scheme and advantage clearer,, the present invention is further elaborated below in conjunction with accompanying drawing and embodiment.Should be appreciated that specific embodiment described herein only in order to explanation the present invention, and be not used in qualification the present invention.
The embodiment of the invention provides a kind of strain BiCMOS integrated device based on crystal face selection, and nmos device and PMOS device are strain Si MOS device, and bipolar device is a SiGe HBT device.
As a prioritization scheme of the embodiment of the invention, the conducting channel of nmos device is a strain Si material, and the conducting channel of nmos device is a tensile strain Si material, and the conducting channel of nmos device is a planar channeling.
As a prioritization scheme of the embodiment of the invention, the conducting channel of PMOS device is a strain Si material, and the conducting channel of PMOS device is a compressive strain Si material, and the conducting channel of PMOS device is a vertical-channel.
As a prioritization scheme of the embodiment of the invention, nmos device is prepared in crystal face on the SOI substrate of (100), and the PMOS device is prepared in crystal face on the substrate of (110).
As a prioritization scheme of the embodiment of the invention, the base of SiGe HBT device is the strain SiGe material.
As a prioritization scheme of the embodiment of the invention, SiGe HBT device is the whole plane structure.
Following with reference to accompanying drawing 1, the technological process of the strain BiCMOS integrated device that the present invention is based on crystal face selection and circuit preparation is described in further detail.
Embodiment 1: preparation 22nm is based on the strain BiCMOS integrated device and the circuit of crystal face selection, and concrete steps are following:
Step 1, the preparation of SOI backing material.
(1a) choosing N type doping content is 1 * 10 15Cm -3The Si sheet, crystal face is (100), and oxidation is carried out on its surface, oxidated layer thickness is 0.5 μ m, as the upper strata basis material, and in this basis material, injects hydrogen;
(1b) choosing N type doping content is 1 * 10 15Cm -3The Si sheet, crystal face is (110), and oxidation is carried out on its surface, oxidated layer thickness is 0.5 μ m, as lower floor's basis material;
(1c) adopt chemico-mechanical polishing (CMP) technology, respectively the upper strata substrate material surface behind lower floor and the injection hydrogen is carried out polishing;
(1d) lower floor after the polishing and upper strata substrate material surface oxide layer are close to relatively, are placed ultra-high vacuum environment under 350 ℃ of temperature, to realize bonding;
(1e) substrate temperature behind the bonding is raise 200 ℃; Make the upper strata basis material in the hydrogen place fracture of injecting, the part that the upper strata basis material is unnecessary is peeled off, keep the Si material of 100nm; And carry out chemico-mechanical polishing (CMP) at this break surface, form soi structure.
Step 2, the preparation of bipolar device active area.
(2a) growth one layer thickness is the N type epitaxy Si layer of 2 μ m on substrate, and as collector region, this layer doping content is 1 * 10 16Cm -3
(2b) utilize the method for chemical vapor deposition (CVD), at 600 ℃, growth one layer thickness is the SiGe layer of 20nm on substrate, and as the base, this layer Ge component is 15%, and doping content is 5 * 10 18Cm -3
(2c) utilize the method for chemical vapor deposition (CVD), at 600 ℃, growth one layer thickness is the N type Si layer of 100nm on substrate, and as the emitter region, this layer doping content is 1 * 10 17Cm -3
Step 3, the preparation of collector electrode shallow-trench isolation.
(5a) fall surperficial SiO with wet etching 2With the SiN layer;
(3b) utilizing the method for chemical vapor deposition (CVD), at 600 ℃, is the SiO of 200nm at substrate surface deposit one layer thickness 2Layer;
(3c) utilizing the method for chemical vapor deposition (CVD), at 600 ℃, is the SiN layer of 100nm at substrate surface deposit one layer thickness;
(3d) photoetching collector electrode shallow trench isolation areas goes out the shallow slot that the degree of depth is 180nm at the shallow trench isolation areas dry etching;
(3e) utilize chemical vapor deposition (CVD) method,, in shallow slot, fill SiO at 600 ℃ 2, form the collector electrode shallow-trench isolation.
Step 4, the preparation of base stage shallow-trench isolation.
(4a) fall surperficial SiO with wet etching 2With the SiN layer;
(4b) utilizing the method for chemical vapor deposition (CVD), at 600 ℃, is the SiO of 200nm at substrate surface deposit one layer thickness 2Layer;
(4c) utilizing the method for chemical vapor deposition (CVD), at 600 ℃, is the SiN layer of 100nm at substrate surface deposit one layer thickness;
(4d) photoetching base stage shallow trench isolation areas goes out the shallow slot that the degree of depth is 105nm at the shallow trench isolation areas dry etching;
(4e) utilize chemical vapor deposition (CVD) method,, in shallow slot, fill SiO at 600 ℃ 2, form the base stage shallow-trench isolation.
Step 5, SiGe HBT forms.
(5a) fall surperficial SiO with wet etching 2With the SiN layer;
(5b) utilizing the method for chemical vapor deposition (CVD), at 600 ℃, is the SiO of 300nm at substrate surface deposit one layer thickness 2Layer;
(5c) photoetching collector region is carried out N type impurity to this zone and is injected, and making collector electrode contact zone doping content is 1 * 10 19Cm -3, form collector electrode;
(5d) photoetching base region carries out p type impurity to this zone and injects, and making base stage contact zone doping content is 1 * 10 19Cm -3, form base stage;
(5e) to substrate under 950 ℃ of temperature, annealing 120s carries out impurity activation, forms SiGe HBT;
(5f) utilize the method for chemical vapor deposition (CVD) at substrate surface, at 600 ℃, deposit one SiO 2Layer.
Step 6, the preparation of deep trench isolation district.
Be the SiO of 300nm (6a) at substrate surface thermal oxidation one layer thickness 2Layer;
(6b) the photoetching area of isolation utilizes dry etch process, etches the deep trouth that the degree of depth is 3 μ m in the deep trench isolation zone;
(6c) utilize chemical vapor deposition (CVD) method,, in deep trouth, fill SiO at 600 ℃ 2
(6d) with chemico-mechanical polishing (CMP) method, remove the unnecessary oxide layer in surface, form deep trench isolation.
Step 7, the preparation of PMOS device active region.
(7a) photoetching PMOS device active region at the PMOS device active region, utilizes dry etching, etches the deep trouth that the degree of depth is 3.4 μ m, oxide layer is carved pass through;
(7b) utilizing the method for chemical vapor deposition (CVD), at 600 ℃, is the N type Si resilient coating of 1.5 μ m along (110) crystal face layer thickness of growing in deep trouth, and doping content is 1 * 10 15Cm -3
(7c) utilize the method for chemical vapor deposition (CVD), at 600 ℃, growth one layer thickness is the SiGe of the N type Ge component trapezoidal profile of 1.5 μ m on the Si resilient coating, and bottom Ge component is 0%, and the top is 15%, and doping content is 1 * 10 15Cm -3
(7d) utilize the method for chemical vapor deposition (CVD), at 600 ℃, growth one layer thickness is the P type SiGe layer of 200nm on the SiGe layer of Ge component trapezoidal profile, and the Ge component is 15%, and doping content is 5 * 10 19Cm -3, as the drain region of PMOS device;
(7e) utilize the method for chemical vapor deposition (CVD), at 600 ℃, growth thickness is the P type strain Si layer of 3nm on substrate, and doping content is 1 * 10 18Cm -3, as a P type lightly-doped source drain structure (P-LDD) layer;
(7f) utilize chemical vapor deposition (CVD) method, at 600 ℃, growth one layer thickness is the N type strain Si layer of 22nm on the drain region, and doping content is 5 * 10 16Cm -3, as the raceway groove of PMOS device;
(7g) utilize the method for chemical vapor deposition (CVD), at 600 ℃, growth thickness is the P type strain Si layer of 3nm on substrate, and doping content is 1 * 10 18Cm -3, as the 2nd P type lightly-doped source drain structure (P-LDD) layer;
(7h) utilize chemical vapor deposition (CVD) method, at 600 ℃, growth one layer thickness is the P type SiGe layer of 200nm on strain Si layer, and the Ge component is 15%, and doping content is 5 * 10 19Cm -3, as the source region of PMOS device.
Step 8, the preparation of nmos device active area.
(8a) photoetching nmos device active area at the nmos device active area, utilizes dry etching, etches the deep trouth that the degree of depth is 1.9 μ m;
(8b) utilizing the method for chemical vapor deposition (CVD), at 600 ℃, is the P type Si resilient coating of 200nm at nmos device active area (100) the crystal face layer thickness of growing, and doping content is 1 * 10 15Cm -3
(8c) utilize the method for chemical vapor deposition (CVD), at 600 ℃, growth one layer thickness is the SiGe of the P type Ge component trapezoidal profile of 1.5 μ m on the Si resilient coating, and bottom Ge component is 0%, and the top is 15%, and doping content is 1 * 10 15Cm -3
(8d) utilize the method for chemical vapor deposition (CVD), at 600 ℃, growth one layer thickness is the P type SiGe layer of 200nm on the SiGe layer of Ge component trapezoidal profile, and the Ge component is 15%, and doping content is 1 * 10 16Cm -3
(8e) utilize chemical vapor deposition (CVD) method, at 600 ℃, regrowth one layer thickness is the P type strain Si layer of 15nm, and doping content is 5 * 10 16Cm -3, as the raceway groove of nmos device.
Step 9, PMOS device are leaked the bonding pad preparation.
(9a) utilize chemical vapor deposition (CVD) method, at 600 ℃, at substrate surface consecutive deposition one deck SiO 2And layer of sin;
(9b) etch the PMOS device and leak trench openings, utilize dry etch process, etching the degree of depth at PMOS device drain region is that 0.3 μ m leaks groove;
(9c) utilize chemical vapor deposition (CVD) method, at 600 ℃, at substrate surface deposit one deck SiO 2, utilize dry etching to remove the SiO on plane 2Layer only keeps the PMOS device and leaks trenched side-wall SiO 2Layer forms the PMOS device and leaks the trenched side-wall isolation;
(9d) utilizing chemical vapor deposition (CVD) method, at 600 ℃, is 1 * 10 in substrate surface deposit doping content 20Cm -3P type Poly-Si, the PMOS device is leaked groove fills up, get rid of the PMOS device again and leak the Poly-Si beyond the flute surfaces, form and leak the bonding pad.
Step 10, the preparation of P mos gate bonding pad.
(10a) utilize dry etch process, etching the degree of depth in PMOS device drain-gate zone is 0.5 μ m gate groove;
(10b) utilizing atomic layer chemical vapour deposition (ALCVD) method, at 300 ℃, is the HfO of the high-k of 6nm at the substrate surface deposition thickness 2Layer is as PMOS device gate dielectric layer;
(10c) utilizing chemical vapor deposition (CVD) method, at 600 ℃, is 1 * 10 in substrate surface deposit doping content 20Cm -3P type Poly-SiGe, the Ge component is 10%, and PMOS device gate groove is filled up, and gets rid of Poly-SiGe and SiO beyond the PMOS device gate groove surface again 2Layer forms the PMOS device as the grid region.
Step 11, the nmos device preparation.
(11a) etching the nmos device active area, utilize atomic layer chemical vapour deposition (ALCVD) method, at 300 ℃, is the HfO of the high-k of 6nm at the substrate surface deposition thickness 2Layer is as the nmos device gate dielectric layer;
(11b) utilize chemical vapor deposition (CVD) method, at 600 ℃, deposit one deck Poly-SiGe on gate dielectric layer, thickness is 100nm, the Ge component is 10%;
(11c) etching Poly-SiGe, HfO 2Layer forms grid;
(11d) photoetching nmos device active area carries out N type ion to nmos device and injects, and forming doping content is 1 * 10 18Cm -3N type lightly-doped source drain structure (N-LDD);
(11e) utilize chemical vapor deposition (CVD) method, at 600 ℃, deposit one thickness is the SiO of 3nm on entire substrate 2Layer, dry etching falls this layer SiO 2, keep the nmos device grid curb wall, form the nmos device grid;
(11f) carry out N type phosphonium ion at the nmos device active area and inject, autoregistration generates the source region and the drain region of nmos device, makes source region and drain region doping content reach 1 * 10 20Cm -3, form nmos device.
Step 12 constitutes the preparation of BiCMOS integrated circuit.
(12a) photoetching lead-in wire window;
(12b) sputter layer of metal titanium (Ti) on entire substrate, alloy, autoregistration forms metal silicide, and the metal that clean surface is unnecessary forms Metal Contact;
(12c) splash-proofing sputtering metal; The photoetching lead-in wire; Form leakage, source, the gate electrode of source, grid, drain electrode and the PMOS device of nmos device respectively; Bipolar transistor emitter, base stage, collector electrode metal lead-in wire, finally constituting the CMOS conducting channel is strain BiCMOS integrated device and the circuit based on crystal face selection of 22nm.
Embodiment 2: preparation 30nm is based on the strain BiCMOS integrated device and the circuit of crystal face selection, and concrete steps are following:
Step 1, the preparation of SOI backing material.
(1a) choosing N type doping content is 3 * 10 15Cm -3The Si sheet, crystal face is (100), and oxidation is carried out on its surface, oxidated layer thickness is 0.75 μ m, as the basis material on upper strata, and in this basis material, injects hydrogen;
(1b) choosing N type doping content is 3 * 10 15Cm -3The Si sheet, crystal face is (110), and oxidation is carried out on its surface, oxidated layer thickness is 0.75 μ m, as the basis material of lower floor;
(1c) adopt chemico-mechanical polishing (CMP) technology, respectively the upper strata substrate material surface behind lower floor and the injection hydrogen is carried out polishing;
(1d) lower floor after the polishing and upper strata substrate material surface oxide layer are close to relatively, are placed ultra-high vacuum environment under 400 ℃ of temperature, to realize bonding;
(1e) substrate temperature behind the bonding is raise 150 ℃; Make the upper strata basis material in the hydrogen place fracture of injecting, the part that the upper strata basis material is unnecessary is peeled off, keep the Si material of 150nm; And carry out chemico-mechanical polishing (CMP) at this break surface, form soi structure.
Step 2, the preparation of bipolar device active area.
(2c) growth one layer thickness is the N type epitaxy Si layer of 2.5 μ m on substrate, and as collector region, this layer doping content is 5 * 10 16Cm -3
(2d) utilize the method for chemical vapor deposition (CVD), at 700 ℃, growth one layer thickness is the SiGe layer of 40nm on substrate, and as the base, this layer Ge component is 20%, and doping content is 1 * 10 19Cm -3
(2e) utilize the method for chemical vapor deposition (CVD), at 700 ℃, growth one layer thickness is the N type Si layer of 150nm on substrate, and as the emitter region, this layer doping content is 3 * 10 17Cm -3
Step 3, the preparation of collector electrode shallow-trench isolation.
(3a) fall surperficial SiO with wet etching 2With the SiN layer;
(3b) utilizing the method for chemical vapor deposition (CVD), at 700 ℃, is the SiO of 240nm at substrate surface deposit one layer thickness 2Layer;
(3c) utilizing the method for chemical vapor deposition (CVD), at 700 ℃, is the SiN layer of 150nm at substrate surface deposit one layer thickness;
(3d) photoetching collector electrode shallow trench isolation areas goes out the shallow slot that the degree of depth is 240nm at the shallow trench isolation areas dry etching;
(3e) utilize chemical vapor deposition (CVD) method,, in shallow slot, fill SiO at 700 ℃ 2, form the collector electrode shallow-trench isolation.
Step 4, the preparation of base stage shallow-trench isolation.
(4a) fall surperficial SiO with wet etching 2With the SiN layer;
(4b) utilizing the method for chemical vapor deposition (CVD), at 700 ℃, is the SiO of 240nm at substrate surface deposit one layer thickness 2Layer;
(4c) utilizing the method for chemical vapor deposition (CVD), at 700 ℃, is the SiN layer of 150nm at substrate surface deposit one layer thickness;
(4d) photoetching base stage shallow trench isolation areas goes out the shallow slot that the degree of depth is 155nm at the shallow trench isolation areas dry etching;
(4e) utilize chemical vapor deposition (CVD) method,, in shallow slot, fill SiO at 700 ℃ 2, form the base stage shallow-trench isolation.
Step 5, SiGe HBT forms.
(5a) fall surperficial SiO with wet etching 2With the SiN layer;
(5b) utilizing the method for chemical vapor deposition (CVD), at 700 ℃, is the SiO of 400nm at substrate surface deposit one layer thickness 2Layer;
(5c) photoetching collector region is carried out N type impurity to this zone and is injected, and making collector electrode contact zone doping content is 5 * 10 19Cm -3, form collector electrode;
(5d) photoetching base region carries out p type impurity to this zone and injects, and making base stage contact zone doping content is 5 * 10 19Cm -3, form base stage;
(5e) to substrate under 1000 ℃ of temperature, annealing 60s carries out impurity activation, forms SiGe HBT;
(5f) utilize the method for chemical vapor deposition (CVD) at substrate surface, at 700 ℃, deposit one SiO 2Layer.
Step 6, the preparation of deep trench isolation district.
Be the SiO of 400nm (6a) at substrate surface thermal oxidation one layer thickness 2Layer;
(6b) the photoetching area of isolation utilizes dry etch process, etches the deep trouth that the degree of depth is 4 μ m in the deep trench isolation zone;
(6c) utilize chemical vapor deposition (CVD) method,, in deep trouth, fill SiO at 700 ℃ 2
(6d) with chemico-mechanical polishing (CMP) method, remove the unnecessary oxide layer in surface, form deep trench isolation.
Step 7, the preparation of PMOS device active region.
(7a) photoetching PMOS device active region at the PMOS device active region, utilizes dry etching, etches the deep trouth that the degree of depth is 4.6 μ m, oxide layer is carved pass through;
(7b) utilizing the method for chemical vapor deposition (CVD), at 700 ℃, is the N type Si resilient coating of 2 μ m along (110) crystal face layer thickness of growing in deep trouth, and doping content is 3 * 10 15Cm -3
(7c) utilize the method for chemical vapor deposition (CVD), at 700 ℃, growth one layer thickness is the SiGe of the N type Ge component trapezoidal profile of 2 μ m on the Si resilient coating, and bottom Ge component is 0%, and the top is 20%, and doping content is 3 * 10 15Cm -3
(7d) utilize the method for chemical vapor deposition (CVD), at 700 ℃, growth one layer thickness is the P type SiGe layer of 300nm on the SiGe layer of Ge component trapezoidal profile, and the Ge component is 20%, and doping content is 8 * 10 19Cm -3, as the drain region of PMOS device;
(7e) utilize the method for chemical vapor deposition (CVD), at 700 ℃, growth thickness is the P type strain Si layer of 4nm on substrate, and doping content is 3 * 10 18Cm -3, as a P type lightly-doped source drain structure (P-LDD) layer;
(7f) utilize chemical vapor deposition (CVD) method, at 700 ℃, growth one layer thickness is the N type strain Si layer of 30nm on the drain region, and doping content is 1 * 10 17Cm -3, as the raceway groove of PMOS device;
(7g) utilize the method for chemical vapor deposition (CVD), at 700 ℃, growth thickness is the P type strain Si layer of 4nm on substrate, and doping content is 3 * 10 18Cm -3, as the 2nd P type lightly-doped source drain structure (P-LDD) layer;
(7h) utilize chemical vapor deposition (CVD) method, at 700 ℃, growth one layer thickness is the P type SiGe layer of 300nm on strain Si layer, and the Ge component is 20%, and doping content is 8 * 10 19Cm -3, as the source region of PMOS device.
Step 8, the preparation of nmos device active area.
(8a) photoetching nmos device active area at the nmos device active area, utilizes dry etching, etches the deep trouth that the degree of depth is 2.3 μ m;
(8b) utilizing the method for chemical vapor deposition (CVD), at 700 ℃, is the P type Si resilient coating of 300nm at nmos device active area (100) the crystal face layer thickness of growing, and doping content is 3 * 10 15Cm -3
(8c) utilize the method for chemical vapor deposition (CVD), at 700 ℃, growth one layer thickness is the SiGe of the P type Ge component trapezoidal profile of 1.75 μ m on the Si resilient coating, and bottom Ge component is 0%, and the top is 20%, and doping content is 3 * 10 15Cm -3
(8d) utilize the method for chemical vapor deposition (CVD), at 700 ℃, growth one layer thickness is the P type SiGe layer of 300nm on the SiGe layer of Ge component trapezoidal profile, and the Ge component is 20%, and doping content is 3 * 10 16Cm -3
(8e) utilize chemical vapor deposition (CVD) method, at 700 ℃, regrowth one layer thickness is the P type strain Si layer of 17nm, and doping content is 1 * 10 17Cm -3, as the raceway groove of nmos device.
Step 9, PMOS device are leaked the bonding pad preparation.
(9a) utilize chemical vapor deposition (CVD) method, at 700 ℃, at substrate surface consecutive deposition one deck SiO 2And layer of sin;
(9b) etch the PMOS device and leak trench openings, utilize dry etch process, etching the degree of depth at PMOS device drain region is that 0.5 μ m leaks groove;
(9c) utilize chemical vapor deposition (CVD) method, at 700 ℃, at substrate surface deposit one deck SiO 2, utilize dry etching to remove the SiO on plane 2Layer only keeps the PMOS device and leaks trenched side-wall SiO 2Layer forms the PMOS device and leaks the trenched side-wall isolation;
(9d) utilizing chemical vapor deposition (CVD) method, at 700 ℃, is 3 * 10 in substrate surface deposit doping content 20Cm -3P type Poly-Si, the PMOS device is leaked groove fills up, get rid of the PMOS device again and leak the Poly-Si beyond the flute surfaces, form and leak the bonding pad.
Step 10, the preparation of PMOS device grid bonding pad.
(10a) utilize dry etch process, etching the degree of depth in PMOS device drain-gate zone is 0.7 μ m gate groove;
(10b) utilizing atomic layer chemical vapour deposition (ALCVD) method, at 350 ℃, is the HfO of the high-k of 8nm at the substrate surface deposition thickness 2Layer is as PMOS device gate dielectric layer;
(10c) utilizing chemical vapor deposition (CVD) method, at 700 ℃, is 3 * 10 in substrate surface deposit doping content 20Cm -3P type Poly-SiGe, the Ge component is 20%, and PMOS device gate groove is filled up, and gets rid of Poly-SiGe and SiO beyond the PMOS device gate groove surface again 2Layer forms the PMOS device as the grid region.
Step 11, the nmos device preparation.
(11a) etching the nmos device active area, utilize atomic layer chemical vapour deposition (ALCVD) method, at 350 ℃, is the HfO of the high-k of 8nm at the substrate surface deposition thickness 2Layer is as the nmos device gate dielectric layer;
(11b) utilize chemical vapor deposition (CVD) method, at 700 ℃, deposit one deck intrinsic Poly-SiGe on gate dielectric layer, thickness is 200nm, the Ge component is 20%;
(11c) etching Poly-SiGe, HfO 2Layer forms grid;
(11d) photoetching nmos device active area carries out N type ion to nmos device and injects, and forming doping content is 3 * 10 18Cm -3N type lightly-doped source drain structure (N-LDD);
(11e) utilize chemical vapor deposition (CVD) method, at 700 ℃, deposit one thickness is the SiO of 4nm on entire substrate 2Layer, dry etching falls this layer SiO 2, keep the nmos device grid curb wall, form the nmos device grid;
(11f) carry out N type phosphonium ion at the nmos device active area and inject, autoregistration generates the source region and the drain region of nmos device, makes source region and drain region doping content reach 3 * 10 20Cm -3, form nmos device.
Step 12 constitutes the BiCMOS integrated circuit.
(12a) photoetching lead-in wire window;
(12b) sputter layer of metal titanium (Ti) on entire substrate, alloy, autoregistration forms metal silicide, and the metal that clean surface is unnecessary forms Metal Contact;
(12c) splash-proofing sputtering metal; The photoetching lead-in wire; Form leakage, source, the gate electrode of source, grid, drain electrode and the PMOS device of nmos device respectively; Bipolar transistor emitter, base stage, collector electrode metal lead-in wire, finally constituting conducting channel is strain BiCMOS integrated device and the circuit based on crystal face selection of 30nm.
Embodiment 3: preparation 45nm is based on the strain BiCMOS integrated device and the circuit of crystal face selection, and concrete steps are following:
Step 1, the preparation of SOI backing material.
(1a) choosing N type doping content is 5 * 10 15Cm -3The Si sheet, crystal face is (100), and oxidation is carried out on its surface, oxidated layer thickness is 1 μ m, as the basis material on upper strata, and in this basis material, injects hydrogen;
(1b) choosing N type doping content is 5 * 10 15Cm -3The Si sheet, crystal face is (110), and oxidation is carried out on its surface, oxidated layer thickness is 1 μ m, as the basis material of lower floor's active layer;
(1c) adopt chemico-mechanical polishing (CMP) technology, respectively the upper strata substrate material surface behind lower floor and the injection hydrogen is carried out polishing;
(1d) lower floor after the polishing and upper strata substrate material surface oxide layer are close to relatively, are placed ultra-high vacuum environment under 480 ℃ of temperature, to realize bonding;
(1e) substrate temperature behind the bonding is raise 100 ℃; Make the upper strata basis material in the hydrogen place fracture of injecting, the part that the upper strata basis material is unnecessary is peeled off, keep the Si material of 200nm; And carry out chemico-mechanical polishing (CMP) at this break surface, form soi structure.
Step 2, the preparation of bipolar device active area.
(2a) growth one layer thickness is the N type epitaxy Si layer of 3 μ m on substrate, and as collector region, this layer doping content is 1 * 10 17Cm -3
(2b) utilize the method for chemical vapor deposition (CVD), at 750 ℃, growth one layer thickness is the SiGe layer of 60nm on substrate, and as the base, this layer Ge component is 25%, and doping content is 5 * 10 19Cm -3
(2c) utilize the method for chemical vapor deposition (CVD), at 750 ℃, growth one layer thickness is the N type Si layer of 200nm on substrate, and as the emitter region, this layer doping content is 5 * 10 17Cm -3
Step 3, the preparation of collector electrode shallow-trench isolation.
(3a) fall surperficial SiO with wet etching 2With the SiN layer;
(3b) utilizing the method for chemical vapor deposition (CVD), at 800 ℃, is the SiO of 300nm at substrate surface deposit one layer thickness 2Layer;
(3c) utilizing the method for chemical vapor deposition (CVD), at 800 ℃, is the SiN layer of 200nm at substrate surface deposit one layer thickness;
(3d) photoetching collector electrode shallow trench isolation areas goes out the shallow slot that the degree of depth is 300nm at the shallow trench isolation areas dry etching;
(3e) utilize chemical vapor deposition (CVD) method,, in shallow slot, fill SiO at 800 ℃ 2, form the collector electrode shallow-trench isolation.
Step 4, the preparation of base stage shallow-trench isolation.
(4a) fall surperficial SiO with wet etching 2With the SiN layer;
(4b) utilizing the method for chemical vapor deposition (CVD), at 800 ℃, is the SiO of 300nm at substrate surface deposit one layer thickness 2Layer;
(4c) utilizing the method for chemical vapor deposition (CVD), at 800 ℃, is the SiN layer of 200nm at substrate surface deposit one layer thickness;
(4d) photoetching base stage shallow trench isolation areas goes out the shallow slot that the degree of depth is 205nm at the shallow trench isolation areas dry etching;
(4e) utilize chemical vapor deposition (CVD) method,, in shallow slot, fill SiO at 800 ℃ 2, form the base stage shallow-trench isolation.
Step 5, SiGe HBT forms.
(5a) fall surperficial SiO with wet etching 2With the SiN layer;
(5b) utilizing the method for chemical vapor deposition (CVD), at 800 ℃, is the SiO of 500nm at substrate surface deposit one layer thickness 2Layer;
(5c) photoetching collector region is carried out N type impurity to this zone and is injected, and making collector electrode contact zone doping content is 1 * 10 20Cm -3, form collector electrode;
(5d) photoetching base region carries out p type impurity to this zone and injects, and making base stage contact zone doping content is 1 * 10 20Cm -3, form base stage;
(5e) to substrate under 1100 ℃ of temperature, annealing 15s carries out impurity activation, forms SiGe HBT;
(5f) utilize the method for chemical vapor deposition (CVD) at substrate surface, at 800 ℃, deposit one SiO 2Layer.
Step 6, the preparation of deep trench isolation district.
Be the SiO of 500nm (6a) at substrate surface thermal oxidation one layer thickness 2Layer;
(6b) the photoetching area of isolation utilizes dry etch process, etches the deep trouth that the degree of depth is 5 μ m in the deep trench isolation zone;
(6c) utilize chemical vapor deposition (CVD) method,, in deep trouth, fill SiO at 800 ℃ 2
(6d) with chemico-mechanical polishing (CMP) method, remove the unnecessary oxide layer in surface, form deep trench isolation.
Step 7, the preparation of PMOS device active region.
(7a) photoetching PMOS device active region at the PMOS device active region, utilizes dry etching, etches the deep trouth that the degree of depth is 5.8 μ m, oxide layer is carved pass through;
(7b) utilizing the method for chemical vapor deposition (CVD), at 750 ℃, is the N type Si resilient coating of 2.5 μ m along (110) crystal face layer thickness of growing in deep trouth, and doping content is 5 * 10 15Cm -3
(7c) utilize the method for chemical vapor deposition (CVD), at 750 ℃, growth one layer thickness is the SiGe of the N type Ge component trapezoidal profile of 2.5 μ m on the Si resilient coating, and bottom Ge component is 0%, and the top is 25%, and doping content is 5 * 10 15Cm -3
(7d) utilize the method for chemical vapor deposition (CVD), at 750 ℃, growth one layer thickness is the P type SiGe layer of 400nm on the SiGe layer of Ge component trapezoidal profile, and the Ge component is 25%, and doping content is 1 * 10 20Cm -3, as the drain region of PMOS device;
(7e) utilize the method for chemical vapor deposition (CVD), at 750 ℃, growth thickness is the P type strain Si layer of 5nm on substrate, and doping content is 5 * 10 18Cm -3, as a P type lightly-doped source drain structure (P-LDD) layer;
(7f) utilize chemical vapor deposition (CVD) method, at 750 ℃, growth one layer thickness is the N type strain Si layer of 45nm on the drain region, and doping content is 5 * 10 17Cm -3, as the raceway groove of PMOS device;
(7g) utilize the method for chemical vapor deposition (CVD), at 750 ℃, growth thickness is the P type strain Si layer of 5nm on substrate, and doping content is 5 * 10 18Cm -3, as the 2nd P type lightly-doped source drain structure (P-LDD) layer;
(7h) utilize chemical vapor deposition (CVD) method, at 750 ℃, growth one layer thickness is the P type SiGe layer of 400nm on strain Si layer, and the Ge component is 25%, and doping content is 1 * 10 20Cm -3, as the source region of PMOS device.
Step 8, the preparation of nmos device active area.
(8a) photoetching nmos device active area at the nmos device active area, utilizes dry etching, etches the deep trouth that the degree of depth is 2.8 μ m;
(8b) utilizing the method for chemical vapor deposition (CVD), at 750 ℃, is the P type Si resilient coating of 400nm at nmos device active area (100) the crystal face layer thickness of growing, and doping content is 5 * 10 15Cm -3
(8c) utilize the method for chemical vapor deposition (CVD), at 750 ℃, growth one layer thickness is the SiGe of the P type Ge component trapezoidal profile of 2 μ m on the Si resilient coating, and bottom Ge component is 0%, and the top is 25%, and doping content is 5 * 10 15Cm -3
(8d) utilize the method for chemical vapor deposition (CVD), at 750 ℃, growth one layer thickness is the P type SiGe layer of 400nm on the SiGe layer of Ge component trapezoidal profile, and the Ge component is 25%, and doping content is 5 * 10 16Cm -3
(8e) utilize chemical vapor deposition (CVD) method, at 750 ℃, regrowth one layer thickness is the P type strain Si layer of 20nm, and doping content is 5 * 10 17Cm -3, as the raceway groove of nmos device.
Step 9, PMOS device are leaked the bonding pad preparation.
(9a) utilize chemical vapor deposition (CVD) method, at 800 ℃, at substrate surface consecutive deposition one deck SiO 2And layer of sin;
(9b) etch the PMOS device and leak trench openings, utilize dry etch process, etching the degree of depth at PMOS device drain region is that 0.7 μ m leaks groove;
(9c) utilize chemical vapor deposition (CVD) method, at 800 ℃, at substrate surface deposit one deck SiO 2, utilize dry etching to remove the SiO on plane 2Layer only keeps the PMOS device and leaks trenched side-wall SiO 2Layer forms the PMOS device and leaks the trenched side-wall isolation;
(9d) utilizing chemical vapor deposition (CVD) method, at 800 ℃, is 5 * 10 in substrate surface deposit doping content 20Cm -3P type Poly-Si, the PMOS device is leaked groove fills up, get rid of the PMOS device again and leak the Poly-Si beyond the flute surfaces, form and leak the bonding pad.
Step 10, the preparation of PMOS device grid bonding pad.
(10a) utilize dry etch process, etching the degree of depth in PMOS device drain-gate zone is 0.9 μ m gate groove;
(10b) utilizing atomic layer chemical vapour deposition (ALCVD) method, at 400 ℃, is the HfO of the high-k of 10nm at the substrate surface deposition thickness 2Layer is as PMOS device gate dielectric layer;
(10c) utilizing chemical vapor deposition (CVD) method, at 800 ℃, is 5 * 10 in substrate surface deposit doping content 20Cm -3P type Poly-SiGe, the Ge component is 30%, and PMOS device gate groove is filled up, and gets rid of Poly-SiGe and SiO beyond the PMOS device gate groove surface again 2Layer forms the PMOS device as the grid region.
Step 11, the nmos device preparation.
(11a) etching the nmos device active area, utilize atomic layer chemical vapour deposition (ALCVD) method, at 400 ℃, is the HfO of the high-k of 10nm at the substrate surface deposition thickness 2Layer is as the nmos device gate dielectric layer;
(11b) utilize chemical vapor deposition (CVD) method, at 800 ℃, deposit one deck intrinsic Poly-SiGe on gate dielectric layer, thickness is 300nm, the Ge component is 30%;
(11c) etching Poly-SiGe, HfO 2Layer forms grid;
(11d) photoetching nmos device active area carries out N type ion to nmos device and injects, and forming doping content is 5 * 10 18Cm -3N type lightly-doped source drain structure (N-LDD);
(11e) utilize chemical vapor deposition (CVD) method, at 800 ℃, deposit one thickness is the SiO of 5nm on entire substrate 2Layer, dry etching falls this layer SiO 2, keep the nmos device gate lateral wall, form the nmos device grid;
(11f) carry out N type phosphonium ion at the nmos device active area and inject, autoregistration generates the source region and the drain region of nmos device, makes source region and drain region doping content reach 5 * 10 20Cm -3, form nmos device.
Step 12 constitutes the BiCMOS integrated circuit.
(12a) photoetching lead-in wire window;
(12b) sputter layer of metal titanium (Ti) on entire substrate, alloy, autoregistration forms metal silicide, and the metal that clean surface is unnecessary forms Metal Contact;
(12c) splash-proofing sputtering metal; The photoetching lead-in wire; Form leakage, source, the gate electrode of source, grid, drain electrode and the PMOS device of nmos device respectively; Bipolar transistor emitter, base stage, collector electrode metal lead-in wire, finally constituting conducting channel is strain BiCMOS integrated device and the circuit based on crystal face selection of 45nm.
Strain BiCMOS integrated device and preparation method based on crystal face selection that the embodiment of the invention provides have following advantage:
1. the strain BiCMOS integrated device based on crystal face selection of the present invention's preparation has adopted mixing crystal face substrate technology; Promptly on same substrate slice, be distributed with (100) and (110) these two kinds of crystal faces; On (110) crystal face, be compressive strain for strain Si PMOS device; The mobility in its hole is higher than body Si material, and on (100) crystal face, is tensile strain for strain Si nmos device, and the mobility of its electronics also is higher than body Si material; Therefore, electric properties such as this device frequency and current driving ability are higher than unidimensional body Si cmos device;
2. the strain BiCMOS integrated device based on crystal face selection of the present invention preparation; Employing selective epitaxial technology; At nmos device and PMOS device active region selective growth strain Si material, the flexibility that has improved designs has strengthened BiCMOS device and integrated circuit electric property respectively;
3. in the mixing crystal face strain BiCMOS integrated device technology of the present invention's preparation based on three polycrystal SiGe HBT; Adopt the Poly-SiGe material as grid; Its work function changes with the variation of Ge component, and through regulating Ge component in the Poly-SiGe grid, realization CMOS threshold voltage can be adjusted continuously; Reduce processing step, reduced technology difficulty;
4. the maximum temperature that relates in the strain BiCMOS integrated device process based on crystal face selection of the present invention's preparation is 800 ℃; Be lower than the technological temperature that causes strained Si channel stress relaxation; Therefore this preparation method can keep strained Si channel stress effectively, improves the performance of integrated circuit;
5. the raceway groove based on PMOS device in the strain BiCMOS integrated device of crystal face selection of the present invention's preparation is back type; Promptly grid can be controlled raceway groove on four sides in groove; Therefore, this device has increased the width of raceway groove in limited zone, thereby has improved the current driving ability of device; Increase the integrated level of integrated circuit, reduced the manufacturing cost of lsi unit area;
6. in the strain BiCMOS integrated device based on crystal face selection of the present invention's preparation, in the MOS device architecture,, introduce lightly-doped source and leak (LDD) technology, improved device performance in order effectively to suppress short-channel effect;
7. in the strain BiCMOS integrated device spare structure based on crystal face selection of the present invention's preparation, adopted the HfO of high K value 2As gate medium, improved the grid-control ability of device, strengthened the electric property of device.
The above is merely preferred embodiment of the present invention, not in order to restriction the present invention, all any modifications of within spirit of the present invention and principle, being done, is equal to and replaces and improvement etc., all should be included within protection scope of the present invention.

Claims (11)

1. the strain BiCMOS integrated device based on crystal face selection is characterized in that, nmos device and PMOS device are strain Si MOS device, and bipolar device is SiGe HBT.
2. the strain BiCMOS integrated device based on crystal face selection according to claim 1 is characterized in that the conducting channel of nmos device is a strain Si material, and the conducting channel of nmos device is a tensile strain Si material, and the conducting channel of nmos device is a planar channeling.
3. the strain BiCMOS integrated device based on crystal face selection according to claim 1 is characterized in that the conducting channel of PMOS device is a strain Si material, and the conducting channel of PMOS device is a compressive strain Si material, and the conducting channel of PMOS device is a vertical-channel.
4. the strain BiCMOS integrated device based on crystal face selection according to claim 1 is characterized in that, nmos device is prepared in crystal face on the SOI substrate of (100), and the PMOS device is prepared in crystal face on the substrate of (110).
5. the strain BiCMOS integrated device based on crystal face selection according to claim 1 is characterized in that the base of SiGe HBT device is the strain SiGe material.
6. the strain BiCMOS integrated device based on crystal face selection according to claim 1 is characterized in that SiGe HBT device is a planar structure.
7. the preparation method based on the strain BiCMOS integrated device of crystal face selection is characterized in that, comprises the steps:
The first step, choose the Si sheet that two N types mix, wherein a slice crystal face is (110), and a slice crystal face is (100), and two doping contents are 1 ~ 5 * 10 15Cm -3, oxidation is carried out on two Si sheet surfaces, oxidated layer thickness is 0.5 ~ 1 μ m; With crystal face is the basis material of a slice of (100) as the upper strata, and in this basis material, injects hydrogen, is the basis material of a slice of (110) as lower floor with crystal face; Adopt chemico-mechanical polishing (CMP) technology that two oxide layer surfaces are polished;
Second goes on foot, two Si sheet oxide layers is opposite in the ultra-high vacuum environment mutually under 350～480 ℃ temperature, realizes bonding; Si sheet temperature behind the bonding is raise 100～200 ℃; Make the upper strata basis material in the hydrogen place fracture of injecting, the part that the upper strata basis material is unnecessary is peeled off, keep the Si material of 100 ~ 200nm; And carry out chemico-mechanical polishing (CMP) at its break surface, form the SOI substrate;
The 3rd step, utilizing the method for chemical vapor deposition (CVD), at 600～750 ℃, is the N type Si epitaxial loayer of 2～3 μ m at the substrate layer thickness of growing, and as collector region, this layer doping content is 1 * 10 16～1 * 10 17Cm -3
The 4th goes on foot, utilizes the method for chemical vapor deposition (CVD), and at 600～750 ℃, growth one layer thickness is the SiGe layer of 20 ~ 60nm on substrate, and as the base, this layer Ge component is 15 ~ 25%, and doping content is 5 * 10 18~ 5 * 10 19Cm -3
The 5th goes on foot, utilizes the method for chemical vapor deposition (CVD), and at 600～750 ℃, growth one layer thickness is the N type Si layer of 100～200nm on substrate, and as the emitter region, this layer doping content is 1 * 10 17～5 * 10 17Cm -3
The 6th goes on foot, falls with wet etching the SiO on surface 2With the SiN layer, utilize the method for chemical vapor deposition (CVD), at 600～800 ℃, be the SiO of 200 ~ 300nm at substrate surface deposit one layer thickness 2A layer and a layer thickness are the SiN layer of 100 ~ 200nm; Photoetching collector region shallow trench isolation areas goes out the shallow slot that the degree of depth is 180 ~ 300nm at the shallow trench isolation areas dry etching, utilizes chemical vapor deposition (CVD) method, at 600～800 ℃, in shallow slot, fills SiO 2
The 7th goes on foot, falls with wet etching the SiO on surface 2With the SiN layer, utilize the method for chemical vapor deposition (CVD), at 600～800 ℃, be the SiO of 200 ~ 300nm at substrate surface deposit one layer thickness 2A layer and a layer thickness are the SiN layer of 100 ~ 200nm; Photoetching base shallow trench isolation areas goes out the shallow slot that the degree of depth is 105 ~ 205nm at the shallow trench isolation areas dry etching, utilizes chemical vapor deposition (CVD) method, at 600～800 ℃, in shallow slot, fills SiO 2
The 8th goes on foot, falls with wet etching the SiO on surface 2With the SiN layer, utilize the method for chemical vapor deposition (CVD), at 600～800 ℃, be the SiO of 300 ~ 500nm at substrate surface deposit one layer thickness 2Layer; The photoetching collector region is carried out N type impurity to this zone and is injected, and making collector electrode contact zone doping content is 1 * 10 19～1 * 10 20Cm -3, form collector contact area;
The 9th step, photoetching base region carry out p type impurity to this zone and inject, and making base stage contact zone doping content is 1 * 10 19～1 * 10 20Cm -3, form the base stage contact area, and to substrate under 950～1100 ℃ of temperature, annealing 15～120s carries out impurity activation, forms SiGe HBT; Utilize the method for chemical vapor deposition (CVD) at substrate surface, at 600～800 ℃, deposit one SiO 2Layer;
The tenth step, be the SiO of 300～500nm at substrate surface thermal oxidation one layer thickness 2Layer, the photoetching area of isolation utilizes dry etch process, etches the deep trouth that the degree of depth is 3 ~ 5 μ m in the deep trench isolation zone; Utilize the method for chemical vapor deposition (CVD),, in deep trouth, fill SiO at 600～800 ℃ 2, with chemico-mechanical polishing (CMP) method, remove the unnecessary oxide layer in surface, form deep trench isolation;
The 11 step, photoetching PMOS device active region at the PMOS device active region, utilize dry etching, etch the deep trouth that the degree of depth is 3.4～5.8 μ m, the oxide layer of centre is carved pass through; Utilize chemical vapor deposition (CVD) method; At 600～750 ℃, selective epitaxial growth seven layer materials on the PMOS device active region of (110) crystal face substrate: ground floor is a N type Si resilient coating, and thickness is 1.5～2.5 μ m; This layer fills up deep trouth, and doping content is 1～5 * 10 15Cm -3The second layer is that thickness is the N type SiGe graded bedding of 1.5～2.5 μ m, and bottom Ge component is 0%, and top Ge component is 15～25%, and doping content is 1～5 * 10 15Cm -3The 3rd layer is that the Ge component is 15～25%, and thickness is the P type SiGe layer of 200～400nm, and doping content is 5～10 * 10 20Cm -3, as the drain region of PMOS device; The 4th layer is that thickness is 3 ~ 5nmP type strain Si layer, and doping content is 1～5 * 10 18Cm -3, as a P type lightly-doped source drain structure (P-LDD) layer; Layer 5 be thickness be the N type strain Si of 22～45nm as channel region, doping content is 5 * 10 16～5 * 10 17Cm -3Layer 6 is that thickness is the P type strain Si layer of 3 ~ 5nm, and doping content is 1～5 * 10 18Cm -3, as the 2nd P type lightly-doped source drain structure (P-LDD) layer; Layer 7 is that the Ge component is 15～25%, and thickness is the P type SiGe of 200～400nm, and doping content is 5～10 * 10 19Cm -3, as the source region of PMOS device;
The 12 step, photoetching nmos device active area; At the nmos device active area, utilize dry etching, etch the deep trouth that the degree of depth is 1.9～2.8 μ m; Utilize chemical vapor deposition (CVD) method; At 600～750 ℃, selective epitaxial growth four layer materials on the nmos device active area of (100) crystal face substrate: ground floor is that thickness is the P type Si resilient coating of 200～400nm, and doping content is 1～5 * 10 15Cm -3The second layer is that thickness is the P type SiGe graded bedding of 1.5～2 μ m, and bottom Ge component is 0%, and top Ge component is 15～25%, and doping content is 1～5 * 10 15Cm -3The 3rd layer is that the Ge component is 15～25%, and thickness is the P type SiGe layer of 200～400nm, and doping content is 1～5 * 10 16Cm -3The 4th layer is that thickness is the N type strain Si layer of 15～20nm, and doping content is 5 * 10 16～5 * 10 17Cm -3, as the raceway groove of nmos device;
The 13 the step, utilize chemical vapor deposition (CVD) method at substrate surface, at 600～800 ℃, deposit one deck SiO 2Resilient coating and layer of sin etch leakage trench openings, utilize dry etch process, and etching the degree of depth at PMOS device drain region is that 0.3～0.7 μ m leaks groove; Utilize chemical vapor deposition (CVD) method, at 600～800 ℃, at substrate surface deposit one deck SiO 2, form the PMOS device and leak the trenched side-wall isolation; Utilize dry etching to remove the SiO on plane 2Layer only keeps the PMOS device and leaks trenched side-wall SiO 2Layer; Utilizing chemical vapor deposition (CVD) method, at 600～800 ℃, is 1～5 * 10 in substrate surface deposit doping content 20Cm -3P type Poly-Si, the PMOS device is leaked groove fills up, get rid of the PMOS device again and leak the Poly-SiGe beyond the flute surfaces, form and leak the bonding pad;
The 14 the step, utilize dry etch process, etching the degree of depth in PMOS device gate region is 0.5～0.9 μ m gate groove; Utilizing atomic layer chemical vapour deposition (ALCVD) method, at 300～400 ℃, is the HfO of the high-k of 6～10nm at the substrate surface deposition thickness 2Layer is as PMOS device gate dielectric layer; Utilizing chemical vapor deposition (CVD) method, at 600～800 ℃, is 1～5 * 10 in substrate surface deposit doping content 20Cm -3P type Poly-SiGe, the Ge component is 10～30%, and PMOS device gate groove is filled up, and gets rid of Poly-SiGe and SiO beyond the PMOS device gate groove surface again 2Layer forms the PMOS device as the grid region;
The 15 the step, etch the nmos device active area, utilize atomic layer chemical vapour deposition (ALCVD) method, at 300～400 ℃, be the HfO of the high-k of 6～10nm at the substrate surface deposition thickness 2Layer is as the nmos device gate dielectric layer; Deposit one deck intrinsic Poly-SiGe again, thickness is 100～300nm, the Ge component is 10～30%, etching N MOS device grids; Photoetching nmos device active area carries out N type ion to nmos device and injects, and forming doping content is 1～5 * 10 18Cm -3N type lightly-doped source drain structure (N-LDD); At entire substrate deposit one thickness is the SiO of 3～5nm 2Layer, dry etching falls this layer SiO 2,, form the nmos device grid as the nmos device grid curb wall;
The 16 step, carry out N type phosphonium ion at the nmos device active area and inject, autoregistration generates the source region and the drain region of nmos device, makes source region and drain region doping content reach 1～5 * 10 20Cm -3
The 17 goes on foot, makes by lithography source, leakage and the grid lead window of PMOS device, sputter layer of metal titanium (Ti) on entire substrate, and alloy, autoregistration forms metal silicide, and the metal that clean surface is unnecessary forms Metal Contact; With chemical vapor deposition (CVD) method, at 600～800 ℃, SiO grows on substrate 2Layer, photoetching lead-in wire window, splash-proofing sputtering metal, the photoetching lead-in wire, constituting conducting channel is the mixing crystal face strain BiCMOS integrated device based on three polycrystal SiGe HBT of 22～45nm.
8. preparation method according to claim 7 is characterized in that, the PMOS device channel length according to the N type strain Si of the 11 step deposit layer by layer thickness confirm that get 22～45nm, the nmos device channel length is controlled by photoetching process.
9. preparation method according to claim 7 is characterized in that, related maximum temperature is according to the 4th chemical vapor deposition (CVD) the technological temperature decision that go on foot in the 17 step among this preparation method, and maximum temperature is smaller or equal to 800 ℃.
10. preparation method according to claim 7 is characterized in that, base thickness decides according to the epitaxy layer thickness of the 4th step SiGe, gets 20～60nm.
11. the preparation method based on the strain BiCMOS integrated circuit of crystal face selection is characterized in that, comprises the steps:
Step 1, the implementation method of SOI backing material preparation is:
(1a) choosing N type doping content is 1 * 10 15Cm -3The Si sheet, crystal face is (100), and oxidation is carried out on its surface, oxidated layer thickness is 0.5 μ m, as the upper strata basis material, and in this basis material, injects hydrogen;
(1b) choosing N type doping content is 1 * 10 15Cm -3The Si sheet, crystal face is (110), and oxidation is carried out on its surface, oxidated layer thickness is 0.5 μ m, as lower floor's basis material;
(1c) adopt chemico-mechanical polishing (CMP) technology, respectively the upper strata substrate material surface behind lower floor and the injection hydrogen is carried out polishing;
(1d) lower floor after the polishing and upper strata substrate material surface oxide layer are close to relatively, are placed ultra-high vacuum environment under 350 ℃ of temperature, to realize bonding;
(1e) substrate temperature behind the bonding is raise 200 ℃; Make the upper strata basis material in the hydrogen place fracture of injecting, the part that the upper strata basis material is unnecessary is peeled off, keep the Si material of 100nm; And carry out chemico-mechanical polishing (CMP) at this break surface, form soi structure;
Step 2, the implementation method of bipolar device active area preparation is:
(2a) growth one layer thickness is the N type epitaxy Si layer of 2 μ m on substrate, and as collector region, this layer doping content is 1 * 10 16Cm -3
(2b) utilize the method for chemical vapor deposition (CVD), at 600 ℃, growth one layer thickness is the SiGe layer of 20nm on substrate, and as the base, this layer Ge component is 15%, and doping content is 5 * 10 18Cm -3
(2c) utilize the method for chemical vapor deposition (CVD), at 600 ℃, growth one layer thickness is the N type Si layer of 100nm on substrate, and as the emitter region, this layer doping content is 1 * 10 17Cm -3
Step 3, the implementation method of collector electrode shallow-trench isolation preparation is:
(5a) fall surperficial SiO with wet etching 2With the SiN layer;
(3b) utilizing the method for chemical vapor deposition (CVD), at 600 ℃, is the SiO of 200nm at substrate surface deposit one layer thickness 2Layer;
(3c) utilizing the method for chemical vapor deposition (CVD), at 600 ℃, is the SiN layer of 100nm at substrate surface deposit one layer thickness;
(3d) photoetching collector electrode shallow trench isolation areas goes out the shallow slot that the degree of depth is 180nm at the shallow trench isolation areas dry etching;
(3e) utilize chemical vapor deposition (CVD) method,, in shallow slot, fill SiO at 600 ℃ 2, form the collector electrode shallow-trench isolation;
Step 4, the implementation method of base stage shallow-trench isolation preparation is:
(4a) fall surperficial SiO with wet etching 2With the SiN layer;
(4b) utilizing the method for chemical vapor deposition (CVD), at 600 ℃, is the SiO of 200nm at substrate surface deposit one layer thickness 2Layer;
(4c) utilizing the method for chemical vapor deposition (CVD), at 600 ℃, is the SiN layer of 100nm at substrate surface deposit one layer thickness;
(4d) photoetching base stage shallow trench isolation areas goes out the shallow slot that the degree of depth is 105nm at the shallow trench isolation areas dry etching;
(4e) utilize chemical vapor deposition (CVD) method,, in shallow slot, fill SiO at 600 ℃ 2, form the base stage shallow-trench isolation;
Step 5, the implementation method that SiGe HBT forms is:
(5a) fall surperficial SiO with wet etching 2With the SiN layer;
(5b) utilizing the method for chemical vapor deposition (CVD), at 600 ℃, is the SiO of 300nm at substrate surface deposit one layer thickness 2Layer;
(5c) photoetching collector region is carried out N type impurity to this zone and is injected, and making collector electrode contact zone doping content is 1 * 10 19Cm -3, form collector electrode;
(5d) photoetching base region carries out p type impurity to this zone and injects, and making base stage contact zone doping content is 1 * 10 19Cm -3, form base stage;
(5e) to substrate under 950 ℃ of temperature, annealing 120s carries out impurity activation, forms SiGe HBT;
(5f) utilize the method for chemical vapor deposition (CVD) at substrate surface, at 600 ℃, deposit one SiO 2Layer;
Step 6, the implementation method of deep trench isolation district preparation is:
Be the SiO of 300nm (6a) at substrate surface thermal oxidation one layer thickness 2Layer;
(6b) the photoetching area of isolation utilizes dry etch process, etches the deep trouth that the degree of depth is 3 μ m in the deep trench isolation zone;
(6c) utilize chemical vapor deposition (CVD) method,, in deep trouth, fill SiO at 600 ℃ 2
(6d) with chemico-mechanical polishing (CMP) method, remove the unnecessary oxide layer in surface, form deep trench isolation;
Step 7, the implementation method of PMOS device active region preparation is:
(7a) photoetching PMOS device active region at the PMOS device active region, utilizes dry etching, etches the deep trouth that the degree of depth is 3.4 μ m, oxide layer is carved pass through;
(7b) utilizing the method for chemical vapor deposition (CVD), at 600 ℃, is the N type Si resilient coating of 1.5 μ m along (110) crystal face layer thickness of growing in deep trouth, and doping content is 1 * 10 15Cm -3
(7c) utilize the method for chemical vapor deposition (CVD), at 600 ℃, growth one layer thickness is the SiGe of the N type Ge component trapezoidal profile of 1.5 μ m on the Si resilient coating, and bottom Ge component is 0%, and the top is 15%, and doping content is 1 * 10 15Cm -3
(7d) utilize the method for chemical vapor deposition (CVD), at 600 ℃, growth one layer thickness is the P type SiGe layer of 200nm on the SiGe layer of Ge component trapezoidal profile, and the Ge component is 15%, and doping content is 5 * 10 19Cm -3, as the drain region of PMOS device;
(7e) utilize the method for chemical vapor deposition (CVD), at 600 ℃, growth thickness is the P type strain Si layer of 3nm on substrate, and doping content is 1 * 10 18Cm -3, as a P type lightly-doped source drain structure (P-LDD) layer;
(7f) utilize chemical vapor deposition (CVD) method, at 600 ℃, growth one layer thickness is the N type strain Si layer of 22nm on the drain region, and doping content is 5 * 10 16Cm -3, as the raceway groove of PMOS device;
(7g) utilize the method for chemical vapor deposition (CVD), at 600 ℃, growth thickness is the P type strain Si layer of 3nm on substrate, and doping content is 1 * 10 18Cm -3, as the 2nd P type lightly-doped source drain structure (P-LDD) layer;
(7h) utilize chemical vapor deposition (CVD) method, at 600 ℃, growth one layer thickness is the P type SiGe layer of 200nm on strain Si layer, and the Ge component is 15%, and doping content is 5 * 10 19Cm -3, as the source region of PMOS device;
Step 8, the implementation method of nmos device active area preparation is:
(8a) photoetching nmos device active area at the nmos device active area, utilizes dry etching, etches the deep trouth that the degree of depth is 1.9 μ m;
(8b) utilizing the method for chemical vapor deposition (CVD), at 600 ℃, is the P type Si resilient coating of 200nm at nmos device active area (100) the crystal face layer thickness of growing, and doping content is 1 * 10 15Cm -3
(8c) utilize the method for chemical vapor deposition (CVD), at 600 ℃, growth one layer thickness is the SiGe of the P type Ge component trapezoidal profile of 1.5 μ m on the Si resilient coating, and bottom Ge component is 0%, and the top is 15%, and doping content is 1 * 10 15Cm -3
(8d) utilize the method for chemical vapor deposition (CVD), at 600 ℃, growth one layer thickness is the P type SiGe layer of 200nm on the SiGe layer of Ge component trapezoidal profile, and the Ge component is 15%, and doping content is 1 * 10 16Cm -3
(8e) utilize chemical vapor deposition (CVD) method, at 600 ℃, regrowth one layer thickness is the P type strain Si layer of 15nm, and doping content is 5 * 10 16Cm -3, as the raceway groove of nmos device;
The implementation method that step 9, PMOS device are leaked the bonding pad preparation is:
(9a) utilize chemical vapor deposition (CVD) method, at 600 ℃, at substrate surface consecutive deposition one deck SiO 2And layer of sin;
(9b) etch the PMOS device and leak trench openings, utilize dry etch process, etching the degree of depth at PMOS device drain region is that 0.3 μ m leaks groove;
(9c) utilize chemical vapor deposition (CVD) method, at 600 ℃, at substrate surface deposit one deck SiO 2, utilize dry etching to remove the SiO on plane 2Layer only keeps the PMOS device and leaks trenched side-wall SiO 2Layer forms the PMOS device and leaks the trenched side-wall isolation;
(9d) utilizing chemical vapor deposition (CVD) method, at 600 ℃, is 1 * 10 in substrate surface deposit doping content 20Cm -3P type Poly-Si, the PMOS device is leaked groove fills up, get rid of the PMOS device again and leak the Poly-Si beyond the flute surfaces, form and leak the bonding pad;
Step 10, the implementation method of PMOS grid bonding pad preparation is:
(10a) utilize dry etch process, etching the degree of depth in PMOS device drain-gate zone is 0.5 μ m gate groove;
(10b) utilizing atomic layer chemical vapour deposition (ALCVD) method, at 300 ℃, is the HfO of the high-k of 6nm at the substrate surface deposition thickness 2Layer is as PMOS device gate dielectric layer;
(10c) utilizing chemical vapor deposition (CVD) method, at 600 ℃, is 1 * 10 in substrate surface deposit doping content 20Cm -3P type Poly-SiGe, the Ge component is 10%, and PMOS device gate groove is filled up, and gets rid of Poly-SiGe and SiO beyond the PMOS device gate groove surface again 2Layer forms the PMOS device as the grid region;
Step 11, the implementation method of nmos device preparation is:
(11a) etching the nmos device active area, utilize atomic layer chemical vapour deposition (ALCVD) method, at 300 ℃, is the HfO of the high-k of 6nm at the substrate surface deposition thickness 2Layer is as the nmos device gate dielectric layer;
(11b) utilize chemical vapor deposition (CVD) method, at 600 ℃, deposit one deck Poly-SiGe on gate dielectric layer, thickness is 100nm, the Ge component is 10%;
(11c) etching Poly-SiGe, HfO 2Layer forms grid;
(11d) photoetching nmos device active area carries out N type ion to nmos device and injects, and forming doping content is 1 * 10 18Cm -3N type lightly-doped source drain structure (N-LDD);
(11e) utilize chemical vapor deposition (CVD) method, at 600 ℃, deposit one thickness is the SiO of 3nm on entire substrate 2Layer, dry etching falls this layer SiO 2, keep the nmos device grid curb wall, form the nmos device grid;
(11f) carry out N type phosphonium ion at the nmos device active area and inject, autoregistration generates the source region and the drain region of nmos device, makes source region and drain region doping content reach 1 * 10 20Cm -3, form nmos device;
Step 12, the implementation method that constitutes the preparation of BiCMOS integrated circuit is:
(12a) photoetching lead-in wire window;
(12b) sputter layer of metal titanium (Ti) on entire substrate, alloy, autoregistration forms metal silicide, and the metal that clean surface is unnecessary forms Metal Contact;
(12c) splash-proofing sputtering metal; The photoetching lead-in wire; Form leakage, source, the gate electrode of source, grid, drain electrode and the PMOS device of nmos device respectively; Bipolar transistor emitter, base stage, collector electrode metal lead-in wire, finally constituting the CMOS conducting channel is strain BiCMOS integrated device and the circuit based on crystal face selection of 22nm.
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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020142558A1 (en) * 2001-03-29 2002-10-03 Hsu Sheng Teng Self-aligned SiGe HBT BiCMOS on SOI substrate and method of fabricating the same
CN1848431A (en) * 2005-02-01 2006-10-18 国际商业机器公司 Semiconductor device and method of manufacturing same
CN102064190A (en) * 2009-11-18 2011-05-18 上海华虹Nec电子有限公司 SiGe PNP bipolar transistor in SiGe BiCMOS (Bipolar Complementary Metal Oxide Semiconductor) technique

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020142558A1 (en) * 2001-03-29 2002-10-03 Hsu Sheng Teng Self-aligned SiGe HBT BiCMOS on SOI substrate and method of fabricating the same
CN1848431A (en) * 2005-02-01 2006-10-18 国际商业机器公司 Semiconductor device and method of manufacturing same
CN102064190A (en) * 2009-11-18 2011-05-18 上海华虹Nec电子有限公司 SiGe PNP bipolar transistor in SiGe BiCMOS (Bipolar Complementary Metal Oxide Semiconductor) technique

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
李磊: "应变BiCMOS器件及应力分布研究", 《中国优秀硕士学位论文全文数据库》, 31 January 2010 (2010-01-31) *
颜哲: "应变CMOS器件结构模型研究", 《中国优秀硕士学位论文全文数据库》, 31 January 2010 (2010-01-31) *

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