CN102820296A - Double poly-crystal SOI (Silicon On Insulator) BiCMOS integrated device based on crystal plane selection and preparation method - Google Patents

Double poly-crystal SOI (Silicon On Insulator) BiCMOS integrated device based on crystal plane selection and preparation method Download PDF

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CN102820296A
CN102820296A CN2012102445320A CN201210244532A CN102820296A CN 102820296 A CN102820296 A CN 102820296A CN 2012102445320 A CN2012102445320 A CN 2012102445320A CN 201210244532 A CN201210244532 A CN 201210244532A CN 102820296 A CN102820296 A CN 102820296A
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CN102820296B (en
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胡辉勇
张鹤鸣
周春宇
宣荣喜
宋建军
吕懿
舒斌
郝跃
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Xidian University
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Abstract

The invention discloses a double poly-crystal SOI (Silicon On Insulator) BiCMOS integrated device based on crystal plane selection and a preparation method. The preparation method comprises the following steps: preparing a SOI substrate; growing N-Si as a collector region of a bipolar device; photo-etching a base region; growing P-SiGe, i-Si and i-Poly-Si on the area of the base region, thereby forming an emitter, a base and a collector, and forming a SiGe HBT (Heterojunction Bipolar Transistor) device; etching a deep slot on an NMOS (N-channel Metal Oxide Semiconductor) device region, selectively growing a strain Si epitaxial layer and preparing an NMOS device; selectively growing a strain SiGe epitaxial layer on a PMOS (P-channel Metal Oxide Semiconductor) device active region, thereby preparing a PMOS device; and preparing a SOI BiCMOS integrated device and a circuit. According to the preparation method, a SOI BiCMOS integrated circuit with an enhanced property is prepared on the basis of the SOI substrate by fully utilizing the characteristics that the electronic mobility of a Si material is higher than that of a semiconductor Si material, the hole mobility of a compressive strain SiGe material is higher than that of the semiconductor Si material and the mobility ratio is anisotropic.

Description

A kind of two polycrystalline SOI BiCMOS integrated devices and preparation method based on crystal face selection
Technical field
The invention belongs to the semiconductor integrated circuit technical field, relate in particular to a kind of two polycrystalline SOI BiCMOS integrated devices and preparation method based on crystal face selection.
Background technology
In the present age of information technology high development, be that the microelectric technique of representative is the key of information technology with the integrated circuit.Integrated circuit as with fastest developing speed on the human history, have the greatest impact, most widely used technology, it has become the important symbol of weighing national science technical merit, overall national strength and a defense force.
Development has an immense impact on to microelectronic industry " Moore's Law " pointed out: the transistor size on the IC chip, increased by 1 times in per approximately 18 months, and performance also promotes 1 times.Over more than 40 year, world's microelectronic industry constantly advances according to this law all the time, and circuit scale has been developed into present ultra-large by initial small-scale.The Si material is with its excellent performance; In microelectronic industry always in occupation of consequence, and the CMOS integrated circuit that is the basis with the Si material with advantages such as low-power consumption, low noise, high input impedance, high integration, good reliability in integrated circuit fields in occupation of leading position.
Along with progressively reducing of device feature size, especially get into after the nanoscale, the development of microelectric technique more and more approaches the limit of material, technology, device, is faced with great challenge.After device feature size narrowed down to 65 nanometers, problems such as the influence of the short channel effect in the MOS device, high-field effect, quantum effect, parasitic parameter, technological parameter fluctuation were more and more outstanding to Effect on Performance such as device leakage electric current, subthreshold characteristic, ON state, off-state currents; And along with the develop rapidly of wireless mobile communications; Performance to device and integrated circuit; Have higher requirement like frequency characteristic, noise characteristic, package area, power consumption and cost etc., the device of traditional silica-based prepared and integrated circuit more and more can't satisfy demand novel, the high-velocity electrons system.
An important performance indexes of CMOS integrated circuit is the driving force of NMOS and PMOS device, and the mobility in electronics and hole is respectively one of key factor of its driving force of decision.For performance that improves nmos device and PMOS device and then the performance that improves the CMOS integrated circuit, two kinds of mobility of charge carrier rates all should be high as much as possible.
As far back as the fifties in last century, just discovered stress application on silicon materials, the mobility in electronics and hole be can change, thereby the NMOS prepared on the semi-conducting material and the performance of PMOS device changed.But electronics is not always made identical reaction to stress of the same race with the hole.Simultaneously, preparation nmos device and PMOS device on identical crystal face, it is optimum that their mobility can not reach simultaneously.
SOI (Silicon-On-Insulator, the silicon on the dielectric substrate) technology is to have introduced one deck between at the bottom of top layer silicon and the backing to bury oxide layer.Through on insulator, forming semiconductive thin film, the SOI material had body silicon incomparable advantage; Realize the dielectric isolation of components and parts in the integrated circuit, thoroughly eliminated the parasitic latch-up in the body silicon CMOS circuit; The integrated circuit that adopts this material to process has also that parasitic capacitance is little, integration density is high, speed is fast, technology is simple, short-channel effect is little and is specially adapted to advantage such as low-voltage and low-power dissipation circuit, therefore we can say that SOI might become the low pressure of deep-submicron, the mainstream technology of low power consumption integrated circuit.In addition, the SOI material also is used to make mems optical switch, as utilizes body silicon Machining Technology.
Because Si material carrier material transition rate is lower, so the performance of integrated circuits, the especially frequency performance that adopt Si BiCMOS technology to make have received great restriction; And for SiGe BiCMOS technology, though bipolar transistor has adopted SiGe HBT, the unipolar device that promotes for restriction BiCMOS integrated circuit frequency characteristic still adopts Si CMOS, further promotes so these all limit BiCMOS performance of integrated circuits ground.
Summary of the invention
The object of the present invention is to provide a kind of two polycrystalline SOI BiCMOS integrated devices and preparation method based on crystal face selection; To realize utilizing tensile strain Si material electronics mobility to be higher than body Si material and compressive strain SiGe material hole mobility is higher than body Si material and the anisotropic characteristics of mobility; Based on the SOI substrate, prepare two polycrystalline SOI BiCMOS integrated devices and circuit preparation method that performance strengthens based on crystal face selection.
The object of the present invention is to provide a kind of two polycrystalline SOI BiCMOS integrated devices and circuit based on crystal face selection, nmos device is a strain Si planar channeling device, and the PMOS device is a strain SiGe planar channeling device, and bipolar device is two polycrystalline SOI SiGe HBT.
Further, the conducting channel of nmos device is tensile strain Si material, the conducting channel of nmos device is a planar channeling.
Further, the conducting channel of PMOS device is compressive strain SiGe material, the conducting channel of PMOS device is a planar channeling.
Further, nmos device is different with the crystal face of PMOS device, wherein the crystal face of nmos device is (100), the crystal face of PMOS device is (110).
Further, SiGe HBT device adopts the SOI substrate.
Further, the emitter of SiGe HBT device adopts polysilicon to contact with base stage.
Further, the base of SiGe HBT device is the strain SiGe material.
Another object of the present invention is to provide a kind of preparation method of the two polycrystalline SOI BiCMOS integrated devices based on crystal face selection, comprise the steps:
The first step, choose two Si sheets, one is that N type doping content is 1～5 * 10 15Cm -3Si (110) substrate slice, as the upper strata basis material, another piece is that P type doping content is 1～5 * 10 15Cm -3Si (100) substrate slice, as lower floor's basis material, oxidation is carried out on two Si sheet surfaces, oxidated layer thickness is 0.5 ~ 1 μ m, adopts chemico-mechanical polishing (CMP) technology that two oxide layer surfaces are polished;
Second step, to injecting hydrogen in the basis material of upper strata, and two Si sheet oxide layers be opposite in the ultra-high vacuum environment mutually under 350～480 ℃ temperature, realize bonding; Si sheet temperature behind the bonding is raise 100～200 ℃; Make the upper strata basis material in the hydrogen place fracture of injecting, the part that the upper strata basis material is unnecessary is peeled off, keep the Si material of 100 ~ 200nm; And carry out chemico-mechanical polishing (CMP) at its break surface, form the SOI substrate;
The 3rd goes on foot, utilizes the method for chemical vapor deposition (CVD), at 600～750 ℃, and growth Si epitaxial loayer on substrate, thickness is 250～300nm, and the N type mixes, and doping content is 1 * 10 16～1 * 10 17Cm -3, as collector region;
The 4th goes on foot, utilizes the method for chemical vapor deposition (CVD), at 600～800 ℃, is the SiO of 200 ~ 300nm at substrate surface deposit one layer thickness 2A layer and a layer thickness are the SiN layer of 100 ~ 200nm; The photoetching base utilizes dry etching, etches the degree of depth and be the zone, base of 200nm, and at substrate surface growth trilaminate material: ground floor is the SiGe layer, and the Ge component is 15 ~ 25%, and thickness is 20 ~ 60nm, and the P type mixes, and doping content is 5 * 10 18~ 5 * 10 19Cm -3, as the base; The second layer is unadulterated intrinsic Si layer, and thickness is 10 ~ 20nm; The 3rd layer is unadulterated intrinsic Poly-Si layer, and thickness is 200～300nm, as base stage and emitter region;
The 5th goes on foot, utilizes the method for chemical vapor deposition (CVD), at 600～800 ℃, is the SiO of 200 ~ 300nm at substrate surface deposit one layer thickness 2A layer and a layer thickness are the SiN layer of 100 ~ 200nm; Deep trench isolation zone between lithographic device, dry etching goes out the deep trouth that the degree of depth is 5 μ m in the deep trench isolation zone, utilizes chemical vapor deposition (CVD) method, at 600～800 ℃, in deep trouth, fills SiO 2
The 6th goes on foot, falls with wet etching the SiO on surface 2With the SiN layer, utilize the method for chemical vapor deposition (CVD) again, at 600～800 ℃, be the SiO of 200 ~ 300nm at substrate surface deposit one layer thickness 2A layer and a layer thickness are the SiN layer of 100 ~ 200nm; Photoetching collector region shallow trench isolation areas goes out the shallow slot that the degree of depth is 180 ~ 300nm at the shallow trench isolation areas dry etching, utilizes chemical vapor deposition (CVD) method, at 600～800 ℃, in shallow slot, fills SiO 2
The 7th goes on foot, falls with wet etching the SiO on surface 2With the SiN layer, utilize the method for chemical vapor deposition (CVD) again, at 600～800 ℃, be the SiO of 200 ~ 300nm at substrate surface deposit one layer thickness 2A layer and a layer thickness are the SiN layer of 100 ~ 200nm; Photoetching base shallow trench isolation areas goes out the shallow slot that the degree of depth is 215 ~ 325nm at the shallow trench isolation areas dry etching, utilizes chemical vapor deposition (CVD) method, at 600～800 ℃, in shallow slot, fills SiO 2
The 8th goes on foot, falls with wet etching the SiO on surface 2With the SiN layer, utilize the method for chemical vapor deposition (CVD), at 600～800 ℃, be the SiO of 300 ~ 500nm at substrate surface deposit one layer thickness 2Layer; The photoetching base region carries out p type impurity to this zone and injects, and making base stage contact zone doping content is 1 * 10 19～1 * 10 20Cm -3, form the base stage contact area;
The 9th step, photoetching emitting area carry out N type impurity to this zone and inject, and making doping content is 1 * 10 17～5 * 10 17Cm -3, form the emitter region;
The tenth step, photoetching collector region, and utilize the method for chemico-mechanical polishing (CMP), remove intrinsic Si layer and the intrinsic Poly-Si layer of collector region, the injection of N type impurity is carried out in this zone, making collector electrode contact zone doping content is 1 * 10 19～1 * 10 20Cm -3, form collector contact area; And to substrate under 950～1100 ℃ of temperature, annealing 15～120s carries out impurity activation, forms SiGe HBT device;
The 11 the step, utilize chemical vapor deposition (CVD) method, at 600～800 ℃, at substrate surface deposit one deck SiO 2, photoetching nmos device active area utilizes dry etch process, at the nmos device active area, etches the deep trouth that the degree of depth is 1.7～2.9 μ m, the oxide layer of centre is carved pass through; Utilize chemical vapor deposition (CVD) method, at 600～750 ℃, selective epitaxial growth four layer materials on the nmos device active area of (100) crystal face substrate: ground floor is that thickness is the P type Si resilient coating of 200～400nm, and doping content is 1～5 * 10 15Cm -3The second layer is that thickness is the P type SiGe graded bedding of 1.3～2.1nm, and this layer bottom Ge component is 0%, and top Ge component is 15～25%, and doping content is 1～5 * 10 15Cm -3The 3rd layer is that the Ge component is 15～25%, and thickness is the P type SiGe layer of 200～400nm, and doping content is 0.5～5 * 10 17Cm -3The 4th layer is that thickness is the P type strain Si layer of 8～20nm, and doping content is 0.5～5 * 10 17Cm -3, as the raceway groove of nmos device; Utilize wet etching, etch away the layer SiO on surface 2
The 12 the step, utilize chemical vapor deposition (CVD) method, at 600～800 ℃, at substrate surface deposit one deck SiO 2, photoetching PMOS device area utilizes chemical vapor deposition (CVD) method; At 600～750 ℃; Selective epitaxial growth materials at two layers on the PMOS device active region: ground floor is that thickness is the N type SiGe strained layer of 8～20nm, and the Ge component is 15～25%, and doping content is 0.5～5 * 10 17Cm -3, as the raceway groove of PMOS device; The second layer is that thickness is the intrinsic relaxation Si cap layer of 3～5nm, forms the PMOS device active region; Utilize wet etching, etch away the layer SiO on surface 2
The 13 step, at 300～400 ℃, on active area with the method deposit HfO of atomic layer chemical vapour deposition (ALCVD) 2Layer, thickness is 6～10nm, as the gate medium of nmos device and PMOS device; Utilize chemical vapor deposition (CVD) method again; At 600～750 ℃, on gate dielectric layer deposit one layer thickness be the intrinsic Poly-SiGe of 100～500nm as gate electrode, the Ge component is 10～30%; Photoetching NMOS and PMOS device gate medium and grid polycrystalline form grid;
The 14 step, photoetching nmos device active area carry out N type ion to the nmos device active area and inject, and forming doping content is 1～5 * 10 18Cm -3N type lightly-doped source drain structure (N-LDD) zone; Photoetching PMOS device active region carries out P type ion to the PMOS device active region and injects, and forming doping content is 1～5 * 10 18Cm -3P type lightly-doped source drain structure (P-LDD) zone;
The 15 the step, utilize chemical vapor deposition (CVD) method, at 600～800 ℃, deposit one thickness is the SiO of 3～5nm on entire substrate 2Layer falls this layer SiO with dry etching 2, form nmos device and PMOS device grids side wall;
The 16 step, photoetching nmos device active area carry out N type ion at the nmos device active area and inject, and autoregistration generates source region, drain region and the grid of nmos device; Photoetching PMOS device active region carries out N type ion at the PMOS device active region and injects, and autoregistration generates source region, drain region and the grid of PMOS device;
The 17 the step, on entire substrate with chemical vapor deposition (CVD) method, at 600～800 ℃, the SiO that deposit 300～500nm is thick 2Layer; Make the lead-in wire window by lithography, sputter layer of metal titanium (Ti) on entire substrate, alloy, autoregistration forms metal silicide, and the metal that clean surface is unnecessary forms the MOS device and contacts with the bipolar device electrode metal; Splash-proofing sputtering metal, the photoetching lead-in wire, constituting conducting channel is the two polycrystalline SOI BiCMOS integrated devices based on crystal face selection of 22～45nm.
Further, wherein, the channel length of MOS device is got 22～45nm.
Further, wherein, base thickness decides according to the epitaxy layer thickness of the 4th step SiGe, gets 20～60nm.
Further, related maximum temperature is according to the 4th chemical vapor deposition (CVD) the technological temperature decision that go on foot in the 17 step among this preparation method, maximum temperature is smaller or equal to 800 ℃.
Another object of the present invention is to provide a kind of preparation method of the two polycrystalline SOI BiCMOS integrated circuits based on crystal face selection, comprise the steps:
Step 1, the implementation method of SOI backing material preparation is:
(1a) choosing N type doping content is 1 * 10 15Cm -3The Si sheet, crystal face is (110), and oxidation is carried out on its surface, oxidated layer thickness is 0.5 μ m, as the basis material on upper strata, and in this basis material, injects hydrogen;
(1b) choosing P type doping content is 1 * 10 15Cm -3The Si sheet, crystal face is (100), and oxidation is carried out on its surface, oxidated layer thickness is 0.5 μ m, as the basis material of lower floor;
(1c) adopt chemico-mechanical polishing (CMP) technology, respectively the upper strata substrate material surface behind lower floor and the injection hydrogen is carried out polishing;
(1d) with lower floor after the polishing and upper strata substrate material surface SiO 2Be close to relatively, place ultra-high vacuum environment under 350 ℃ of temperature, to realize bonding;
(1e) substrate temperature behind the bonding is raise 200 ℃; Make the upper strata basis material in the hydrogen place fracture of injecting, the part that the upper strata basis material is unnecessary is peeled off, keep the Si material of 100nm; And carry out chemico-mechanical polishing (CMP) at this break surface, form soi structure;
Step 2, the implementation method of epitaxial material preparation is:
(2a) utilize the method for chemical vapor deposition (CVD), at 600 ℃, growth one layer thickness is the N type epitaxy Si layer of 250nm on the Si material of upper strata, and as collector region, this layer doping content is 1 * 10 16Cm -3
(2b) utilizing the method for chemical vapor deposition (CVD), at 600 ℃, is the SiO of 200nm at substrate surface deposit one layer thickness 2Layer;
(2c) utilizing the method for chemical vapor deposition (CVD), at 600 ℃, is the SiN layer of 100nm at substrate surface deposit one layer thickness;
(2d) the photoetching base utilizes dry etching, and etching the degree of depth is the zone, base of 200nm;
(2e) utilize the method for chemical vapor deposition (CVD), at 600 ℃, growth one layer thickness is the SiGe layer of 20nm on substrate, and as the base, this layer Ge component is 15%, and doping content is 5 * 10 18Cm -3
(2f) utilize the method for chemical vapor deposition (CVD), at 600 ℃, the unadulterated intrinsic Si layer of growth one layer thickness 10nm on substrate;
(2g) utilize the method for chemical vapor deposition (CVD), at 600 ℃, the unadulterated intrinsic Poly-Si layer of growth one layer thickness 200nm on substrate;
Step 3, the implementation method of device deep trench isolation preparation is:
(3a) utilizing the method for chemical vapor deposition (CVD), at 600 ℃, is the SiO of 200nm at substrate surface deposit one layer thickness 2Layer;
(3b) utilizing the method for chemical vapor deposition (CVD), at 600 ℃, is the SiN layer of 100nm at substrate surface deposit one layer thickness;
(3c) deep trench isolation zone between the lithographic device, dry etching goes out the shallow slot that the degree of depth is 5um in the deep trench isolation zone;
(3d) utilize chemical vapor deposition (CVD) method,, in deep trouth, fill SiO at 600 ℃ 2, form the device deep trench isolation;
Step 4, the implementation method of collector electrode shallow-trench isolation preparation is:
(4a) fall surperficial SiO with wet etching 2With the SiN layer;
(4b) utilizing the method for chemical vapor deposition (CVD), at 600 ℃, is the SiO of 200nm at substrate surface deposit one layer thickness 2Layer;
(4c) utilizing the method for chemical vapor deposition (CVD), at 600 ℃, is the SiN layer of 100nm at substrate surface deposit one layer thickness;
(4d) photoetching collector electrode shallow trench isolation areas goes out the shallow slot that the degree of depth is 180nm at the shallow trench isolation areas dry etching;
(4e) utilize chemical vapor deposition (CVD) method,, in shallow slot, fill SiO at 600 ℃ 2, form the collector electrode shallow-trench isolation;
Step 5, the implementation method of base stage shallow-trench isolation preparation is:
(5a) fall surperficial SiO with wet etching 2With the SiN layer;
(5b) utilizing the method for chemical vapor deposition (CVD), at 600 ℃, is the SiO of 200nm at substrate surface deposit one layer thickness 2Layer;
(5c) utilizing the method for chemical vapor deposition (CVD), at 600 ℃, is the SiN layer of 100nm at substrate surface deposit one layer thickness;
(5d) photoetching base stage shallow trench isolation areas goes out the shallow slot that the degree of depth is 215nm at the shallow trench isolation areas dry etching;
(5e) utilize chemical vapor deposition (CVD) method,, in shallow slot, fill SiO at 600 ℃ 2, form the base stage shallow-trench isolation;
Step 6, the implementation method that SiGe HBT forms is:
(6a) fall surperficial SiO with wet etching 2With the SiN layer;
(6b) utilizing the method for chemical vapor deposition (CVD), at 600 ℃, is the SiO of 300nm at substrate surface deposit one layer thickness 2Layer;
(6c) photoetching base region carries out p type impurity to this zone and injects, and making the contact zone doping content is 1 * 10 19Cm -3, form base stage;
(6d) photoetching emitter region is carried out N type impurity to this zone and is injected, and making doping content is 1 * 10 17Cm -3, form the emitter region;
(6e) photoetching collector region, and utilize the method for chemico-mechanical polishing (CMP), remove intrinsic Si layer and the intrinsic Poly-Si layer of collector region, the injection of N type impurity is carried out in this zone, making collector electrode contact zone doping content is 1 * 10 19Cm -3, form collector electrode;
(6f) to substrate under 950 ℃ of temperature, annealing 120s carries out impurity activation, forms SiGe HBT;
Step 7, the implementation method of nmos device active area preparation is:
(7a) utilize chemical vapor deposition (CVD) method, at 600 ℃, at substrate surface deposit one deck SiO 2
(7b) photoetching nmos device active area utilizes dry etch process, at the nmos device active area, etches the deep trouth that the degree of depth is 1.7 μ m, oxide layer is carved pass through;
(7c) utilizing the method for chemical vapor deposition (CVD), at 600 ℃, is the P type Si resilient coating of 200nm along (100) crystal face layer thickness of growing in deep trouth, and doping content is 1 * 10 15Cm -3
(7d) utilize the method for chemical vapor deposition (CVD), at 600 ℃, growth one layer thickness is the SiGe of the P type Ge component trapezoidal profile of 1.3 μ m on the P type resilient coating, and bottom Ge component is 0%, and the top is 15%, and doping content is 1 * 10 15Cm -3
(7e) utilize the method for chemical vapor deposition (CVD), at 600 ℃, growth one layer thickness is the P type SiGe layer of 200nm on the SiGe layer of Ge component trapezoidal profile, and the Ge component is 15%, and doping content is 5 * 10 16Cm -3
(7f) utilize chemical vapor deposition (CVD) method, at 600 ℃, growth one layer thickness is the strain Si layer of 20nm on the SiGe layer, and doping content is 5 * 10 16Cm -3, as the raceway groove of nmos device;
(7g) utilize wet etching, etch away the layer SiO on surface 2
Step 8, the implementation method of PMOS device active region preparation is:
(8a) utilize chemical vapor deposition (CVD) method, at 600 ℃, at substrate surface deposit one deck SiO 2
(8b) photoetching PMOS device area utilizes the method for chemical vapor deposition (CVD), and at 600 ℃, growth one layer thickness is the P type SiGe layer of 20nm on the Si resilient coating, and the Ge component is 15%, and doping content is 5 * 10 16Cm -3
(8c) utilize the method for chemical vapor deposition (CVD), at 600 ℃, growth one layer thickness is the intrinsic relaxation Si cap layer of 5nm on the strain SiGe layer, forms the PMOS device active region;
(8d) utilize wet etching, etch away the layer SiO on surface 2
The implementation method that step 9, MOS device grids and lightly-doped source are leaked (LDD) preparation is:
(9a) at 300 ℃, on active area with the method deposit HfO of atomic layer chemical vapour deposition (ALCVD) 2Layer, thickness is 6nm, as the gate medium of nmos device and PMOS device;
(9b) utilize chemical vapor deposition (CVD) method, at 600 ℃, the Poly-SiGe of deposit one deck intrinsic on gate dielectric layer, thickness is 100nm, the Ge component is 10%;
(9c) photoetching MOS device gate medium and grid polycrystalline form grid;
(9d) photoetching nmos device active area carries out N type ion to the nmos device active area and injects, and forming doping content is 1 * 10 18Cm -3N type lightly-doped source drain structure (N-LDD) zone;
(9e) photoetching PMOS device active region carries out P type ion to the PMOS device active region and injects, and forming doping content is 1 * 10 18Cm -3P type lightly-doped source drain structure (P-LDD) zone;
Step 10, the implementation method that the MOS device forms is:
(10a) utilize chemical vapor deposition (CVD) method, at 600 ℃, deposit one thickness is the SiO of 3nm on entire substrate 2Layer;
(10b) utilize dry etch process, this layer of eating away SiO 2, keep nmos device and PMOS device grids side wall;
(10c) photoetching nmos device active area carries out N type ion at the nmos device active area and injects, and autoregistration generates source, drain region and the grid of nmos device;
(10d) photoetching PMOS device active region carries out N type ion at the PMOS device active region and injects, and autoregistration generates source, drain region and the grid of PMOS device;
Step 11, the implementation method that constitutes the BiCMOS integrated circuit is:
(11a) with chemical vapor deposition (CVD) method, at 600 ℃, the thick SiO of deposit 300nm on entire substrate 2Layer;
(11b) photoetching lead-in wire window, sputter layer of metal titanium (Ti) on entire substrate, alloy, autoregistration forms metal silicide, and the metal that clean surface is unnecessary forms the device metal contact;
(11c) splash-proofing sputtering metal; The photoetching lead-in wire; Form drain electrode, source electrode, the gate electrode of MOS device, and bipolar transistor emitter, base stage, collector electrode metal lead-in wire, finally constituting conducting channel is two polycrystalline SOI BiCMOS integrated devices and the circuit based on crystal face selection of 22nm.
The present invention has following advantage:
1. in the two polycrystalline SOI BiCMOS integrated devices and circuit based on crystal face selection of the present invention's preparation; Adopted mixing crystal face substrate technology, promptly on same substrate slice, be distributed with (100) and (110) these two kinds of crystal faces, electron mobility is the highest on (100) crystal face; And for the hole; (110) the highest on the crystal face, be 2.5 times on (100) crystal face, the present invention has combined carrier mobility to reach two kinds of the highest crystal faces simultaneously; Can under the situation of the mobility of charge carrier rate that does not reduce a kind of types of devices, improve the mobility of charge carrier rate of another kind of types of devices;
2. the two polycrystalline SOI BiCMOS integrated devices based on crystal face selection of the present invention preparation; Employing selective epitaxial technology; Respectively at nmos device and PMOS device active region selective growth tensile strain Si and compressive strain SiGe material; Make nmos device and electric properties such as PMOS device frequency performance and current driving ability can obtain to promote simultaneously, thereby cmos device and performance of integrated circuits have obtained enhancing;
3. the present invention preparation has adopted the HfO of high K value based on MOS device in two polycrystalline SOI BiCMOS integrated device structures of crystal face selection 2As gate medium, improved the grid-control ability of MOS device, strengthened the electric property of MOS device;
4. the present invention's preparation is quantum well devices based on PMOS device in two polycrystalline SOI BiCMOS integrated device structures of crystal face selection; Be that the strain SiGe channel layer is between Si cap layer and the body Si layer; Compare with the surface channel device; This device can reduce the channel interface scattering effectively, has improved the device electrology characteristic; Simultaneously, SQW can make the problem in the hot electron injection grid medium improve, and has increased the reliability of device and circuit;
5. in the two polycrystalline SOI BiCMOS integrated device technologies based on crystal face selection of the present invention's preparation; Adopt the Poly-SiGe material as gate electrode; Its work function changes with the variation of Ge component, and through regulating Ge component among the Poly-SiGe, realization CMOS threshold voltage can be adjusted continuously; Reduce processing step, reduced technology difficulty;
6. the maximum temperature that relates in the two polycrystalline SOI BiCMOS integrated device processes based on crystal face selection of the present invention's preparation is 800 ℃; Be lower than the technological temperature that causes strain Si and strain SiGe channel stress relaxation; Therefore this preparation method can keep strain Si and strain SiGe channel stress effectively, improves the performance of integrated circuit.
Description of drawings
Fig. 1 is provided by the invention based on two polycrystalline SOI BiCMOS integrated devices of crystal face selection and circuit preparation method's realization flow figure.
Embodiment
In order to make the object of the invention, technical scheme and advantage clearer,, the present invention is further elaborated below in conjunction with accompanying drawing and embodiment.Should be appreciated that specific embodiment described herein only in order to explanation the present invention, and be not used in qualification the present invention.
The embodiment of the invention provides a kind of two polycrystalline SOI BiCMOS integrated devices and circuit based on crystal face selection, and nmos device is a strain Si planar channeling device, and the PMOS device is a strain SiGe planar channeling device, and bipolar device is two polycrystalline SOI SiGe HBT.
As a prioritization scheme of the embodiment of the invention, the conducting channel of nmos device is a tensile strain Si material, and the conducting channel of nmos device is a planar channeling.
As a prioritization scheme of the embodiment of the invention, the conducting channel of PMOS device is a compressive strain SiGe material, and the conducting channel of PMOS device is a planar channeling.
As a prioritization scheme of the embodiment of the invention, nmos device is different with the crystal face of PMOS device, and wherein the crystal face of nmos device is (100), and the crystal face of PMOS device is (110).
As a prioritization scheme of the embodiment of the invention, SiGe HBT device adopts the SOI substrate.
As a prioritization scheme of the embodiment of the invention, the emitter of SiGe HBT device adopts polysilicon to contact with base stage.
As a prioritization scheme of the embodiment of the invention, the base of SiGe HBT device is the strain SiGe material.
Following with reference to accompanying drawing 1, the technological process of the two polycrystalline SOI BiCMOS integrated devices that the present invention is based on crystal face selection and circuit preparation is described in further detail.
Embodiment 1: preparation 22nm is based on the two polycrystalline SOI BiCMOS integrated devices and the circuit of crystal face selection, and concrete steps are following:
Step 1, the preparation of SOI backing material.
(1a) choosing N type doping content is 1 * 10 15Cm -3The Si sheet, crystal face is (110), and oxidation is carried out on its surface, oxidated layer thickness is 0.5 μ m, as the basis material on upper strata, and in this basis material, injects hydrogen;
(1b) choosing P type doping content is 1 * 10 15Cm -3The Si sheet, crystal face is (100), and oxidation is carried out on its surface, oxidated layer thickness is 0.5 μ m, as the basis material of lower floor;
(1c) adopt chemico-mechanical polishing (CMP) technology, respectively the upper strata substrate material surface behind lower floor and the injection hydrogen is carried out polishing;
(1d) with lower floor after the polishing and upper strata substrate material surface SiO 2Be close to relatively, place ultra-high vacuum environment under 350 ℃ of temperature, to realize bonding;
(1e) substrate temperature behind the bonding is raise 200 ℃; Make the upper strata basis material in the hydrogen place fracture of injecting, the part that the upper strata basis material is unnecessary is peeled off, keep the Si material of 100nm; And carry out chemico-mechanical polishing (CMP) at this break surface, form soi structure.
Step 2, the epitaxial material preparation.
(2a) utilize the method for chemical vapor deposition (CVD), at 600 ℃, growth one layer thickness is the N type epitaxy Si layer of 250nm on the Si material of upper strata, and as collector region, this layer doping content is 1 * 10 16Cm -3
(2b) utilizing the method for chemical vapor deposition (CVD), at 600 ℃, is the SiO of 200nm at substrate surface deposit one layer thickness 2Layer;
(2c) utilizing the method for chemical vapor deposition (CVD), at 600 ℃, is the SiN layer of 100nm at substrate surface deposit one layer thickness;
(2d) the photoetching base utilizes dry etching, and etching the degree of depth is the zone, base of 200nm;
(2e) utilize the method for chemical vapor deposition (CVD), at 600 ℃, growth one layer thickness is the SiGe layer of 20nm on substrate, and as the base, this layer Ge component is 15%, and doping content is 5 * 10 18Cm -3
(2f) utilize the method for chemical vapor deposition (CVD), at 600 ℃, the unadulterated intrinsic Si layer of growth one layer thickness 10nm on substrate;
(2g) utilize the method for chemical vapor deposition (CVD), at 600 ℃, the unadulterated intrinsic Poly-Si layer of growth one layer thickness 200nm on substrate.
Step 3, the preparation of device deep trench isolation.
(3a) utilizing the method for chemical vapor deposition (CVD), at 600 ℃, is the SiO of 200nm at substrate surface deposit one layer thickness 2Layer;
(3b) utilizing the method for chemical vapor deposition (CVD), at 600 ℃, is the SiN layer of 100nm at substrate surface deposit one layer thickness;
(3c) deep trench isolation zone between the lithographic device, dry etching goes out the shallow slot that the degree of depth is 5um in the deep trench isolation zone;
(3d) utilize chemical vapor deposition (CVD) method,, in deep trouth, fill SiO at 600 ℃ 2, form the device deep trench isolation.
Step 4, the preparation of collector electrode shallow-trench isolation.
(4a) fall surperficial SiO with wet etching 2With the SiN layer;
(4b) utilizing the method for chemical vapor deposition (CVD), at 600 ℃, is the SiO of 200nm at substrate surface deposit one layer thickness 2Layer;
(4c) utilizing the method for chemical vapor deposition (CVD), at 600 ℃, is the SiN layer of 100nm at substrate surface deposit one layer thickness;
(4d) photoetching collector electrode shallow trench isolation areas goes out the shallow slot that the degree of depth is 180nm at the shallow trench isolation areas dry etching;
(4e) utilize chemical vapor deposition (CVD) method,, in shallow slot, fill SiO at 600 ℃ 2, form the collector electrode shallow-trench isolation.
Step 5, the preparation of base stage shallow-trench isolation.
(5a) fall surperficial SiO with wet etching 2With the SiN layer;
(5b) utilizing the method for chemical vapor deposition (CVD), at 600 ℃, is the SiO of 200nm at substrate surface deposit one layer thickness 2Layer;
(5c) utilizing the method for chemical vapor deposition (CVD), at 600 ℃, is the SiN layer of 100nm at substrate surface deposit one layer thickness;
(5d) photoetching base stage shallow trench isolation areas goes out the shallow slot that the degree of depth is 215nm at the shallow trench isolation areas dry etching;
(5e) utilize chemical vapor deposition (CVD) method,, in shallow slot, fill SiO at 600 ℃ 2, form the base stage shallow-trench isolation.
Step 6, SiGe HBT forms.
(6a) fall surperficial SiO with wet etching 2With the SiN layer;
(6b) utilizing the method for chemical vapor deposition (CVD), at 600 ℃, is the SiO of 300nm at substrate surface deposit one layer thickness 2Layer;
(6c) photoetching base region carries out p type impurity to this zone and injects, and making the contact zone doping content is 1 * 10 19Cm -3, form base stage;
(6d) photoetching emitter region is carried out N type impurity to this zone and is injected, and making doping content is 1 * 10 17Cm -3, form the emitter region;
(6e) photoetching collector region, and utilize the method for chemico-mechanical polishing (CMP), remove intrinsic Si layer and the intrinsic Poly-Si layer of collector region, the injection of N type impurity is carried out in this zone, making collector electrode contact zone doping content is 1 * 10 19Cm -3, form collector electrode;
(6f) to substrate under 950 ℃ of temperature, annealing 120s carries out impurity activation, forms SiGe HBT.
Step 7, the preparation of nmos device active area.
(7a) utilize chemical vapor deposition (CVD) method, at 600 ℃, at substrate surface deposit one deck SiO 2
(7b) photoetching nmos device active area utilizes dry etch process, at the nmos device active area, etches the deep trouth that the degree of depth is 1.7 μ m, oxide layer is carved pass through;
(7c) utilizing the method for chemical vapor deposition (CVD), at 600 ℃, is the P type Si resilient coating of 200nm along (100) crystal face layer thickness of growing in deep trouth, and doping content is 1 * 10 15Cm -3
(7d) utilize the method for chemical vapor deposition (CVD), at 600 ℃, growth one layer thickness is the SiGe of the P type Ge component trapezoidal profile of 1.3 μ m on the P type resilient coating, and bottom Ge component is 0%, and the top is 15%, and doping content is 1 * 10 15Cm -3
(7e) utilize the method for chemical vapor deposition (CVD), at 600 ℃, growth one layer thickness is the P type SiGe layer of 200nm on the SiGe layer of Ge component trapezoidal profile, and the Ge component is 15%, and doping content is 5 * 10 16Cm -3
(7f) utilize chemical vapor deposition (CVD) method, at 600 ℃, growth one layer thickness is the strain Si layer of 20nm on the SiGe layer, and doping content is 5 * 10 16Cm -3, as the raceway groove of nmos device;
(7g) utilize wet etching, etch away the layer SiO on surface 2
Step 8, the preparation of PMOS device active region.
(8a) utilize chemical vapor deposition (CVD) method, at 600 ℃, at substrate surface deposit one deck SiO 2
(8b) photoetching PMOS device area utilizes the method for chemical vapor deposition (CVD), and at 600 ℃, growth one layer thickness is the P type SiGe layer of 20nm on the Si resilient coating, and the Ge component is 15%, and doping content is 5 * 10 16Cm -3
(8c) utilize the method for chemical vapor deposition (CVD), at 600 ℃, growth one layer thickness is the intrinsic relaxation Si cap layer of 5nm on the strain SiGe layer, forms the PMOS device active region;
(8d) utilize wet etching, etch away the layer SiO on surface 2
Step 9, MOS device grids and lightly-doped source are leaked (LDD) preparation.
(9a) at 300 ℃, on active area with the method deposit HfO of atomic layer chemical vapour deposition (ALCVD) 2Layer, thickness is 6nm, as the gate medium of nmos device and PMOS device;
(9b) utilize chemical vapor deposition (CVD) method, at 600 ℃, the Poly-SiGe of deposit one deck intrinsic on gate dielectric layer, thickness is 100nm, the Ge component is 10%;
(9c) photoetching MOS device gate medium and grid polycrystalline form grid;
(9d) photoetching nmos device active area carries out N type ion to the nmos device active area and injects, and forming doping content is 1 * 10 18Cm -3N type lightly-doped source drain structure (N-LDD) zone;
(9e) photoetching PMOS device active region carries out P type ion to the PMOS device active region and injects, and forming doping content is 1 * 10 18Cm -3P type lightly-doped source drain structure (P-LDD) zone.
Step 10, the MOS device forms.
(10a) utilize chemical vapor deposition (CVD) method, at 600 ℃, deposit one thickness is the SiO of 3nm on entire substrate 2Layer;
(10b) utilize dry etch process, this layer of eating away SiO 2, keep nmos device and PMOS device grids side wall;
(10c) photoetching nmos device active area carries out N type ion at the nmos device active area and injects, and autoregistration generates source, drain region and the grid of nmos device;
(10d) photoetching PMOS device active region carries out N type ion at the PMOS device active region and injects, and autoregistration generates source, drain region and the grid of PMOS device.
Step 11 constitutes the BiCMOS integrated circuit.
(11a) with chemical vapor deposition (CVD) method, at 600 ℃, the thick SiO of deposit 300nm on entire substrate 2Layer;
(11b) photoetching lead-in wire window, sputter layer of metal titanium (Ti) on entire substrate, alloy, autoregistration forms metal silicide, and the metal that clean surface is unnecessary forms the device metal contact;
(11c) splash-proofing sputtering metal; The photoetching lead-in wire; Form drain electrode, source electrode, the gate electrode of MOS device, and bipolar transistor emitter, base stage, collector electrode metal lead-in wire, finally constituting conducting channel is two polycrystalline SOI BiCMOS integrated devices and the circuit based on crystal face selection of 22nm.
Embodiment 2: preparation 30nm is based on the two polycrystalline SOI BiCMOS integrated devices and the circuit of crystal face selection, and concrete steps are following:
Step 1, the preparation of SOI backing material.
(1a) choosing N type doping content is 3 * 10 15Cm -3The Si sheet, crystal face is (110), and oxidation is carried out on its surface, oxidated layer thickness is 0.75 μ m, as the basis material on upper strata, and in this basis material, injects hydrogen;
(1b) choosing P type doping content is 3 * 10 15Cm -3The Si sheet, crystal face is (100), and oxidation is carried out on its surface, oxidated layer thickness is 0.75 μ m, as the basis material of lower floor;
(1c) adopt chemico-mechanical polishing (CMP) technology, respectively the upper strata active layer substrate material surface behind lower floor and the injection hydrogen is carried out polishing;
(1d) with lower floor after the polishing and upper strata substrate material surface SiO 2Be close to relatively, place ultra-high vacuum environment under 400 ℃ of temperature, to realize bonding;
(1e) substrate temperature behind the bonding is raise 150 ℃; Make the upper strata basis material in the hydrogen place fracture of injecting, the part that the upper strata basis material is unnecessary is peeled off, keep the Si material of 150nm; And carry out chemico-mechanical polishing (CMP) at this break surface, form soi structure.
Step 2, the epitaxial material preparation.
(2a) utilize the method for chemical vapor deposition (CVD), at 700 ℃, growth one layer thickness is the N type epitaxy Si layer of 250nm on the Si material of upper strata, and as collector region, this layer doping content is 5 * 10 16Cm -3
(2b) utilizing the method for chemical vapor deposition (CVD), at 700 ℃, is the SiO of 240nm at substrate surface deposit one layer thickness 2Layer;
(2c) utilizing the method for chemical vapor deposition (CVD), at 700 ℃, is the SiN layer of 150nm at substrate surface deposit one layer thickness;
(2d) the photoetching base utilizes dry etching, and etching the degree of depth is the zone, base of 200nm;
(2e) utilize the method for chemical vapor deposition (CVD), at 700 ℃, growth one layer thickness is the SiGe layer of 40nm on substrate, and as the base, this layer Ge component is 20%, and doping content is 1 * 10 19Cm -3
(2f) utilize the method for chemical vapor deposition (CVD), at 700 ℃, the unadulterated intrinsic Si layer of growth one layer thickness 15nm on substrate;
(2g) utilize the method for chemical vapor deposition (CVD), at 700 ℃, the unadulterated intrinsic Poly-Si layer of growth one layer thickness 240nm on substrate.
Step 3, the preparation of device deep trench isolation.
(3a) utilizing the method for chemical vapor deposition (CVD), at 700 ℃, is the SiO of 240nm at substrate surface deposit one layer thickness 2Layer;
(3b) utilizing the method for chemical vapor deposition (CVD), at 700 ℃, is the SiN layer of 150nm at substrate surface deposit one layer thickness;
(3c) deep trench isolation zone between the lithographic device, dry etching goes out the shallow slot that the degree of depth is 5 μ m in the deep trench isolation zone;
(3d) utilize chemical vapor deposition (CVD) method,, in deep trouth, fill SiO at 700 ℃ 2, form the device deep trench isolation.
Step 4, the preparation of collector electrode shallow-trench isolation.
(4a) fall surperficial SiO with wet etching 2With the SiN layer;
(4b) utilizing the method for chemical vapor deposition (CVD), at 700 ℃, is the SiO of 240nm at substrate surface deposit one layer thickness 2Layer;
(4c) utilizing the method for chemical vapor deposition (CVD), at 700 ℃, is the SiN layer of 150nm at substrate surface deposit one layer thickness;
(4d) photoetching collector electrode shallow trench isolation areas goes out the shallow slot that the degree of depth is 240nm at the shallow trench isolation areas dry etching;
(4e) utilize chemical vapor deposition (CVD) method,, in shallow slot, fill SiO at 700 ℃ 2, form the collector electrode shallow-trench isolation.
Step 5, the preparation of base stage shallow-trench isolation.
(5a) fall surperficial SiO with wet etching 2With the SiN layer;
(5b) utilizing the method for chemical vapor deposition (CVD), at 700 ℃, is the SiO of 240nm at substrate surface deposit one layer thickness 2Layer;
(5c) utilizing the method for chemical vapor deposition (CVD), at 700 ℃, is the SiN layer of 150nm at substrate surface deposit one layer thickness;
(5d) photoetching base stage shallow trench isolation areas goes out the shallow slot that the degree of depth is 260nm at the shallow trench isolation areas dry etching;
(5e) utilize chemical vapor deposition (CVD) method,, in shallow slot, fill SiO at 700 ℃ 2, form the base stage shallow-trench isolation.
Step 6, SiGe HBT forms.
(6a) fall surperficial SiO with wet etching 2With the SiN layer;
(6b) utilizing the method for chemical vapor deposition (CVD), at 700 ℃, is the SiO of 400nm at substrate surface deposit one layer thickness 2Layer;
(6c) photoetching base region carries out p type impurity to this zone and injects, and making the contact zone doping content is 5 * 10 19Cm -3, form base stage;
(6d) photoetching emitter region is carried out N type impurity to this zone and is injected, and making doping content is 3 * 10 17Cm -3, form the emitter region;
(6e) photoetching collector region, and utilize the method for chemico-mechanical polishing (CMP), remove intrinsic Si layer and the intrinsic Poly-Si layer of collector region, the injection of N type impurity is carried out in this zone, making collector electrode contact zone doping content is 5 * 10 19Cm -3, form collector electrode;
(6f) to substrate under 1000 ℃ of temperature, annealing 60s carries out impurity activation, forms SiGe HBT.
Step 7, the preparation of nmos device active area.
(7a) utilize chemical vapor deposition (CVD) method, at 700 ℃, at substrate surface deposit one deck SiO 2
(7b) photoetching nmos device active area utilizes dry etch process, at the nmos device active area, etches the deep trouth that the degree of depth is 2.3 μ m, oxide layer is carved pass through;
(7c) utilizing the method for chemical vapor deposition (CVD), at 700 ℃, is the P type Si resilient coating of 300nm along (100) crystal face layer thickness of growing in deep trouth, and doping content is 3 * 10 15Cm -3
(7d) utilize the method for chemical vapor deposition (CVD), at 700 ℃, growth one layer thickness is the SiGe of the P type Ge component trapezoidal profile of 1.7 μ m on the P type resilient coating, and bottom Ge component is 0%, and the top is 20%, and doping content is 3 * 10 15Cm -3
(7e) utilize the method for chemical vapor deposition (CVD), at 700 ℃, growth one layer thickness is the P type SiGe layer of 300nm on the SiGe layer of Ge component trapezoidal profile, and the Ge component is 20%, and doping content is 1 * 10 17Cm -3
(7f) utilize chemical vapor deposition (CVD) method, at 700 ℃, growth one layer thickness is the strain Si layer of 15nm on the SiGe layer, and doping content is 1 * 10 17Cm -3, as the raceway groove of nmos device;
(7g) utilize wet etching, etch away the layer SiO on surface 2
Step 8, the preparation of PMOS device active region.
(8a) utilize chemical vapor deposition (CVD) method, at 700 ℃, at substrate surface deposit one deck SiO 2
(8b) photoetching PMOS device area utilizes the method for chemical vapor deposition (CVD), and at 700 ℃, growth one layer thickness is the P type SiGe layer of 15nm on the Si resilient coating, and the Ge component is 20%, and doping content is 1 * 10 17Cm -3
(8c) utilize the method for chemical vapor deposition (CVD), at 700 ℃, growth one layer thickness is the intrinsic relaxation Si cap layer of 4nm on the strain SiGe layer, forms the PMOS device active region;
(8d) utilize wet etching, etch away the layer SiO on surface 2
Step 9, MOS device grids and lightly-doped source are leaked (LDD) preparation.
(9a) at 350 ℃, on active area with the method deposit HfO of atomic layer chemical vapour deposition (ALCVD) 2Layer, thickness is 8nm, as the gate medium of nmos device and PMOS device;
(9b) utilize chemical vapor deposition (CVD) method, at 700 ℃, the Poly-SiGe of deposit one deck intrinsic on gate dielectric layer, thickness is 300nm, the Ge component is 20%;
(9c) photoetching MOS device gate medium and grid polycrystalline form grid;
(9d) photoetching nmos device active area carries out N type ion to the nmos device active area and injects, and forming doping content is 3 * 10 18Cm -3N type lightly-doped source drain structure (N-LDD) zone;
(9e) photoetching PMOS device active region carries out P type ion to the PMOS device active region and injects, and forming doping content is 3 * 10 18Cm -3P type lightly-doped source drain structure (P-LDD) zone.
Step 10, the MOS device forms.
(10a) utilize chemical vapor deposition (CVD) method, at 700 ℃, deposit one thickness is the SiO of 4nm on entire substrate 2Layer;
(10b) utilize dry etch process, this layer of eating away SiO 2, keep nmos device and PMOS device grids side wall;
(10c) photoetching nmos device active area carries out N type ion at the nmos device active area and injects, and autoregistration generates source, drain region and the grid of nmos device;
(10d) photoetching PMOS device active region carries out N type ion at the PMOS device active region and injects, and autoregistration generates source, drain region and the grid of PMOS device.
Step 11 constitutes the BiCMOS integrated circuit.
(11a) with chemical vapor deposition (CVD) method, at 700 ℃, the thick SiO of deposit 400nm on entire substrate 2Layer;
(11b) photoetching lead-in wire window, sputter layer of metal titanium (Ti) on entire substrate, alloy, autoregistration forms metal silicide, and the metal that clean surface is unnecessary forms the device metal contact;
(11c) splash-proofing sputtering metal; The photoetching lead-in wire; Form drain electrode, source electrode, the gate electrode of MOS device respectively, and bipolar transistor emitter, base stage, collector electrode metal lead-in wire, finally constituting conducting channel is two polycrystalline SOI BiCMOS integrated devices and the circuit based on crystal face selection of 30nm.
Embodiment 3: preparation 45nm is based on the two polycrystalline SOI BiCMOS integrated devices and the circuit of crystal face selection, and concrete steps are following:
Step 1, the preparation of SOI backing material.
(1a) choosing N type doping content is 5 * 10 15Cm -3The Si sheet, crystal face is (110), and oxidation is carried out on its surface, oxidated layer thickness is 1 μ m, as the basis material on upper strata, and in this basis material, injects hydrogen;
(1b) choosing P type doping content is 5 * 10 15Cm -3The Si sheet, crystal face is (100), and oxidation is carried out on its surface, oxidated layer thickness is 1 μ m, as the basis material of lower floor;
(1c) adopt chemico-mechanical polishing (CMP) technology, respectively to carrying out polishing with the upper strata substrate material surface that injects behind the hydrogen layer by layer down;
(1d) with lower floor after the polishing and upper strata substrate material surface SiO 2Be close to relatively, place ultra-high vacuum environment under 480 ℃ of temperature, to realize bonding;
(1e) substrate temperature behind the bonding is raise 100 ℃; Make the upper strata basis material in the hydrogen place fracture of injecting, the part that the upper strata basis material is unnecessary is peeled off, keep the Si material of 200nm; And carry out chemico-mechanical polishing (CMP) at this break surface, form soi structure.
Step 2, the epitaxial material preparation.
(2a) utilize the method for chemical vapor deposition (CVD), at 750 ℃, growth one layer thickness is the N type epitaxy Si layer of 300nm on the Si material of upper strata, and as collector region, this layer doping content is 1 * 10 17Cm -3
(2b) utilizing the method for chemical vapor deposition (CVD), at 800 ℃, is the SiO of 300nm at substrate surface deposit one layer thickness 2Layer;
(2c) utilizing the method for chemical vapor deposition (CVD), at 800 ℃, is the SiN layer of 200nm at substrate surface deposit one layer thickness;
(2d) the photoetching base utilizes dry etching, and etching the degree of depth is the zone, base of 200nm;
(2e) utilize the method for chemical vapor deposition (CVD), at 750 ℃, growth one layer thickness is the SiGe layer of 60nm on substrate, and as the base, this layer Ge component is 25%, and doping content is 5 * 10 19Cm -3
(2f) utilize the method for chemical vapor deposition (CVD), at 750 ℃, the unadulterated intrinsic Si layer of growth one layer thickness 20nm on substrate;
(2g) utilize the method for chemical vapor deposition (CVD), at 750 ℃, the unadulterated intrinsic Poly-Si layer of growth one layer thickness 300nm on substrate.
Step 3, the preparation of device deep trench isolation.
(3a) utilizing the method for chemical vapor deposition (CVD), at 800 ℃, is the SiO of 300nm at substrate surface deposit one layer thickness 2Layer;
(3b) utilizing the method for chemical vapor deposition (CVD), at 800 ℃, is the SiN layer of 200nm at substrate surface deposit one layer thickness;
(3c) deep trench isolation zone between the lithographic device, dry etching goes out the shallow slot that the degree of depth is 5 μ m in the deep trench isolation zone;
(3d) utilize chemical vapor deposition (CVD) method,, in deep trouth, fill SiO at 800 ℃ 2, form the device deep trench isolation.
Step 4, the preparation of collector electrode shallow-trench isolation.
(4a) fall surperficial SiO with wet etching 2With the SiN layer;
(4b) utilizing the method for chemical vapor deposition (CVD), at 800 ℃, is the SiO of 300nm at substrate surface deposit one layer thickness 2Layer;
(4c) utilizing the method for chemical vapor deposition (CVD), at 800 ℃, is the SiN layer of 200nm at substrate surface deposit one layer thickness;
(4d) photoetching collector electrode shallow trench isolation areas goes out the shallow slot that the degree of depth is 300nm at the shallow trench isolation areas dry etching;
(4e) utilize chemical vapor deposition (CVD) method,, in shallow slot, fill SiO at 800 ℃ 2, form the collector electrode shallow-trench isolation.
Step 5, the preparation of base stage shallow-trench isolation.
(5a) fall surperficial SiO with wet etching 2With the SiN layer;
(5b) utilizing the method for chemical vapor deposition (CVD), at 800 ℃, is the SiO of 300nm at substrate surface deposit one layer thickness 2Layer;
(5c) utilizing the method for chemical vapor deposition (CVD), at 800 ℃, is the SiN layer of 200nm at substrate surface deposit one layer thickness;
(5d) photoetching base stage shallow trench isolation areas goes out the shallow slot that the degree of depth is 325nm at the shallow trench isolation areas dry etching;
(5e) utilize chemical vapor deposition (CVD) method,, in shallow slot, fill SiO at 800 ℃ 2, form the base stage shallow-trench isolation.
Step 6, SiGe HBT forms.
(6a) fall surperficial SiO with wet etching 2With the SiN layer;
(6b) utilizing the method for chemical vapor deposition (CVD), at 800 ℃, is the SiO of 500nm at substrate surface deposit one layer thickness 2Layer;
(6c) photoetching base region carries out p type impurity to this zone and injects, and making the contact zone doping content is 1 * 10 20Cm -3, form base stage;
(6d); The photoetching emitter region is carried out N type impurity to this zone and is injected, and making doping content is 5 * 10 17Cm -3, form the emitter region;
(6e) photoetching collector region, and utilize the method for chemico-mechanical polishing (CMP), remove intrinsic Si layer and the intrinsic Poly-Si layer of collector region, the injection of N type impurity is carried out in this zone, making collector electrode contact zone doping content is 1 * 10 20Cm -3, form collector electrode;
(6f) to substrate under 1100 ℃ of temperature, annealing 15s carries out impurity activation, forms SiGe HBT.
Step 7, the preparation of nmos device active area.
(7a) utilize chemical vapor deposition (CVD) method, at 800 ℃, at substrate surface deposit one deck SiO 2
(7b) photoetching nmos device active area utilizes dry etch process, at the nmos device active area, etches the deep trouth that the degree of depth is 2.9 μ m, oxide layer is carved pass through;
(7c) utilizing the method for chemical vapor deposition (CVD), at 750 ℃, is the P type Si resilient coating of 400nm along (100) crystal face layer thickness of growing in deep trouth, and doping content is 5 * 10 15Cm -3
(7d) utilize the method for chemical vapor deposition (CVD), at 750 ℃, growth one layer thickness is the SiGe of the P type Ge component trapezoidal profile of 2.1 μ m on the P type resilient coating, and bottom Ge component is 0%, and the top is 25%, and doping content is 5 * 10 15Cm -3
(7e) utilize the method for chemical vapor deposition (CVD), at 750 ℃, growth one layer thickness is the P type SiGe layer of 400nm on the SiGe layer of Ge component trapezoidal profile, and the Ge component is 25%, and doping content is 5 * 10 17Cm -3
(7f) utilize chemical vapor deposition (CVD) method, at 750 ℃, growth one layer thickness is the strain Si layer of 8nm on the SiGe layer, and doping content is 5 * 10 17Cm -3, as the raceway groove of nmos device;
(7g) utilize wet etching, etch away the layer SiO on surface 2
Step 8, the preparation of PMOS device active region.
(8a) utilize chemical vapor deposition (CVD) method, at 800 ℃, at substrate surface deposit one deck SiO 2
(8b) photoetching PMOS device area utilizes the method for chemical vapor deposition (CVD), and at 750 ℃, growth one layer thickness is the P type SiGe layer of 8nm on the Si resilient coating, and the Ge component is 25%, and doping content is 5 * 10 17Cm -3
(8c) utilize the method for chemical vapor deposition (CVD), at 750 ℃, growth one layer thickness is the intrinsic relaxation Si cap layer of 3nm on the strain SiGe layer, forms the PMOS device active region;
(8d) utilize wet etching, etch away the layer SiO on surface 2
Step 9, MOS device grids and LDD preparation.
(9a) at 400 ℃, on active area with the method deposit HfO of atomic layer chemical vapour deposition (ALCVD) 2Layer, thickness is 10nm, as the gate medium of nmos device and PMOS device;
(9b) utilize chemical vapor deposition (CVD) method, at 750 ℃, the Poly-SiGe of deposit one deck intrinsic on gate dielectric layer, thickness is 500nm, the Ge component is 30%;
(9c) photoetching MOS device gate medium and grid polycrystalline form grid;
(9d) photoetching nmos device active area carries out N type ion to the nmos device active area and injects, and forming doping content is 5 * 10 18Cm -3N type lightly-doped source drain structure (N-LDD) zone;
(9e) photoetching PMOS device active region carries out P type ion to the PMOS device active region and injects, and forming doping content is 5 * 10 18Cm -3P type lightly-doped source drain structure (P-LDD) zone.
Step 10, the MOS device forms.
(10a) utilize chemical vapor deposition (CVD) method, at 800 ℃, deposit one thickness is the SiO of 5nm on entire substrate 2Layer;
(10b) utilize dry etch process, this layer of eating away SiO 2, keep nmos device and PMOS device grids side wall;
(10c) photoetching nmos device active area carries out N type ion at the nmos device active area and injects, and autoregistration generates source, drain region and the grid of nmos device;
(10d) photoetching PMOS device active region carries out N type ion at the PMOS device active region and injects, and autoregistration generates source, drain region and the grid of PMOS device.
Step 11 constitutes the BiCMOS integrated circuit.
(11a) with chemical vapor deposition (CVD) method, at 800 ℃, the thick SiO of deposit 500nm on entire substrate 2Layer;
(11b) photoetching lead-in wire window, sputter layer of metal titanium (Ti) on entire substrate, alloy, autoregistration forms metal silicide, and the metal that clean surface is unnecessary forms the device metal contact;
(11c) splash-proofing sputtering metal; The photoetching lead-in wire; Form drain electrode, source electrode, the gate electrode of MOS device, and bipolar transistor emitter, base stage, collector electrode metal lead-in wire, finally constituting conducting channel is two polycrystalline SOI BiCMOS integrated devices and the circuit based on crystal face selection of 45nm.
Two polycrystalline SOI BiCMOS integrated devices and preparation method based on crystal face selection that the embodiment of the invention provides have following advantage:
1. in the two polycrystalline SOI BiCMOS integrated devices and circuit based on crystal face selection of the present invention's preparation; Adopted mixing crystal face substrate technology, promptly on same substrate slice, be distributed with (100) and (110) these two kinds of crystal faces, electron mobility is the highest on (100) crystal face; And for the hole; (110) the highest on the crystal face, be 2.5 times on (100) crystal face, the present invention has combined carrier mobility to reach two kinds of the highest crystal faces simultaneously; Can under the situation of the mobility of charge carrier rate that does not reduce a kind of types of devices, improve the mobility of charge carrier rate of another kind of types of devices;
2. the two polycrystalline SOI BiCMOS integrated devices based on crystal face selection of the present invention preparation; Employing selective epitaxial technology; Respectively at nmos device and PMOS device active region selective growth tensile strain Si and compressive strain SiGe material; Make nmos device and electric properties such as PMOS device frequency performance and current driving ability can obtain to promote simultaneously, thereby cmos device and performance of integrated circuits have obtained enhancing;
3. the present invention preparation has adopted the HfO of high K value based on MOS device in two polycrystalline SOI BiCMOS integrated device structures of crystal face selection 2As gate medium, improved the grid-control ability of MOS device, strengthened the electric property of MOS device;
4. the present invention's preparation is quantum well devices based on PMOS device in two polycrystalline SOI BiCMOS integrated device structures of crystal face selection; Be that the strain SiGe channel layer is between Si cap layer and the body Si layer; Compare with the surface channel device; This device can reduce the channel interface scattering effectively, has improved the device electrology characteristic; Simultaneously, SQW can make the problem in the hot electron injection grid medium improve, and has increased the reliability of device and circuit;
5. in the two polycrystalline SOI BiCMOS integrated device technologies based on crystal face selection of the present invention's preparation; Adopt the Poly-SiGe material as gate electrode; Its work function changes with the variation of Ge component, and through regulating Ge component among the Poly-SiGe, realization CMOS threshold voltage can be adjusted continuously; Reduce processing step, reduced technology difficulty;
6. the maximum temperature that relates in the two polycrystalline SOI BiCMOS integrated device processes based on crystal face selection of the present invention's preparation is 800 ℃; Be lower than the technological temperature that causes strain Si and strain SiGe channel stress relaxation; Therefore this preparation method can keep strain Si and strain SiGe channel stress effectively, improves the performance of integrated circuit.
The above is merely preferred embodiment of the present invention, not in order to restriction the present invention, all any modifications of within spirit of the present invention and principle, being done, is equal to and replaces and improvement etc., all should be included within protection scope of the present invention.

Claims (12)

1. the two polycrystalline SOI BiCMOS integrated devices based on crystal face selection is characterized in that nmos device is a strain Si planar channeling device, and the PMOS device is a strain SiGe planar channeling device, and bipolar device is two polycrystalline SOI SiGe HBT.
2. the two polycrystalline SOI BiCMOS integrated devices based on crystal face selection according to claim 1 is characterized in that the conducting channel of nmos device is a tensile strain Si material, and the conducting channel of nmos device is a planar channeling.
3. the two polycrystalline SOI BiCMOS integrated devices based on crystal face selection according to claim 1 is characterized in that the conducting channel of PMOS device is a compressive strain SiGe material, and the conducting channel of PMOS device is a planar channeling.
4. the two polycrystalline SOI BiCMOS integrated devices based on crystal face selection according to claim 1 is characterized in that nmos device is different with the crystal face of PMOS device, and wherein the crystal face of nmos device is (100), and the crystal face of PMOS device is (110).
5. three polycrystalline SOI SiGe HBT integrated devices based on self-registered technology according to claim 1 is characterized in that, SiGe HBT device adopts the SOI substrate.
6. two polycrystalline SOI BiCMOS integrated devices and circuit based on crystal face selection according to claim 1 is characterized in that, the emitter of SiGe HBT device adopts polysilicon to contact with base stage.
7. strain Si vertical-channel SOI BiCMOS integrated device according to claim 1, the base of SiGeHBT device is the strain SiGe material.
8. the preparation method based on two polycrystalline SOI BiCMOS integrated devices of crystal face selection comprises the steps:
The first step, choose two Si sheets, one is that N type doping content is 1～5 * 10 15Cm -3Si (110) substrate slice, as the upper strata basis material, another piece is that P type doping content is 1～5 * 10 15Cm -3Si (100) substrate slice, as lower floor's basis material; Oxidation is carried out on two Si sheet surfaces, and oxidated layer thickness is 0.5 ~ 1 μ m, adopts chemico-mechanical polishing (CMP) technology that two oxide layer surfaces are polished;
Second step, to injecting hydrogen in the basis material of upper strata, and two Si sheet oxide layers be opposite in the ultra-high vacuum environment mutually under 350～480 ℃ temperature, realize bonding; Si sheet temperature behind the bonding is raise 100～200 ℃; Make the upper strata basis material in the hydrogen place fracture of injecting, the part that the upper strata basis material is unnecessary is peeled off, keep the Si material of 100 ~ 200nm; And carry out chemico-mechanical polishing (CMP) at its break surface, form the SOI substrate;
The 3rd goes on foot, utilizes the method for chemical vapor deposition (CVD), at 600～750 ℃, and growth Si epitaxial loayer on substrate, thickness is 250～300nm, and the N type mixes, and doping content is 1 * 10 16～1 * 10 17Cm -3, as collector region;
The 4th goes on foot, utilizes the method for chemical vapor deposition (CVD), at 600～800 ℃, is the SiO of 200 ~ 300nm at substrate surface deposit one layer thickness 2A layer and a layer thickness are the SiN layer of 100 ~ 200nm; The photoetching base utilizes dry etching, etches the degree of depth and be the zone, base of 200nm, and at substrate surface growth trilaminate material: ground floor is the SiGe layer, and the Ge component is 15 ~ 25%, and thickness is 20 ~ 60nm, and the P type mixes, and doping content is 5 * 10 18~ 5 * 10 19Cm -3, as the base; The second layer is unadulterated intrinsic Si layer, and thickness is 10 ~ 20nm; The 3rd layer is unadulterated intrinsic Poly-Si layer, and thickness is 200～300nm, as base stage and emitter region;
The 5th goes on foot, utilizes the method for chemical vapor deposition (CVD), at 600～800 ℃, is the SiO of 200 ~ 300nm at substrate surface deposit one layer thickness 2A layer and a layer thickness are the SiN layer of 100 ~ 200nm; Deep trench isolation zone between lithographic device, dry etching goes out the deep trouth that the degree of depth is 5 μ m in the deep trench isolation zone, utilizes chemical vapor deposition (CVD) method, at 600～800 ℃, in deep trouth, fills SiO 2
The 6th goes on foot, falls with wet etching the SiO on surface 2With the SiN layer, utilize the method for chemical vapor deposition (CVD) again, at 600～800 ℃, be the SiO of 200 ~ 300nm at substrate surface deposit one layer thickness 2A layer and a layer thickness are the SiN layer of 100 ~ 200nm; Photoetching collector region shallow trench isolation areas goes out the shallow slot that the degree of depth is 180 ~ 300nm at the shallow trench isolation areas dry etching, utilizes chemical vapor deposition (CVD) method, at 600～800 ℃, in shallow slot, fills SiO 2
The 7th goes on foot, falls with wet etching the SiO on surface 2With the SiN layer, utilize the method for chemical vapor deposition (CVD) again, at 600～800 ℃, be the SiO of 200 ~ 300nm at substrate surface deposit one layer thickness 2A layer and a layer thickness are the SiN layer of 100 ~ 200nm; Photoetching base shallow trench isolation areas goes out the shallow slot that the degree of depth is 215 ~ 325nm at the shallow trench isolation areas dry etching, utilizes chemical vapor deposition (CVD) method, at 600～800 ℃, in shallow slot, fills SiO 2
The 8th goes on foot, falls with wet etching the SiO on surface 2With the SiN layer, utilize the method for chemical vapor deposition (CVD), at 600～800 ℃, be the SiO of 300 ~ 500nm at substrate surface deposit one layer thickness 2Layer; The photoetching base region carries out p type impurity to this zone and injects, and making base stage contact zone doping content is 1 * 10 19～1 * 10 20Cm -3, form the base stage contact area;
The 9th step, photoetching emitting area carry out N type impurity to this zone and inject, and making doping content is 1 * 10 17～5 * 10 17Cm -3, form the emitter region;
The tenth step, photoetching collector region, and utilize the method for chemico-mechanical polishing (CMP), remove intrinsic Si layer and the intrinsic Poly-Si layer of collector region, the injection of N type impurity is carried out in this zone, making collector electrode contact zone doping content is 1 * 10 19～1 * 10 20Cm -3, form collector contact area; And to substrate under 950～1100 ℃ of temperature, annealing 15～120s carries out impurity activation, forms SiGe HBT device;
The 11 the step, utilize chemical vapor deposition (CVD) method, at 600～800 ℃, at substrate surface deposit one deck SiO 2, photoetching nmos device active area utilizes dry etch process, at the nmos device active area, etches the deep trouth that the degree of depth is 1.7～2.9 μ m, the oxide layer of centre is carved pass through; Utilize chemical vapor deposition (CVD) method, at 600～750 ℃, selective epitaxial growth four layer materials on the nmos device active area of (100) crystal face substrate: ground floor is that thickness is the P type Si resilient coating of 200～400nm, and doping content is 1～5 * 10 15Cm -3The second layer is that thickness is the P type SiGe graded bedding of 1.3～2.1nm, and this layer bottom Ge component is 0%, and top Ge component is 15～25%, and doping content is 1～5 * 10 15Cm -3The 3rd layer is that the Ge component is 15～25%, and thickness is the P type SiGe layer of 200～400nm, and doping content is 0.5～5 * 10 17Cm -3The 4th layer is that thickness is the P type strain Si layer of 8～20nm, and doping content is 0.5～5 * 10 17Cm -3, as the raceway groove of nmos device; Utilize wet etching, etch away the layer SiO on surface 2
The 12 the step, utilize chemical vapor deposition (CVD) method, at 600～800 ℃, at substrate surface deposit one deck SiO 2, photoetching PMOS device area utilizes chemical vapor deposition (CVD) method; At 600～750 ℃; Selective epitaxial growth materials at two layers on the PMOS device active region: ground floor is that thickness is the N type SiGe strained layer of 8～20nm, and the Ge component is 15～25%, and doping content is 0.5～5 * 10 17Cm -3, as the raceway groove of PMOS device; The second layer is that thickness is the intrinsic relaxation Si cap layer of 3～5nm, forms the PMOS device active region; Utilize wet etching, etch away the layer SiO on surface 2
The 13 step, at 300～400 ℃, on active area with the method deposit HfO of atomic layer chemical vapour deposition (ALCVD) 2Layer, thickness is 6～10nm, as the gate medium of nmos device and PMOS device; Utilize chemical vapor deposition (CVD) method again; At 600～750 ℃, on gate dielectric layer deposit one layer thickness be the intrinsic Poly-SiGe of 100～500nm as gate electrode, the Ge component is 10～30%; Photoetching NMOS and PMOS device gate medium and grid polycrystalline form grid;
The 14 step, photoetching nmos device active area carry out N type ion to the nmos device active area and inject, and forming doping content is 1～5 * 10 18Cm -3N type lightly-doped source drain structure (N-LDD) zone; Photoetching PMOS device active region carries out P type ion to the PMOS device active region and injects, and forming doping content is 1～5 * 10 18Cm -3P type lightly-doped source drain structure (P-LDD) zone;
The 15 the step, utilize chemical vapor deposition (CVD) method, at 600～800 ℃, deposit one thickness is the SiO of 3～5nm on entire substrate 2Layer falls this layer SiO with dry etching 2, form nmos device and PMOS device grids side wall;
The 16 step, photoetching nmos device active area carry out N type ion at the nmos device active area and inject, and autoregistration generates source region, drain region and the grid of nmos device; Photoetching PMOS device active region carries out N type ion at the PMOS device active region and injects, and autoregistration generates source region, drain region and the grid of PMOS device;
The 17 the step, on entire substrate with chemical vapor deposition (CVD) method, at 600～800 ℃, the SiO that deposit 300～500nm is thick 2Layer; Make the lead-in wire window by lithography, sputter layer of metal titanium (Ti) on entire substrate, alloy, autoregistration forms metal silicide, and the metal that clean surface is unnecessary forms the MOS device and contacts with the bipolar device electrode metal; Splash-proofing sputtering metal, the photoetching lead-in wire, constituting conducting channel is the two polycrystalline SOI BiCMOS integrated devices based on crystal face selection of 22～45nm.
9. method according to claim 8, wherein, the channel length of MOS device is got 22～45nm.
10. preparation method according to claim 8, wherein, base thickness decides according to the epitaxy layer thickness of the 4th step SiGe, gets 20～60nm.
11. method according to claim 8, related maximum temperature is according to the 4th chemical vapor deposition (CVD) the technological temperature decision that go on foot in the 17 step among this preparation method, and maximum temperature is smaller or equal to 800 ℃.
12. the preparation method based on two polycrystalline SOI BiCMOS integrated circuits of crystal face selection comprises the steps:
Step 1, the implementation method of SOI backing material preparation is:
(1a) choosing N type doping content is 1 * 10 15Cm -3The Si sheet, crystal face is (110), and oxidation is carried out on its surface, oxidated layer thickness is 0.5 μ m, as the basis material on upper strata, and in this basis material, injects hydrogen;
(1b) choosing P type doping content is 1 * 10 15Cm -3The Si sheet, crystal face is (100), and oxidation is carried out on its surface, oxidated layer thickness is 0.5 μ m, as the basis material of lower floor;
(1c) adopt chemico-mechanical polishing (CMP) technology, respectively the upper strata substrate material surface behind lower floor and the injection hydrogen is carried out polishing;
(1d) with lower floor after the polishing and upper strata substrate material surface SiO 2Be close to relatively, place ultra-high vacuum environment under 350 ℃ of temperature, to realize bonding;
(1e) substrate temperature behind the bonding is raise 200 ℃; Make the upper strata basis material in the hydrogen place fracture of injecting, the part that the upper strata basis material is unnecessary is peeled off, keep the Si material of 100nm; And carry out chemico-mechanical polishing (CMP) at this break surface, form soi structure;
Step 2, the implementation method of epitaxial material preparation is:
(2a) utilize the method for chemical vapor deposition (CVD), at 600 ℃, growth one layer thickness is the N type epitaxy Si layer of 250nm on the Si material of upper strata, and as collector region, this layer doping content is 1 * 10 16Cm -3
(2b) utilizing the method for chemical vapor deposition (CVD), at 600 ℃, is the SiO of 200nm at substrate surface deposit one layer thickness 2Layer;
(2c) utilizing the method for chemical vapor deposition (CVD), at 600 ℃, is the SiN layer of 100nm at substrate surface deposit one layer thickness;
(2d) the photoetching base utilizes dry etching, and etching the degree of depth is the zone, base of 200nm;
(2e) utilize the method for chemical vapor deposition (CVD), at 600 ℃, growth one layer thickness is the SiGe layer of 20nm on substrate, and as the base, this layer Ge component is 15%, and doping content is 5 * 10 18Cm -3
(2f) utilize the method for chemical vapor deposition (CVD), at 600 ℃, the unadulterated intrinsic Si layer of growth one layer thickness 10nm on substrate;
(2g) utilize the method for chemical vapor deposition (CVD), at 600 ℃, the unadulterated intrinsic Poly-Si layer of growth one layer thickness 200nm on substrate;
Step 3, the implementation method of device deep trench isolation preparation is:
(3a) utilizing the method for chemical vapor deposition (CVD), at 600 ℃, is the SiO of 200nm at substrate surface deposit one layer thickness 2Layer;
(3b) utilizing the method for chemical vapor deposition (CVD), at 600 ℃, is the SiN layer of 100nm at substrate surface deposit one layer thickness;
(3c) deep trench isolation zone between the lithographic device, dry etching goes out the shallow slot that the degree of depth is 5um in the deep trench isolation zone;
(3d) utilize chemical vapor deposition (CVD) method,, in deep trouth, fill SiO at 600 ℃ 2, form the device deep trench isolation;
Step 4, the implementation method of collector electrode shallow-trench isolation preparation is:
(4a) fall surperficial SiO with wet etching 2With the SiN layer;
(4b) utilizing the method for chemical vapor deposition (CVD), at 600 ℃, is the SiO of 200nm at substrate surface deposit one layer thickness 2Layer;
(4c) utilizing the method for chemical vapor deposition (CVD), at 600 ℃, is the SiN layer of 100nm at substrate surface deposit one layer thickness;
(4d) photoetching collector electrode shallow trench isolation areas goes out the shallow slot that the degree of depth is 180nm at the shallow trench isolation areas dry etching;
(4e) utilize chemical vapor deposition (CVD) method,, in shallow slot, fill SiO at 600 ℃ 2, form the collector electrode shallow-trench isolation;
Step 5, the implementation method of base stage shallow-trench isolation preparation is:
(5a) fall surperficial SiO with wet etching 2With the SiN layer;
(5b) utilizing the method for chemical vapor deposition (CVD), at 600 ℃, is the SiO of 200nm at substrate surface deposit one layer thickness 2Layer;
(5c) utilizing the method for chemical vapor deposition (CVD), at 600 ℃, is the SiN layer of 100nm at substrate surface deposit one layer thickness;
(5d) photoetching base stage shallow trench isolation areas goes out the shallow slot that the degree of depth is 215nm at the shallow trench isolation areas dry etching;
(5e) utilize chemical vapor deposition (CVD) method,, in shallow slot, fill SiO at 600 ℃ 2, form the base stage shallow-trench isolation;
Step 6, the implementation method that SiGe HBT forms is:
(6a) fall surperficial SiO with wet etching 2With the SiN layer;
(6b) utilizing the method for chemical vapor deposition (CVD), at 600 ℃, is the SiO of 300nm at substrate surface deposit one layer thickness 2Layer;
(6c) photoetching base region carries out p type impurity to this zone and injects, and making the contact zone doping content is 1 * 10 19Cm -3, form base stage;
(6d) photoetching emitter region is carried out N type impurity to this zone and is injected, and making doping content is 1 * 10 17Cm -3, form the emitter region;
(6e) photoetching collector region, and utilize the method for chemico-mechanical polishing (CMP), remove intrinsic Si layer and the intrinsic Poly-Si layer of collector region, the injection of N type impurity is carried out in this zone, making collector electrode contact zone doping content is 1 * 10 19Cm -3, form collector electrode;
(6f) to substrate under 950 ℃ of temperature, annealing 120s carries out impurity activation, forms SiGe HBT;
Step 7, the implementation method of nmos device active area preparation is:
(7a) utilize chemical vapor deposition (CVD) method, at 600 ℃, at substrate surface deposit one deck SiO 2
(7b) photoetching nmos device active area utilizes dry etch process, at the nmos device active area, etches the deep trouth that the degree of depth is 1.7 μ m, oxide layer is carved pass through;
(7c) utilizing the method for chemical vapor deposition (CVD), at 600 ℃, is the P type Si resilient coating of 200nm along (100) crystal face layer thickness of growing in deep trouth, and doping content is 1 * 10 15Cm -3
(7d) utilize the method for chemical vapor deposition (CVD), at 600 ℃, growth one layer thickness is the SiGe of the P type Ge component trapezoidal profile of 1.3 μ m on the P type resilient coating, and bottom Ge component is 0%, and the top is 15%, and doping content is 1 * 10 15Cm -3
(7e) utilize the method for chemical vapor deposition (CVD), at 600 ℃, growth one layer thickness is the P type SiGe layer of 200nm on the SiGe layer of Ge component trapezoidal profile, and the Ge component is 15%, and doping content is 5 * 10 16Cm -3
(7f) utilize chemical vapor deposition (CVD) method, at 600 ℃, growth one layer thickness is the strain Si layer of 20nm on the SiGe layer, and doping content is 5 * 10 16Cm -3, as the raceway groove of nmos device;
(7g) utilize wet etching, etch away the layer SiO on surface 2
Step 8, the implementation method of PMOS device active region preparation is:
(8a) utilize chemical vapor deposition (CVD) method, at 600 ℃, at substrate surface deposit one deck SiO 2
(8b) photoetching PMOS device area utilizes the method for chemical vapor deposition (CVD), and at 600 ℃, growth one layer thickness is the P type SiGe layer of 20nm on the Si resilient coating, and the Ge component is 15%, and doping content is 5 * 10 16Cm -3
(8c) utilize the method for chemical vapor deposition (CVD), at 600 ℃, growth one layer thickness is the intrinsic relaxation Si cap layer of 5nm on the strain SiGe layer, forms the PMOS device active region;
(8d) utilize wet etching, etch away the layer SiO on surface 2
The implementation method that step 9, MOS device grids and lightly-doped source are leaked (LDD) preparation is:
(9a) at 300 ℃, on active area with the method deposit HfO of atomic layer chemical vapour deposition (ALCVD) 2Layer, thickness is 6nm, as the gate medium of nmos device and PMOS device;
(9b) utilize chemical vapor deposition (CVD) method, at 600 ℃, the Poly-SiGe of deposit one deck intrinsic on gate dielectric layer, thickness is 100nm, the Ge component is 10%;
(9c) photoetching MOS device gate medium and grid polycrystalline form grid;
(9d) photoetching nmos device active area carries out N type ion to the nmos device active area and injects, and forming doping content is 1 * 10 18Cm -3N type lightly-doped source drain structure (N-LDD) zone;
(9e) photoetching PMOS device active region carries out P type ion to the PMOS device active region and injects, and forming doping content is 1 * 10 18Cm -3P type lightly-doped source drain structure (P-LDD) zone;
Step 10, the implementation method that the MOS device forms is:
(10a) utilize chemical vapor deposition (CVD) method, at 600 ℃, deposit one thickness is the SiO of 3nm on entire substrate 2Layer;
(10b) utilize dry etch process, this layer of eating away SiO 2, keep nmos device and PMOS device grids side wall;
(10c) photoetching nmos device active area carries out N type ion at the nmos device active area and injects, and autoregistration generates source, drain region and the grid of nmos device;
(10d) photoetching PMOS device active region carries out N type ion at the PMOS device active region and injects, and autoregistration generates source, drain region and the grid of PMOS device;
Step 11, the implementation method that constitutes the BiCMOS integrated circuit is:
(11a) with chemical vapor deposition (CVD) method, at 600 ℃, the thick SiO of deposit 300nm on entire substrate 2Layer;
(11b) photoetching lead-in wire window, sputter layer of metal titanium (Ti) on entire substrate, alloy, autoregistration forms metal silicide, and the metal that clean surface is unnecessary forms the device metal contact;
(11c) splash-proofing sputtering metal; The photoetching lead-in wire; Form drain electrode, source electrode, the gate electrode of MOS device, and bipolar transistor emitter, base stage, collector electrode metal lead-in wire, finally constituting conducting channel is two polycrystalline SOI BiCMOS integrated devices and the circuit based on crystal face selection of 22nm.
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