CN102737985A - 半导体构件的制造方法 - Google Patents

半导体构件的制造方法 Download PDF

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CN102737985A
CN102737985A CN2011101442195A CN201110144219A CN102737985A CN 102737985 A CN102737985 A CN 102737985A CN 2011101442195 A CN2011101442195 A CN 2011101442195A CN 201110144219 A CN201110144219 A CN 201110144219A CN 102737985 A CN102737985 A CN 102737985A
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material layer
semiconductor component
opening
manufacturing approach
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廖建茂
陈逸男
刘献文
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Nanya Technology Corp
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321After treatment
    • H01L21/32115Planarisation
    • H01L21/3212Planarisation by chemical mechanical polishing [CMP]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/7684Smoothing; Planarisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76898Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate

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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)

Abstract

一种半导体构件的制造方法,包括下列步骤。首先,提供基底,基底中已形成有开口。接着,于基底上形成材料层,且材料层填满开口,而位于开口外部且位于开口上方的材料层中具有凹陷。然后,于凹陷的表面上形成牺牲层。接下来,进行化学机械研磨处理,以移除牺牲层及位于开口外部的材料层,其特征在于化学机械研磨处理对材料层的研磨速率大于对牺牲层的研磨速率。本发明可提升经研磨后的材料层的表面平坦度并抑制碟形效应的产生,进而提升所形成的半导体构件的可靠度。

Description

半导体构件的制造方法
技术领域
本发明涉及一种半导体构件的制造方法,且特别涉及一种可降低阶梯高度(step height)的半导体构件的制造方法。
背景技术
随着元件尺寸持续缩减,微影曝光解析度相对增加,伴随着曝光景深的缩减,对于晶片表面的高低起伏程度的要求更为严苛。因此在进入深次微米的处理时,晶片的平坦化就依赖化学机械研磨处理来完成,它独特的非等向性磨除性质除了用于晶片表面轮廓的平坦化之外,亦可应用于垂直及水平金属内连线的镶嵌结构的制作、前段处理中元件浅沟渠隔离制作及先进元件的制作、微机电系统平坦化和平面显示器制作等。
化学机械研磨主要是利用研浆中的化学助剂(reagent),在晶圆的正面上产生化学反应,形成易研磨层,再配合晶圆在研磨垫上,藉由研浆中的研磨粒(abrasive particles)辅助的机械研磨,将易研磨层的突出部份研磨,反复上述化学反应与机械研磨,即可形成平坦的表面。
在填洞(gap-filling)处理时,常会选择使用化学机械研磨法移除位于开口外部的多余材料层。然而,当开口的深宽比(aspect ratio)太高时,会在开口上方的材料层中形成凹陷。若凹陷的阶梯高度过高(如微米(μm)级),进行化学机械研磨处理并无法将凹陷平坦化。因此,在填入开口内的材料层中会产生碟形效应(dishing effect),而导致材料层的平坦化程度不佳,进而降低所形成的半导体构件的可靠度。
发明内容
本发明提供一种半导体构件的制造方法,其可降低阶梯高度且抑制碟形效应的产生。
本发明提出一种半导体构件的制造方法,包括下列步骤。首先,提供基底,基底中已形成有开口。接着,于基底上形成材料层,且材料层填满开口,而位于开口外部且位于开口上方的材料层中具有凹陷。然后,于凹陷的表面上形成牺牲层。接下来,进行化学机械研磨处理,以移除牺牲层及位于开口外部的材料层,其中化学机械研磨处理对材料层的研磨速率大于对牺牲层的研磨速率。
依照本发明的一实施例所述,在上述的半导体构件的制造方法中,开口的深度例如是70μm至150μm。
依照本发明的一实施例所述,在上述的半导体构件的制造方法中,开口的宽度例如是10μm至40μm。
依照本发明的一实施例所述,在上述的半导体构件的制造方法中,开口的深宽比例如是1.8至15。
依照本发明的一实施例所述,在上述的半导体构件的制造方法中,凹陷的阶梯高度例如是2μm至4μm。
依照本发明的一实施例所述,在上述的半导体构件的制造方法中,材料层的材料例如是金属材料。
依照本发明的一实施例所述,在上述的半导体构件的制造方法中,牺牲层的形成方法包括下列步骤。首先,于材料层上形成牺牲材料层。接着,移除位于凹陷外部的牺牲材料层。
依照本发明的一实施例所述,在上述的半导体构件的制造方法中,位于凹陷外部的牺牲材料层的移除方法例如是化学机械研磨法。
依照本发明的一实施例所述,在上述的半导体构件的制造方法中,牺牲层的材料例如是介电材料。
依照本发明的一实施例所述,在上述的半导体构件的制造方法中,半导体构件例如是硅通孔(through-silicon via,TSV)结构。
基于上述,在本发明所提出的半导体构件的制造方法中,由于会在材料层中的凹陷表面上形成牺牲层,且化学机械研磨处理对材料层的研磨速率大于对牺牲层的研磨速率,所以可有效地降低材料层的凹陷处的阶梯高度。因此,本发明所提出的半导体构件的制造方法可提升经研磨后的材料层的表面平坦度并抑制碟形效应的产生,进而提升所形成的半导体构件的可靠度。
为让本发明的上述特征能更明显易懂,下文特举实施例,并配合附图式详细说明如下。
附图说明
图1A至图1D为本发明一实施例的半导体构件的制造流程剖面图。
主要元件符号说明:
100:基底
100a:背面
102:开口
104:材料层
106:凹陷
108:牺牲材料层
110:牺牲层
112:半导体构件
D:深度
H1:阶梯高度
H2:高度
W:宽度
具体实施方式
图1A至图1D为本发明一实施例的半导体构件的制造流程剖面图。在此实施例中,半导体构件例如是用以形成半导体元件的构件,如电极、导线、接触窗插塞、介层窗插塞或硅通孔结构等构件。
首先,请参照图1A,提供基底100,基底100中已形成有开口102。基底100例如是硅基底。开口102的形成方法例如是对基底100进行微影处理及蚀刻处理所形成。
接着,于基底100上形成材料层104,且材料层104填满开口102,而位于开口102外部且位于开口102上方的材料层104中具有凹陷106。材料层104的材料例如是铜等金属材料。材料层104的形成方法例如是物理气相沉积法。开口102的深度D例如是70μm至150μm。开口102的宽度W例如是10μm至40μm。开口102的深宽比例如是1.8至15。凹陷106的阶梯高度H1例如是2μm至4μm。
然后,于材料层104上形成牺牲材料层108。牺牲材料层108的材料与材料层104的材料互不相同。牺牲材料层108的材料例如是介电材料、光阻或多晶硅。介电材料例如是氮化物或氧化物。
接下来,请参照图1B,移除位于凹陷106外部的牺牲材料层108,以于凹陷106的表面上形成牺牲层110。位于凹陷106外部的牺牲材料层108的移除方法例如是化学机械研磨法。虽然牺牲层110是以上述方法所形成,但牺牲层110的形成方法并不以此为限。
之后,请参照图1C,进行化学机械研磨处理,以移除牺牲层110及位于开口102外部的材料层104,而由位于开口102中的材料层104形成半导体构件112。其中,化学机械研磨处理对材料层104的研磨速率大于对牺牲层110的研磨速率。由于化学机械研磨处理对材料层104的研磨速率大于对牺牲层110的研磨速率,因此可有效地降低凹陷106的阶梯高度H1,以使得所形成的半导体构件112具有平坦的表面。在此实施例中,半导体构件112例如是用以形成半导体元件的构件,如电极、导线、接触窗插塞、介层窗插塞或硅通孔结构等。
当半导体构件112为硅通孔结构时,请接着参照图1D,更包括从基底100的背面100a移除部分基底100,直到暴露出半导体构件112为止。此时,半导体构件112的高度H2可由部分基底100的移除程度来决定,高度H2例如是30μm至60μm。部分基底100的移除方法例如是化学机械研磨法。
值得注意的是,在此实施例中虽然是以材料层104的材料为金属材料且牺牲层110的材料为介电材料为例进行说明,但并不用以限制本发明的范围。此技术领域中的普通技术人员可依据所要形成的半导体构件112来决定材料层104的材料,只要材料层104的材料与牺牲层110的材料具有不同的研磨速率,即属于本发明所保护的范围。
此外,材料层104与基底100之间更可选择性地形成其他膜层,如介电层(未显示)或阻障层(未显示)等,此技术领域具中的普通技术人员可依据所要形成的半导体构件112进行设计。
基于上述实施例可知,由于在材料层104中的凹陷106表面上形成牺牲层110,且化学机械研磨处理对材料层104的研磨速率大于对牺牲层110的研磨速率,所以可有效地降低材料层104的凹陷106处的阶梯高度H1。藉此,可提升经研磨后的材料层104的表面平坦度并抑制碟形效应的产生,进而获得具有高可靠度的半导体构件112。
综上所述,上述实施例的半导体构件的制造方法至少具有下列特征:
1.上述实施例的半导体构件的制造方法可有效地降低材料层的凹陷处的阶梯高度。
2.藉由上述实施例的半导体构件的制造方法可提升所形成的半导体构件的可靠度。
虽然本发明已以实施例揭示如上,然其并非用以限定本发明,任何所属技术领域中的普通技术人员,当可作些许的更动与润饰,而不脱离本发明的精神和范围。

Claims (10)

1.一种半导体构件的制造方法,包括:
提供一基底,该基底中已形成有一开口;
于该基底上形成一材料层,且该材料层填满该开口,而位于该开口外部且位于该开口上方的该材料层中具有一凹陷;
于该凹陷的表面上形成一牺牲层;以及
进行一化学机械研磨处理,以移除该牺牲层及位于该开口外部的该材料层,其特征在于该化学机械研磨处理对该材料层的研磨速率大于对该牺牲层的研磨速率。
2.根据权利要求1所述的半导体构件的制造方法,其特征在于该开口的深度为70μm至150μm。
3.根据权利要求1所述的半导体构件的制造方法,其特征在于该开口的宽度为10μm至40μm。
4.根据权利要求1所述的半导体构件的制造方法,其特征在于该开口的深宽比为1.8至15。
5.根据权利要求1所述的半导体构件的制造方法,其特征在于该凹陷的阶梯高度为2μm至4μm。
6.根据权利要求1所述的半导体构件的制造方法,其特征在于该材料层的材料包括金属材料。
7.根据权利要求1所述的半导体构件的制造方法,其特征在于该牺牲层的形成方法包括:
于该材料层上形成一牺牲材料层;以及
移除位于该凹陷外部的该牺牲材料层。
8.根据权利要求7所述的半导体构件的制造方法,其特征在于位于该凹陷外部的该牺牲材料层的移除方法包括化学机械研磨法。
9.根据权利要求1所述的半导体构件的制造方法,其特征在于该牺牲层的材料包括介电材料。
10.根据权利要求1所述的半导体构件的制造方法,其特征在于该半导体构件包括硅通孔结构。
CN2011101442195A 2011-04-13 2011-05-31 半导体构件的制造方法 Pending CN102737985A (zh)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105449101A (zh) * 2014-09-01 2016-03-30 中芯国际集成电路制造(上海)有限公司 相变存储器单元的形成方法

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6383935B1 (en) * 2000-10-16 2002-05-07 Taiwan Semiconductor Manufacturing Company Method of reducing dishing and erosion using a sacrificial layer
US20020142582A1 (en) * 2001-03-30 2002-10-03 Kim Kil Ho Method for forming copper lines for semiconductor devices
US20040259348A1 (en) * 2001-02-27 2004-12-23 Basol Bulent M. Method of reducing post-CMP defectivity

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5618381A (en) * 1992-01-24 1997-04-08 Micron Technology, Inc. Multiple step method of chemical-mechanical polishing which minimizes dishing
US5885900A (en) * 1995-11-07 1999-03-23 Lucent Technologies Inc. Method of global planarization in fabricating integrated circuit devices
US6103592A (en) * 1997-05-01 2000-08-15 International Business Machines Corp. Manufacturing self-aligned polysilicon fet devices isolated with maskless shallow trench isolation and gate conductor fill technology with active devices and dummy doped regions formed in mesas
US6051496A (en) * 1998-09-17 2000-04-18 Taiwan Semiconductor Manufacturing Company Use of stop layer for chemical mechanical polishing of CU damascene
US7686935B2 (en) * 1998-10-26 2010-03-30 Novellus Systems, Inc. Pad-assisted electropolishing
US6251788B1 (en) * 1999-05-03 2001-06-26 Winbond Electronics Corp. Method of integrated circuit polishing without dishing effects
US6383933B1 (en) * 2000-03-23 2002-05-07 National Semiconductor Corporation Method of using organic material to enhance STI planarization or other planarization processes
US6559033B1 (en) * 2001-06-27 2003-05-06 Lsi Logic Corporation Processing for forming integrated circuit structure with low dielectric constant material between closely spaced apart metal lines
US6548399B1 (en) * 2001-11-20 2003-04-15 Intel Corporation Method of forming a semiconductor device using a carbon doped oxide layer to control the chemical mechanical polishing of a dielectric layer
US7217649B2 (en) * 2003-03-14 2007-05-15 Lam Research Corporation System and method for stress free conductor removal
US7078344B2 (en) * 2003-03-14 2006-07-18 Lam Research Corporation Stress free etch processing in combination with a dynamic liquid meniscus
US7825024B2 (en) * 2008-11-25 2010-11-02 Taiwan Semiconductor Manufacturing Company, Ltd. Method of forming through-silicon vias
US8586481B2 (en) * 2010-06-01 2013-11-19 Applied Materials, Inc. Chemical planarization of copper wafer polishing
US8273610B2 (en) * 2010-11-18 2012-09-25 Monolithic 3D Inc. Method of constructing a semiconductor device and structure
KR101767654B1 (ko) * 2011-05-19 2017-08-14 삼성전자주식회사 에어 갭 절연 구조를 갖는 관통전극을 구비한 반도체 소자 및 그 제조방법

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6383935B1 (en) * 2000-10-16 2002-05-07 Taiwan Semiconductor Manufacturing Company Method of reducing dishing and erosion using a sacrificial layer
US20040259348A1 (en) * 2001-02-27 2004-12-23 Basol Bulent M. Method of reducing post-CMP defectivity
US20020142582A1 (en) * 2001-03-30 2002-10-03 Kim Kil Ho Method for forming copper lines for semiconductor devices

Cited By (2)

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CN105449101A (zh) * 2014-09-01 2016-03-30 中芯国际集成电路制造(上海)有限公司 相变存储器单元的形成方法
CN105449101B (zh) * 2014-09-01 2018-06-01 中芯国际集成电路制造(上海)有限公司 相变存储器单元的形成方法

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