CN102709312B - Oxide thin-film, thin-film transistor and preparation method thereof - Google Patents
Oxide thin-film, thin-film transistor and preparation method thereof Download PDFInfo
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- CN102709312B CN102709312B CN201210125134.7A CN201210125134A CN102709312B CN 102709312 B CN102709312 B CN 102709312B CN 201210125134 A CN201210125134 A CN 201210125134A CN 102709312 B CN102709312 B CN 102709312B
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Abstract
The invention discloses an oxide thin-film, a thin-film transistor and a preparation method thereof. The invention relates to the technical field of the thin-film transistor. In the thin-film transistor, the chemical general formula of the oxide thin-film of the oxide thin-film channel layer is In-X-Zn-O, wherein X is Si element, Ge element, La element or Y element; a gate electrode is arranged over a substrate; a gate insulation layer is arranged at the gate electrode, and over the portion of the substrate not covered by the gate electrode; the oxide thin-film channel layer is arranged over the gate insulation layer; a source electrode area is arranged at one side of the upper of the oxide thin-film channel layer; and the leakage electrode area is arranged at the side of the upper of the oxide thin-film channel layer. Based on the In-X-Zn-O thin-film transistor, the invention can enhance the inhibiting ability of the oxide thin-film channel layer to the formation of a charge carrier, improves the crystallization temperature of a crystal so as to improve the consistency of element preparation, and weakens the effects of the oxide thin-film channel layer to the threshold voltage, leakage current Ioff and on-off time ratio of the thin-film transistor.
Description
Technical field
The present invention relates to thin-film transistor technologies field, particularly a kind of sull, thin-film transistor and preparation method thereof.
Background technology
In Display Technique, conventionally can adopt in a large number thin-film transistor built-up circuit to drive display unit.And in the past in long time, what adopt is all and the silicon based material of CMOS (Complementary Metal Oxide Semiconductor, complementary metal oxide semiconductors (CMOS)) process compatible always.
Yet the light transmission of silicon based material is poor.And when these silicon based materials of preparation, compare the film forming of the amorphous silicon that can prepare at low temperatures with polysilicon, also need approximately 200 ℃ of above high temperature.Therefore, can not use and have cheapness, the polymer film of light weight, this advantage of pliability is as base material.Thereby, exist the more significant shortcomings such as heating cost is high, preparation time is long.
In view of silica-based TFT (Thin Film Transistor, Thin Film Transistor (TFT), i.e. thin-film transistor) device exists above-mentioned shortcoming, the semiconductor that can replace silicon based material is being found always and developed to scientists in recent ten years.Transparent oxide semiconductor material is because it can realize film formation at low temp, and has the excellent characteristics such as higher mobility, has been a great concern.Wherein, as list of references K.Nomura et al. " Room-temperature fabrication of transparent flexible thin-film transistors using amorphous oxide semiconductors ", Nature, 432, described in p488-492 (2004), the In-Ga-Zn-O film forming with In, Ga, Zn element, because it compares the ZnO semiconductor using with tradition, there is less cut-off current, larger switch current ratio and higher mobility, become the focus of research gradually.
But, due in In-Ga-Zn-O membrane structure, Ga element is with the associativity problem of O element, and in the channel layer that makes to form, oxygen room is more, the inhibition ability forming for charge carrier a little less than, to thin-film transistor threshold voltage, leakage current I
offand on-off ratio has larger impact.
Summary of the invention
(1) technical problem that will solve
The technical problem to be solved in the present invention is: how a kind of sull, thin-film transistor and preparation method thereof are provided, the inhibition ability forming for charge carrier with the channel layer that overcomes existing thin-film transistor a little less than, to thin-film transistor threshold voltage, leakage current I
offand on-off ratio affects large problem.
(2) technical scheme
For solving the problems of the technologies described above, the invention provides a kind of sull, the chemical general formula of described sull is In-X-Zn-O, wherein, X is Si, Ge, La or Y element.
Preferably, in described sull, also doped with at least one in metallic element titanium, aluminium, magnesium, zirconium, hafnium, praseodymium, cerium or neodymium, and the content of the metallic element adulterating is lower than the content of described X.
The present invention also provides a kind of thin-film transistor, and described thin-film transistor comprises sull channel layer; The chemical general formula of the sull that described sull channel layer adopts is In-X-Zn-O, and wherein, X is Si, Ge, La or Y element.
Preferably, in described sull, also doped with at least one in metallic element titanium, aluminium, magnesium, zirconium, hafnium, praseodymium, cerium or neodymium, and the content of the metallic element adulterating is lower than the content of described X.
Preferably, described thin-film transistor is bottom gate alternating expression thin-film transistor;
Described bottom gate alternating expression thin-film transistor also comprises: substrate, gate electrode, gate insulator, source area and drain region;
Described gate electrode is arranged on described substrate top;
Described gate insulator is arranged on described gate electrode and described substrate not by the top of the part that described gate electrode covered;
Described sull channel layer is arranged on the top of described gate insulator;
Described source area is arranged on a side of the top of described sull channel layer;
Described drain region is arranged on the opposite side of the top of described sull channel layer.
Preferably, described thin-film transistor is the coplanar formula thin-film transistor of bottom gate;
The coplanar formula thin-film transistor of described bottom gate also comprises: substrate, gate electrode, gate insulator, source area and drain region;
Described gate electrode is arranged on described substrate top;
Described gate insulator is arranged on described gate electrode and described substrate not by the top of the part that described gate electrode covered;
Described source area is arranged on a side of the top of described gate insulator;
Described drain region is arranged on the opposite side of the top of described gate insulator;
Described sull channel layer is arranged on described source area and described drain region and described gate insulator not by the top of the part that described source area and described drain region covered.
Preferably, described thin-film transistor is top grid alternating expression thin-film transistor;
Described top grid alternating expression thin-film transistor also comprises: substrate, gate electrode, gate insulator, source area and drain region;
Described source area is arranged on a side of the top of described substrate;
Described drain region is arranged on the opposite side of the top of described substrate;
Described sull channel layer is arranged on described source area and described drain region and described substrate not by the top of the part that described source area and described drain region covered;
Described gate insulator is arranged on the top of described sull channel layer;
Described gate electrode is arranged on the top of described gate insulator.
Preferably, described thin-film transistor is the coplanar formula thin-film transistors of top grid;
Grid coplanar formula thin-film transistor in described top also comprises: substrate, gate electrode, gate insulator, source area and drain region;
Described sull channel layer is arranged on the top of described substrate;
Described source area is arranged on a side of the top of described sull channel layer;
Described drain region is arranged on the opposite side of the top of described sull channel layer;
Described gate insulator is arranged on described sull channel layer not by the top of the part that described source area and described drain region covered;
Described gate electrode is arranged on the top of described gate insulator.
The present invention also provides a kind of film crystal tube preparation method, comprises step:
A: clean substrate;
B: form gate electrode above described substrate;
C: form gate insulator above not by part that described gate electrode covered in described gate electrode and described substrate;
D: form sull channel layer above described gate insulator; The chemical general formula of the sull that described sull channel layer adopts is In-X-Zn-O, and wherein, X is Si, Ge, La or Y element;
E: make described gate electrode exposed by etching, then the both sides above described sull channel layer form respectively source area and drain region.
Preferably, described step D specifically comprises: use magnetically controlled sputter method, to In
2o
3, the oxide of X element, ZnO apply voltage, carries out cosputtering, forms the sull that chemical general formula is In-X-Zn-O above described gate insulator, wherein, X is Si, Ge, La or Y element.
(3) beneficial effect
Thin-film transistor based on In-X-Zn-O of the present invention has advantage: adopt the sull channel layer based on In-X-Zn-O, can strengthen the inhibition ability that sull channel layer forms for charge carrier, reduce thin-film transistor threshold voltage, leakage current I
offand the impact of on-off ratio; Guaranteeing, in the reliability and electrology characteristic basis of thin-film transistor, to make the sull channel layer of thin-film transistor have material range of choice widely; And by the doping of other elements, can modulate the characteristic of the sull channel layer based on In-X-Zn-O, further improve reliability and the electrology characteristic of thin-film transistor; Can improve the crystallization temperature of material, be conducive to form at low temperatures amorphous film, be conducive to guarantee consistency prepared by device, the stability of improving the device of manufacturing by low temperature process.
Accompanying drawing explanation
Fig. 1 is the bottom gate alternating expression thin-film transistor structure schematic diagram described in the first embodiment of the present invention;
Fig. 2 is preparation method's flow chart of bottom gate alternating expression thin-film transistor described in the first embodiment of the present invention;
Fig. 3 is the coplanar formula thin-film transistor structure of the bottom gate schematic diagram described in the second embodiment of the present invention;
Fig. 4 is the top grid alternating expression thin-film transistor structure schematic diagram described in the third embodiment of the present invention;
Fig. 5 is the coplanar formula thin-film transistor structure of the top grid schematic diagram described in the 4th kind of embodiment of the present invention.
Embodiment
Below in conjunction with drawings and Examples, the specific embodiment of the present invention is described in further detail.Following examples are used for illustrating the present invention, but are not used for limiting the scope of the invention.
Embodiment 1
Fig. 1 is bottom gate alternating expression thin-film transistor (the TFT with inverted staggered structure) structural representation described in the first embodiment of the present invention, as shown in Figure 1, described bottom gate alternating expression thin-film transistor comprises: substrate 11, gate electrode 12, gate insulator 13, sull channel layer 14,15He drain region, source area 16.
Described gate electrode 12 is arranged on the top of described substrate 11.Described substrate 11 can adopt silicon, glass or plastics.
Described gate insulator 13 is arranged on the top of the part that described gate electrode 12 and described substrate 11 do not covered by described gate electrode 12.
Described sull channel layer 14 is arranged on the top of described gate insulator 13.The chemical general formula of the sull that described sull channel layer 14 adopts is In-X-Zn-O, and wherein, X is Si, Ge, La or Y element.In described sull, also doped with at least one in metallic element titanium, aluminium, magnesium, zirconium, hafnium, praseodymium, cerium or neodymium, and the content of the metallic element adulterating is lower than the content of described X.Preparation for described sull, can be by simultaneously applying voltage and cosputtering forms to the oxide of the oxide of In, the oxide of Zn and X, and can control In, Zn and the atomic concentration of each element of X in the described sull forming by controlling the intensity of voltage.But, it is pointed out that the method that forms described sull is not limited to this kind of specific sputtering method, any can the use in the several different methods other method such as dry method (printing) or wet method (sol-gal process).The method that at least one doping in metallic element titanium, aluminium, magnesium, zirconium, hafnium, praseodymium, cerium and neodymium is added in described sull is not limited to specific method, can use any in the several different methods of dry method or wet method and so on.Preferential use ion injection method or ion doping method, or sol-gal process.
Described source area 15 is arranged on a side of the top of described sull channel layer 14;
Described drain region 16 is arranged on the opposite side of the top of described sull channel layer 14.
Described gate electrode 12, described source area 15 and described drain region 16 can adopt metal (as Ti, Pt, Ru, Cu, Au, Ag, Mo, Cr, Al, Ta, W or their alloy) or conductive oxide (as being tin oxide, zinc oxide, indium oxide, tin indium oxide, indium zinc oxide, gallium oxide zinc or aluminum zinc oxide).Described gate insulator 13 can be such as SiO
2, Si
3n
4, SiON, HfO
2, Al
2o
3, Y
2o
3or Ta
2o
5and so on dielectric material, high-k dielectric material or their mixture.
Fig. 2 is preparation method's flow chart of bottom gate alternating expression thin-film transistor described in the first embodiment of the present invention, and as shown in Figure 2, described method comprises step:
A: clean substrate: use supersonic cleaning machine to clean substrate of glass, first substrate of glass is immersed in acetone to heating water bath to 50 ℃, ultrasonic 5 minutes; Again substrate of glass is immersed in absolute ethyl alcohol to heating water bath to 50 ℃, ultrasonic 5 minutes.
B: forming gate electrode above described substrate: make gate electrode area by lithography above described substrate, adopt ITO (the Indium Tin Oxides of magnetron sputtering technique growth one deck 50～300 nanometer thickness, nano indium tin metal oxide) conductive film, uses stripping means to form gate electrode.
C: form gate insulator in described gate electrode and described substrate above not by part that described gate electrode covered: described gate electrode and described substrate not by part that described gate electrode covered above, adopt PECVD (Plasma Enhanced Chemical Vapor Deposition, plasma enhanced chemical vapor deposition method) the folded gate dielectric layer of the silicon dioxide of technology or magnetron sputtering technique or ALD (Atomic layer deposition, ald) technology growth one deck 50～200 nanometer thickness.
D: form sull channel layer above described gate insulator: use magnetically controlled sputter method, to In
2o
3, X element oxide (can be SiO
2, GeO
2, La
2o
3, Y
2o
3), ZnO applies voltage, carries out cosputtering, the sull that the chemical general formula that forms approximately 100 nanometers left and right above described gate insulator is In-X-Zn-O, wherein, X is Si, Ge, La or Y element.
E: make described gate electrode exposed by etching, then the both sides above described sull channel layer form respectively source area and drain region: the above-mentioned made sample of getting ready is carried out to photoetching, use watery hydrochloric acid to etch away a part of sull channel layer, photoetching fall the described gate insulator of appropriate section with hf etching again, exposes described gate electrode; Then, adopt PVD (Physical Vapor Deposition, physical vapour deposition (PVD)) the ITO conductive film of technique deposit one deck 50～300 nanometer thickness, uses stripping means to form described source area and drain region, has just obtained the TFT device of required preparation.
Experimental result shows, by the prepared bottom gate alternating expression thin-film transistor of method described in the embodiment of the present invention, expects that its cut-off current can reach 6 * 10
-12a, on-off ratio is 3 * 10
5, mobility can reach 12cm
2/ (Vs), defect state density is 8 * 10
11, can be used as a kind of TFT device of better performances.
Embodiment 2
Fig. 3 is the coplanar formula thin-film transistor of the bottom gate described in the second embodiment of the present invention (TFT with inverted staggered structure) structural representation, as shown in Figure 3, the coplanar formula thin-film transistor of described bottom gate comprises: substrate 21, gate electrode 22, gate insulator 23, sull channel layer 24,25He drain region, source area 26.Each parts in the coplanar formula thin-film transistor of described bottom gate are identical with the material that each parts in the thin-film transistor of bottom gate alternating expression described in embodiment mono-adopt, and its difference is that the structure between each parts is as follows:
Described gate electrode 22 is arranged on described substrate 21 tops;
Described gate insulator 23 is arranged on the top of the part that described gate electrode 22 and described substrate 21 do not covered by described gate electrode 22;
Described source area 25 is arranged on a side of the top of described gate insulator 23;
Described drain region 26 is arranged on the opposite side of the top of described gate insulator 23;
Described sull channel layer 24 is arranged on the top of the part that described source area 25 and described drain region 26 and described gate insulator 23 do not covered by described source area 25 and described drain region 26.
According to the architectural feature of the coplanar formula thin-film transistor of described bottom gate, those skilled in the art easily expect corresponding preparation method, therefore, at this, its preparation method are repeated no more.
Embodiment 3
Fig. 4 is top grid alternating expression thin-film transistor (the TFT with top gate staggered structure) structural representation described in the third embodiment of the present invention, as shown in Figure 4, described top grid alternating expression thin-film transistor comprises: substrate 31, gate electrode 32, gate insulator 33, sull channel layer 34,35He drain region, source area 36.Each parts in the grid alternating expression thin-film transistor of described top are identical with the material that each parts in the thin-film transistor of bottom gate alternating expression described in embodiment mono-adopt, and its difference is that the structure between each parts is as follows:
Described source area 35 is arranged on a side of the top of described substrate 31;
Described drain region 36 is arranged on the opposite side of the top of described substrate 31;
Described sull channel layer 34 is arranged on the top of the part that described source area 35 and described drain region 36 and described substrate 31 do not covered by described source area 35 and described drain region 36;
Described gate insulator 33 is arranged on the top of described sull channel layer 34;
Described gate electrode 32 is arranged on the top of described gate insulator 33.
According to the architectural feature of described top grid alternating expression thin-film transistor, those skilled in the art easily expect corresponding preparation method, therefore, at this, its preparation method are repeated no more.
Embodiment 4
Fig. 5 is the coplanar formula thin-film transistor of top grid (the TFT with top gate coplanar structure) structural representation described in the 4th kind of embodiment of the present invention, as shown in Figure 5, grid coplanar formula thin-film transistor in described top comprises: substrate 41, gate electrode 42, gate insulator 43, sull channel layer 44,45He drain region, source area 46.Each parts in the coplanar formula thin-film transistor of described top grid are identical with the material that each parts in the thin-film transistor of bottom gate alternating expression described in embodiment mono-adopt, and its difference is that the structure between each parts is as follows:
Described sull channel layer 44 is arranged on the top of described substrate 41;
Described source area 45 is arranged on a side of the top of described sull channel layer 44;
Described drain region 46 is arranged on the opposite side of the top of described sull channel layer 44;
Described gate insulator 43 is arranged on the top of the part that described sull channel layer 44 do not covered by described source area 45 and described drain region 46;
Described gate electrode 42 is arranged on the top of described gate insulator 43.
According to the architectural feature of the coplanar formula thin-film transistor of described top grid, those skilled in the art easily expect corresponding preparation method, therefore, at this, its preparation method are repeated no more.
Than traditional thin-film transistor based on In-Ga-Zn-O, thin-film transistor based on In-X-Zn-O of the present invention has advantage: adopt the sull channel layer based on In-X-Zn-O, can strengthen the inhibition ability that sull channel layer forms for charge carrier, reduce thin-film transistor threshold voltage, leakage current I
offand the impact of on-off ratio; Guaranteeing, in the reliability and electrology characteristic basis of thin-film transistor, to make the sull channel layer of thin-film transistor have material range of choice widely; And by the doping of other elements, can modulate the characteristic of the sull channel layer based on In-X-Zn-O, further improve reliability and the electrology characteristic of thin-film transistor; Can improve the crystallization temperature of material, be conducive to form at low temperatures amorphous film, be conducive to guarantee consistency prepared by device, the stability of improving the device of manufacturing by low temperature process.
Above execution mode is only for illustrating the present invention; and be not limitation of the present invention; the those of ordinary skill in relevant technologies field; without departing from the spirit and scope of the present invention; can also make a variety of changes and modification; therefore all technical schemes that are equal to also belong to category of the present invention, and scope of patent protection of the present invention should be defined by the claims.
Claims (7)
1. a sull, is characterized in that, the chemical general formula of described sull is In-X-Zn-O, and wherein, X is Si, Ge, La or Y element; In described sull, also doped with at least one in metallic element titanium, aluminium, zirconium, hafnium, praseodymium, cerium or neodymium, and the content of the metallic element adulterating is lower than the content of described X.
2. a thin-film transistor, is characterized in that, described thin-film transistor comprises sull channel layer; The chemical general formula of the sull that described sull channel layer adopts is In-X-Zn-O, and wherein, X is Si, Ge, La or Y element; In described sull, also doped with at least one in metallic element titanium, aluminium, zirconium, hafnium, praseodymium, cerium or neodymium, and the content of the metallic element adulterating is lower than the content of described X.
3. thin-film transistor as claimed in claim 2, is characterized in that, described thin-film transistor is bottom gate alternating expression thin-film transistor;
Described bottom gate alternating expression thin-film transistor also comprises: substrate, gate electrode, gate insulator, source area and drain region;
Described gate electrode is arranged on described substrate top;
Described gate insulator is arranged on described gate electrode and described substrate not by the top of the part that described gate electrode covered;
Described sull channel layer is arranged on the top of described gate insulator;
Described source area is arranged on a side of the top of described sull channel layer;
Described drain region is arranged on the opposite side of the top of described sull channel layer.
4. thin-film transistor as claimed in claim 2, is characterized in that, described thin-film transistor is the coplanar formula thin-film transistor of bottom gate;
The coplanar formula thin-film transistor of described bottom gate also comprises: substrate, gate electrode, gate insulator, source area and drain region;
Described gate electrode is arranged on described substrate top;
Described gate insulator is arranged on described gate electrode and described substrate not by the top of the part that described gate electrode covered;
Described source area is arranged on a side of the top of described gate insulator;
Described drain region is arranged on the opposite side of the top of described gate insulator;
Described sull channel layer is arranged on described source area and described drain region and described gate insulator not by the top of the part that described source area and described drain region covered.
5. thin-film transistor as claimed in claim 2, is characterized in that, described thin-film transistor is top grid alternating expression thin-film transistor;
Described top grid alternating expression thin-film transistor also comprises: substrate, gate electrode, gate insulator, source area and drain region;
Described source area is arranged on a side of the top of described substrate;
Described drain region is arranged on the opposite side of the top of described substrate;
Described sull channel layer is arranged on described source area and described drain region and described substrate not by the top of the part that described source area and described drain region covered;
Described gate insulator is arranged on the top of described sull channel layer;
Described gate electrode is arranged on the top of described gate insulator.
6. thin-film transistor as claimed in claim 2, is characterized in that, described thin-film transistor is the coplanar formula thin-film transistors of top grid;
Grid coplanar formula thin-film transistor in described top also comprises: substrate, gate electrode, gate insulator, source area and drain region;
Described sull channel layer is arranged on the top of described substrate;
Described source area is arranged on a side of the top of described sull channel layer;
Described drain region is arranged on the opposite side of the top of described sull channel layer;
Described gate insulator is arranged on described sull channel layer not by the top of the part that described source area and described drain region covered;
Described gate electrode is arranged on the top of described gate insulator.
7. a film crystal tube preparation method, is characterized in that, comprises step:
A: clean substrate;
B: form gate electrode above described substrate;
C: form gate insulator above not by part that described gate electrode covered in described gate electrode and described substrate;
D: form sull channel layer above described gate insulator; The chemical general formula of the sull that described sull channel layer adopts is In-X-Zn-O, wherein, X is Si, Ge, La or Y element, in described sull, also doped with at least one in metallic element titanium, aluminium, zirconium, hafnium, praseodymium, cerium or neodymium, and the content of the metallic element adulterating is lower than the content of described X;
E: make described gate electrode exposed by etching, then the both sides above described sull channel layer form respectively source area and drain region;
Described step D specifically comprises: use magnetically controlled sputter method, to In
2o
3, the oxide of X element, ZnO apply voltage, carries out cosputtering, forms the sull that chemical general formula is In-X-Zn-O above described gate insulator, wherein, X is Si, Ge, La or Y element.
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101872787A (en) * | 2010-05-19 | 2010-10-27 | 华南理工大学 | Metal oxide thin film transistor and preparation method thereof |
| CN102290443A (en) * | 2011-07-28 | 2011-12-21 | 北京大学深圳研究生院 | Amorphous thin film transistor and preparation method thereof |
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| JP5121254B2 (en) * | 2007-02-28 | 2013-01-16 | キヤノン株式会社 | Thin film transistor and display device |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101872787A (en) * | 2010-05-19 | 2010-10-27 | 华南理工大学 | Metal oxide thin film transistor and preparation method thereof |
| CN102290443A (en) * | 2011-07-28 | 2011-12-21 | 北京大学深圳研究生院 | Amorphous thin film transistor and preparation method thereof |
Non-Patent Citations (2)
| Title |
|---|
| 林明通 等.氧化锌基薄膜晶体管最新研究进展.《光电子技术》.2008,第28卷(第4期),218. * |
| 氧化锌基薄膜晶体管最新研究进展;林明通 等;《光电子技术》;20081231;第28卷(第4期);第217-226页 * |
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