CN103762227B - A kind of sull, contain transistor of this film and preparation method thereof - Google Patents
A kind of sull, contain transistor of this film and preparation method thereof Download PDFInfo
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- CN103762227B CN103762227B CN201410031240.8A CN201410031240A CN103762227B CN 103762227 B CN103762227 B CN 103762227B CN 201410031240 A CN201410031240 A CN 201410031240A CN 103762227 B CN103762227 B CN 103762227B
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- sull
- channel layer
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- 238000002360 preparation method Methods 0.000 title claims abstract description 26
- 239000010409 thin film Substances 0.000 claims abstract description 40
- 229910007604 Zn—Sn—O Inorganic materials 0.000 claims abstract description 14
- 239000000758 substrate Substances 0.000 claims description 53
- 239000012212 insulator Substances 0.000 claims description 42
- 238000000034 method Methods 0.000 claims description 30
- 239000010408 film Substances 0.000 claims description 27
- 230000008569 process Effects 0.000 claims description 11
- 229910052751 metal Inorganic materials 0.000 claims description 10
- 238000001755 magnetron sputter deposition Methods 0.000 claims description 8
- 239000011701 zinc Substances 0.000 claims description 7
- 229910021627 Tin(IV) chloride Inorganic materials 0.000 claims description 6
- 238000000231 atomic layer deposition Methods 0.000 claims description 6
- 229910052788 barium Inorganic materials 0.000 claims description 6
- 238000010438 heat treatment Methods 0.000 claims description 6
- 238000004528 spin coating Methods 0.000 claims description 6
- 238000003756 stirring Methods 0.000 claims description 6
- HPGGPRDJHPYFRM-UHFFFAOYSA-J tin(iv) chloride Chemical compound Cl[Sn](Cl)(Cl)Cl HPGGPRDJHPYFRM-UHFFFAOYSA-J 0.000 claims description 6
- 239000010936 titanium Substances 0.000 claims description 6
- 239000004246 zinc acetate Substances 0.000 claims description 6
- -1 zinc acetate compound Chemical class 0.000 claims description 6
- 229910052782 aluminium Inorganic materials 0.000 claims description 5
- DSAJWYNOEDNPEQ-UHFFFAOYSA-N barium atom Chemical compound [Ba] DSAJWYNOEDNPEQ-UHFFFAOYSA-N 0.000 claims description 5
- 239000002184 metal Substances 0.000 claims description 5
- XNWFRZJHXBZDAG-UHFFFAOYSA-N 2-METHOXYETHANOL Chemical compound COCCO XNWFRZJHXBZDAG-UHFFFAOYSA-N 0.000 claims description 4
- 239000004411 aluminium Substances 0.000 claims description 4
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 4
- 238000005660 chlorination reaction Methods 0.000 claims description 4
- 238000005530 etching Methods 0.000 claims description 4
- 229910052719 titanium Inorganic materials 0.000 claims description 4
- 229910052684 Cerium Inorganic materials 0.000 claims description 3
- FYYHWMGAXLPEAU-UHFFFAOYSA-N Magnesium Chemical compound [Mg] FYYHWMGAXLPEAU-UHFFFAOYSA-N 0.000 claims description 3
- 229910052779 Neodymium Inorganic materials 0.000 claims description 3
- 229910052777 Praseodymium Inorganic materials 0.000 claims description 3
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 3
- QCWXUUIWCKQGHC-UHFFFAOYSA-N Zirconium Chemical compound [Zr] QCWXUUIWCKQGHC-UHFFFAOYSA-N 0.000 claims description 3
- ZMIGMASIKSOYAM-UHFFFAOYSA-N cerium Chemical compound [Ce][Ce][Ce][Ce][Ce][Ce][Ce][Ce][Ce][Ce][Ce][Ce][Ce][Ce][Ce][Ce][Ce][Ce][Ce][Ce][Ce][Ce][Ce][Ce][Ce][Ce][Ce][Ce][Ce][Ce][Ce][Ce][Ce][Ce][Ce][Ce][Ce][Ce] ZMIGMASIKSOYAM-UHFFFAOYSA-N 0.000 claims description 3
- 229910052735 hafnium Inorganic materials 0.000 claims description 3
- VBJZVLUMGGDVMO-UHFFFAOYSA-N hafnium atom Chemical compound [Hf] VBJZVLUMGGDVMO-UHFFFAOYSA-N 0.000 claims description 3
- 229910052746 lanthanum Inorganic materials 0.000 claims description 3
- FZLIPJUXYLNCLC-UHFFFAOYSA-N lanthanum atom Chemical compound [La] FZLIPJUXYLNCLC-UHFFFAOYSA-N 0.000 claims description 3
- 229910052749 magnesium Inorganic materials 0.000 claims description 3
- 239000011777 magnesium Substances 0.000 claims description 3
- QEFYFXOXNSNQGX-UHFFFAOYSA-N neodymium atom Chemical compound [Nd] QEFYFXOXNSNQGX-UHFFFAOYSA-N 0.000 claims description 3
- PUDIUYLPXJFUGB-UHFFFAOYSA-N praseodymium atom Chemical compound [Pr] PUDIUYLPXJFUGB-UHFFFAOYSA-N 0.000 claims description 3
- 229910052727 yttrium Inorganic materials 0.000 claims description 3
- VWQVUPCCIRVNHF-UHFFFAOYSA-N yttrium atom Chemical compound [Y] VWQVUPCCIRVNHF-UHFFFAOYSA-N 0.000 claims description 3
- 229910052726 zirconium Inorganic materials 0.000 claims description 3
- 238000000151 deposition Methods 0.000 claims 2
- 230000008021 deposition Effects 0.000 claims 2
- 239000000463 material Substances 0.000 abstract description 16
- 239000004065 semiconductor Substances 0.000 abstract description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 11
- 239000000126 substance Substances 0.000 description 7
- XLOMVQKBTHCTTD-UHFFFAOYSA-N Zinc monoxide Chemical compound [Zn]=O XLOMVQKBTHCTTD-UHFFFAOYSA-N 0.000 description 6
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 6
- 239000000377 silicon dioxide Substances 0.000 description 6
- 239000011521 glass Substances 0.000 description 5
- 239000002210 silicon-based material Substances 0.000 description 5
- VEXZGXHMUGYJMC-UHFFFAOYSA-N Hydrochloric acid Chemical compound Cl VEXZGXHMUGYJMC-UHFFFAOYSA-N 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 4
- RHZWSUVWRRXEJF-UHFFFAOYSA-N indium tin Chemical compound [In].[Sn] RHZWSUVWRRXEJF-UHFFFAOYSA-N 0.000 description 4
- 238000001459 lithography Methods 0.000 description 4
- 229910007541 Zn O Inorganic materials 0.000 description 3
- ZOIORXHNWRGPMV-UHFFFAOYSA-N acetic acid;zinc Chemical compound [Zn].CC(O)=O.CC(O)=O ZOIORXHNWRGPMV-UHFFFAOYSA-N 0.000 description 3
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 3
- 229910044991 metal oxide Inorganic materials 0.000 description 3
- 239000001301 oxygen Substances 0.000 description 3
- 229910052760 oxygen Inorganic materials 0.000 description 3
- 229910052725 zinc Inorganic materials 0.000 description 3
- 239000011787 zinc oxide Substances 0.000 description 3
- CSCPPACGZOOCGX-UHFFFAOYSA-N Acetone Chemical compound CC(C)=O CSCPPACGZOOCGX-UHFFFAOYSA-N 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- GWEVSGVZZGPLCZ-UHFFFAOYSA-N Titan oxide Chemical compound O=[Ti]=O GWEVSGVZZGPLCZ-UHFFFAOYSA-N 0.000 description 2
- 239000002253 acid Substances 0.000 description 2
- 230000004888 barrier function Effects 0.000 description 2
- 229910052791 calcium Inorganic materials 0.000 description 2
- 239000011575 calcium Substances 0.000 description 2
- 229910052681 coesite Inorganic materials 0.000 description 2
- 230000000052 comparative effect Effects 0.000 description 2
- 229910052906 cristobalite Inorganic materials 0.000 description 2
- 239000003989 dielectric material Substances 0.000 description 2
- 239000008236 heating water Substances 0.000 description 2
- 230000006872 improvement Effects 0.000 description 2
- 229910052738 indium Inorganic materials 0.000 description 2
- 239000007791 liquid phase Substances 0.000 description 2
- 238000001259 photo etching Methods 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 229910052682 stishovite Inorganic materials 0.000 description 2
- 238000002207 thermal evaporation Methods 0.000 description 2
- XOLBLPGZBRYERU-UHFFFAOYSA-N tin dioxide Chemical compound O=[Sn]=O XOLBLPGZBRYERU-UHFFFAOYSA-N 0.000 description 2
- 229910001887 tin oxide Inorganic materials 0.000 description 2
- 238000002834 transmittance Methods 0.000 description 2
- 229910052905 tridymite Inorganic materials 0.000 description 2
- OYPRJOBELJOOCE-UHFFFAOYSA-N Calcium Chemical compound [Ca] OYPRJOBELJOOCE-UHFFFAOYSA-N 0.000 description 1
- UXVMQQNJUSDDNG-UHFFFAOYSA-L Calcium chloride Chemical compound [Cl-].[Cl-].[Ca+2] UXVMQQNJUSDDNG-UHFFFAOYSA-L 0.000 description 1
- 235000007926 Craterellus fallax Nutrition 0.000 description 1
- 240000007175 Datura inoxia Species 0.000 description 1
- LFQSCWFLJHTTHZ-UHFFFAOYSA-N Ethanol Chemical compound CCO LFQSCWFLJHTTHZ-UHFFFAOYSA-N 0.000 description 1
- 240000007594 Oryza sativa Species 0.000 description 1
- 235000007164 Oryza sativa Nutrition 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- HCHKCACWOHOZIP-UHFFFAOYSA-N Zinc Chemical compound [Zn] HCHKCACWOHOZIP-UHFFFAOYSA-N 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
- 238000005269 aluminizing Methods 0.000 description 1
- WDIHJSXYQDMJHN-UHFFFAOYSA-L barium chloride Chemical compound [Cl-].[Cl-].[Ba+2] WDIHJSXYQDMJHN-UHFFFAOYSA-L 0.000 description 1
- 229910001626 barium chloride Inorganic materials 0.000 description 1
- QVQLCTNNEUAWMS-UHFFFAOYSA-N barium oxide Inorganic materials [Ba]=O QVQLCTNNEUAWMS-UHFFFAOYSA-N 0.000 description 1
- CSSYLTMKCUORDA-UHFFFAOYSA-N barium(2+);oxygen(2-) Chemical compound [O-2].[Ba+2] CSSYLTMKCUORDA-UHFFFAOYSA-N 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 239000001110 calcium chloride Substances 0.000 description 1
- 229910001628 calcium chloride Inorganic materials 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 229910052804 chromium Inorganic materials 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 239000002131 composite material Substances 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 238000009833 condensation Methods 0.000 description 1
- 230000005494 condensation Effects 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 229910052593 corundum Inorganic materials 0.000 description 1
- 229910021419 crystalline silicon Inorganic materials 0.000 description 1
- JAONJTDQXUSBGG-UHFFFAOYSA-N dialuminum;dizinc;oxygen(2-) Chemical compound [O-2].[O-2].[O-2].[O-2].[O-2].[Al+3].[Al+3].[Zn+2].[Zn+2] JAONJTDQXUSBGG-UHFFFAOYSA-N 0.000 description 1
- AJNVQOSZGJRYEI-UHFFFAOYSA-N digallium;oxygen(2-) Chemical compound [O-2].[O-2].[O-2].[Ga+3].[Ga+3] AJNVQOSZGJRYEI-UHFFFAOYSA-N 0.000 description 1
- 238000001035 drying Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 229910052733 gallium Inorganic materials 0.000 description 1
- 229910001195 gallium oxide Inorganic materials 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- CJNBYAVZURUTKZ-UHFFFAOYSA-N hafnium(IV) oxide Inorganic materials O=[Hf]=O CJNBYAVZURUTKZ-UHFFFAOYSA-N 0.000 description 1
- 230000007062 hydrolysis Effects 0.000 description 1
- 238000006460 hydrolysis reaction Methods 0.000 description 1
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 1
- 229910003437 indium oxide Inorganic materials 0.000 description 1
- PJXISJQVUVHSOJ-UHFFFAOYSA-N indium(iii) oxide Chemical compound [O-2].[O-2].[O-2].[In+3].[In+3] PJXISJQVUVHSOJ-UHFFFAOYSA-N 0.000 description 1
- MRNHPUHPBOKKQT-UHFFFAOYSA-N indium;tin;hydrate Chemical compound O.[In].[Sn] MRNHPUHPBOKKQT-UHFFFAOYSA-N 0.000 description 1
- 230000005764 inhibitory process Effects 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 229910052750 molybdenum Inorganic materials 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 150000002927 oxygen compounds Chemical class 0.000 description 1
- 239000004033 plastic Substances 0.000 description 1
- 229920003023 plastic Polymers 0.000 description 1
- 229910052697 platinum Inorganic materials 0.000 description 1
- 231100000614 poison Toxicity 0.000 description 1
- 230000007096 poisonous effect Effects 0.000 description 1
- 229920000642 polymer Polymers 0.000 description 1
- 239000002994 raw material Substances 0.000 description 1
- 235000009566 rice Nutrition 0.000 description 1
- 150000003839 salts Chemical class 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 229910052715 tantalum Inorganic materials 0.000 description 1
- PBCFLUZVCVVTBY-UHFFFAOYSA-N tantalum pentoxide Inorganic materials O=[Ta](=O)O[Ta](=O)=O PBCFLUZVCVVTBY-UHFFFAOYSA-N 0.000 description 1
- 239000004408 titanium dioxide Substances 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 229910001845 yogo sapphire Inorganic materials 0.000 description 1
- YVTHLONGBIQYBO-UHFFFAOYSA-N zinc indium(3+) oxygen(2-) Chemical compound [O--].[Zn++].[In+3] YVTHLONGBIQYBO-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1025—Channel region of field-effect devices
- H01L29/1029—Channel region of field-effect devices of field-effect transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/24—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only semiconductor materials not provided for in groups H01L29/16, H01L29/18, H01L29/20, H01L29/22
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66969—Multistep manufacturing processes of devices having semiconductor bodies not comprising group 14 or group 13/15 materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
- H01L29/78693—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate the semiconducting oxide being amorphous
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Thin Film Transistor (AREA)
Abstract
The invention belongs to field of semiconductor devices, a kind of sull is provided, it is Ba-Zn-Sn-O sull, and in oxide, the mol ratio of each element is Ba:Zn:Sn=0.4～0.6:1.8～2.2:2. The present invention also provides transistor containing described sull and preparation method thereof. Adopt the sull channel layer based on Ba-Zn-Sn-O, can strengthen the control ability that sull channel layer forms for carrier, improve on-off ratio, significantly increase mobility, optimize sub-threshold slope, ensureing, in the reliability and electrology characteristic basis of thin film transistor (TFT), to make the sull channel layer of thin film transistor (TFT) have material range of choice widely.
Description
Technical field
The invention belongs to field of semiconductor devices, be specifically related to a kind of sull of includingSemiconductor devices and preparation method thereof.
Background technology
In image display technology field, conventionally can adopt in a large number thin film transistor (TFT) built-up circuitDrive display unit. And in the past in long time, thin film transistor (TFT) generally adopt andCMOS(ComplementaryMetalOxideSemiconductor, CMOSSemiconductor) the silicon based material of process compatible prepares.
But the light transmission of silicon based material is poor. And in the time of these silicon based materials of preparation, withPolysilicon is compared the film forming of the non-crystalline silicon that can prepare at low temperatures, also need approximately 200 DEG C aboveHigh temperature. Can not prepare as base material with possessing cheapness, light weight, flexual polymer filmSilicon based material. Therefore, prepare thin film transistor (TFT) with silicon based material, exist heating cost high,Preparation time length waits more significant shortcoming.
In view of silica-based TFT(ThinFilmTransistor, TFT,Thin film transistor (TFT)) there is above-mentioned shortcoming, in recent ten years scientists in device and preparation methodFinding always and developing the semi-conducting material that can replace silicon based material. Transparent oxide is partly ledBody material, owing to can realizing film formation at low temp, and has the excellent spies such as higher mobilityProperty, have been a great concern. Wherein, as document K.Nomuraetal. "Room-temperaturefabricationoftransparentflexiblethin-filmtransistorsusingamorphousoxidesemiconductors”,Nature,432,p488-492(2004)Described in, the In-Ga-Zn-O film forming with In, Ga, Zn element, because it is compared and passesThe ZnO semiconductor that system uses, has less cut-off current, larger switch current ratio and moreHigh mobility, becomes the focus of research gradually.
But, due in In-Ga-Zn-O membrane structure, Ga element is with the associativity of O elementProblem, in the channel layer that makes to form, oxygen room is more, the inhibition ability forming for carrier, to thin film transistor (TFT) threshold voltage, leakage current IoffAnd on-off ratio has larger impact.And the content of In element in the earth's crust is 1 × 10-5%, and be poisonous. And Sn element is on groundContent in shell is 4 × 10-3%, compares more horn of plenty, meanwhile, and similar due to atomic structureProperty, Sn can play the effect of carrier mobility in the raising material identical with In.
For pure ZTO(Zn-Sn-O) film, the control ability that channel layer forms carrier, the leakage current while simultaneously shutoff is larger. Suitably doping can significantly improve the performance of ZTO;The control ability forming for carrier with the channel layer that overcomes existing ZTO thin film transistor (TFT)A little less than, turn-off the problem that leakage current is large simultaneously.
Therefore,, if can develop brand-new sull, overcome lacking of existing sullPoint, certainly will have very large application prospect and economic worth.
Summary of the invention
For the weak point of this area, first object of the present invention is to propose a kind of oxideFilm.
Second object of the present invention is to propose a kind of transistor that contains sull.
The 3rd object of the present invention is to propose the described transistorized method of preparation.
The technical scheme that realizes above-mentioned purpose of the present invention is:
A kind of sull, it is Ba-Zn-Sn-O sull, each unit in oxideThe mol ratio of element is Ba:Zn:Sn=0.4～0.6:1.8～2.2:2, and the ratio in oxide is correspondingRatio in barium monoxide, zinc oxide, tin oxide, for example Ba0.5mol, Zn2mol, SnIn the Ba-Zn-Sn-O sull of 2mol, the molal quantity of oxygen is 4.5mol.
Further, in described sull also doped with metallic element titanium, aluminium, magnesium, zirconium,At least one in hafnium, praseodymium, cerium, yttrium, lanthanum or neodymium, and the rubbing of the metallic element adulteratingYour content is 10～99% of Ba molar content.
The transistor that contains sull of the present invention.
Preferably, described transistor is bottom gate alternating expression thin film transistor (TFT); Described bottom gate alternating expressionThin film transistor (TFT) comprises: sull channel layer, substrate, gate electrode, gate insulator,Source area and drain region;
Described sull channel layer, gate electrode, gate insulator, source area and drain regionAll be arranged on substrate, described sull channel layer and gate electrode pass through gate insulatorSeparate; Described source area and drain region are divided and are located at sull channel layer both sides, and not mutualContact.
Described transistorized structure can be: from described substrate upwards, set gradually gate electrode,Gate insulator, sull channel layer; And gate insulator cover described gate electrode, withDescribed substrate contact; Described source area and drain region are divided and are located at sull channel layer both sides,And do not contact with each other.
Or described transistorized structure can be: from described substrate upwards, set gradually oxidationThing film channel layer, gate insulator, gate electrode; Described source area and drain region are divided and are located at oxygenCompound film channel layer both sides, and with described substrate contact.
Or described transistorized structure can be: from described substrate upwards, set gradually oxidationThing film channel layer, gate insulator, gate electrode; Described source area and drain region are divided and are located at oxygenThe both sides of compound film channel layer top, and with described substrate contact.
Prepare transistorized method of the present invention, comprise step: with metal or conductive oxidePrepare conductive film, adopt sol-gal process to prepare described sull channel layer, use gas phaseDeposition or magnetron sputtering or Atomic layer deposition method are prepared gate insulator, make by etchingDescribed conductive film part forms gate electrode, part forms source area and drain region.
Described substrate can adopt silicon, glass or plastics. Described gate electrode, source area and described inDrain region can adopt metal (as Ti, Pt, Ru, Cu, Au, Ag, Mo, Cr, Al,Ta, W or its alloy) or conductive oxide (as tin oxide, zinc oxide, indium oxide, oxygenChange the one in indium tin, indium zinc oxide, gallium oxide zinc or aluminum zinc oxide).
Described gate insulator can be such as SiO2、Si3N4、SiON、HfO2、Al2O3、Y2O3Or Ta2O5And so on dielectric material, high-k dielectric material or their mixture.
According to transistor concrete structure difference, can select the priority different order of a step. For exampleStructure " from described substrate upwards, sets gradually gate electrode, gate insulator, sullChannel layer; And gate insulator cover described gate electrode, with described substrate contact; Described source electrodeDistrict and drain region are divided and are located at sull channel layer both sides, and do not contact with each other ", preparation stepSuddenly be:
A: clean substrate;
B: forming gate electrode above described substrate: make grid by lithography above described substrateElectrode district, the ITO(IndiumTin of employing magnetron sputtering technique growth one deck 50～300 nanometer thicknessOxides, nano indium tin metal oxide) conductive film, use stripping means to form gate electrode.
C: in described gate electrode and described substrate not by part that described gate electrode coveredTop forms gate insulator: in described gate electrode and described substrate not by described gate electrode instituteThe top of the part covering, adopts PECVD(PlasmaEnhancedChemicalVaporDeposition, plasma enhanced chemical vapor deposition method) technology or magnetron sputtering technique orALD(Atomiclayerdeposition, ald) technology growth one deck 50～200 receivesThe folded gate dielectric layer of silica that rice is thick.
D: form sull channel layer above described gate insulator: at described gridThe oxide that the chemical formula of the top formation 80-150 nanometer of utmost point insulating barrier is Ba-Zn-Sn-O is thinFilm.
E: make described gate electrode exposed by etching, then at described sull channel layerThe both sides of top form respectively source area and drain region: the above-mentioned made sample of getting ready is carried outPhotoetching, is used watery hydrochloric acid to etch away a part of sull channel layer, then photoetching use hydrogenFluoric acid etches away the described gate insulator of appropriate section, exposes gate electrode; Then, employing is coveredLamina membranacea, uses the mode of thermal evaporation to draw as electrode at source-drain area formation 100nmAl, justObtain the TFT device of required preparation.
Preferably, adopt sol-gal process to prepare described sull channel layer, comprising: choosingSelect barium chloride, stannic chloride and zinc acetate compound are as presoma, in EGME liquid phaseDescribed presoma is mixed according to molar ratio, stir 15 minutes to 1 at temperature 30-60 DEG CHour, until form stable vitreosol system in solution, by this colloidal sol by spin coating sideMethod is deposited in substrate, is positioned over heat treatment 10-30min at 110-140 DEG C in air atmosphere.
Or, adopt sol-gal process to prepare described sull channel layer, comprising: select chlorineChange barium, stannic chloride, zinc acetate and metallic element titanium, aluminium, magnesium, zirconium, hafnium, praseodymium, cerium, yttrium,The soluble salt of lanthanum or neodymium, as presoma, in EGME by described presoma according toMolar ratio mixes, and stirs 15 minutes to 1 hour at temperature 30-60 DEG C, until in solutionForm stable vitreosol system, this colloidal sol is deposited in substrate to sky by spin coating methodAtmosphere is positioned over heat treatment 10-30min at 110-140 DEG C in enclosing.
Beneficial effect of the present invention is:
Adopt the sull channel layer based on Ba-Zn-Sn-O, can strengthen sullThe control ability that channel layer forms for carrier, improves on-off ratio, significantly increases mobility,Optimize sub-threshold slope, in the reliability and electrology characteristic basis of guarantee thin film transistor (TFT), makeThe sull channel layer that obtains thin film transistor (TFT) has material range of choice widely;
Head store invention also can be passed through the doping of other elements, to the oxide based on Ba-Zn-Sn-OThe characteristic of film channel layer is modulated, and further improves the reliability of thin film transistor (TFT); FavourableIn forming at low temperatures amorphous film, be conducive to the uniformity, the improvement that ensure prepared by deviceThe stability of the device of manufacturing by low temperature process; The In replacing in traditional scheme with Sn canNot reduce under the prerequisite of device performance, saving resource, reduces costs.
Brief description of the drawings
Fig. 1 is the bottom gate alternating expression thin-film transistor structure schematic diagram described in the embodiment of the present invention 1;
Fig. 2 is the preparation method of the bottom gate alternating expression thin film transistor (TFT) described in the embodiment of the present invention 1Flow chart;
Fig. 3 is the coplanar formula thin-film transistor structure of the bottom gate described in the embodiment of the present invention 2 schematic diagram;
Fig. 4 is the top grid alternating expression thin-film transistor structure schematic diagram described in the embodiment of the present invention 3;
Fig. 5 is the coplanar formula thin-film transistor structure of the top grid schematic diagram described in the embodiment of the present invention 4.
Detailed description of the invention
Below in conjunction with drawings and Examples, the specific embodiment of the present invention is done further in detailDescribe. Those skilled in the art should know, and following examples are only for the present invention is described, butBe not used for limiting the scope of the invention.
The present invention's material used is can purchase available conventional material from the market, notThe operational means of special instruction also can be considered the technological means of this area routine.
Embodiment 1
Fig. 1 is the present embodiment bottom gate alternating expression thin film transistor (TFT) (TFTwithinvertedStaggeredstructure) structural representation, as shown in Figure 1, described bottom gate alternating expression filmTransistor comprises: substrate 1(glass), gate electrode 2, gate insulator 3, sullChannel layer 4, source area 5 and drain region 6.
Gate electrode 2 is arranged on the top of substrate 1. Gate insulator 3 covers on gate electrode 2,The part that substrate 1 is not covered by gate electrode 2 contacts with gate insulator 3. SullChannel layer 4 is arranged on the top of gate insulator 3. It is thin that source area 5 is arranged on described oxideOne side of the top of film channel layer 4; Drain region 6 is arranged on described sull channel layer 4The opposite side of top. Gate electrode 2, described source area 5 and described drain region 6 are indium oxideTin material. Gate insulator 3 is SiO2Material.
The chemical formula of the sull that described sull channel layer 4 adopts isBa-Zn-Sn-O; The content mol ratio of each element is 0.5:2:2.
The preparation of this sull: selective chlorination barium, stannic chloride and the conduct of zinc acetate compoundPrecursor material is mixed these raw materials in liquid phase according to proportioning, be placed in water-bath spyAt 50 DEG C of fixed temperatures, stir 0.5 hour, by hydrolysis, condensation chemical reaction, shape in solutionBecome stable vitreosol system, then the colloidal sol in this system is deposited on by spin coating methodOn substrate, in air atmosphere, be positioned at 120 DEG C of drying bakers and place 10 minutes, finally formChemical formula is the film of Ba-Zn-Sn-O.
Transistor preparation process is as Fig. 2:
A: clean substrate: use supersonic cleaning machine to clean substrate of glass, first substrate of glass is soakedEnter in acetone heating water bath to 50 DEG C, ultrasonic 5 minutes; Again substrate of glass is immersed to anhydrous secondIn alcohol, heating water bath to 50 DEG C, ultrasonic 5 minutes.
B: forming gate electrode above described substrate: make grid by lithography above described substrateElectrode district, the ITO(IndiumTin of employing magnetron sputtering technique growth one deck 150 nanometer thicknessOxides, nano indium tin metal oxide) conductive film, use stripping means to form gate electrode.
C: in described gate electrode and described substrate not by part that described gate electrode coveredTop forms gate insulator: in described gate electrode and described substrate not by described gate electrode instituteThe top of the part covering, adopts PECVD(PlasmaEnhancedChemicalVaporDeposition, plasma enhanced chemical vapor deposition method) method growth one deck 150 nanometersThe folded gate dielectric layer of thick silica.
D: form sull channel layer above described gate insulator: at described gridIt is thin that the top of utmost point insulating barrier forms the oxide that the chemical formula of approximately 100 nanometers is Ba-Zn-Sn-OFilm.
E: make described gate electrode exposed by etching, then at described sull channel layerThe both sides of top form respectively source area and drain region: the above-mentioned made sample of getting ready is carried outPhotoetching, is used watery hydrochloric acid to etch away a part of sull channel layer, then photoetching use hydrogenFluoric acid etches away the gate insulator of appropriate section, exposes gate electrode; Then, adopt mask plateCover and do not need the place of aluminizing, use the mode of thermal evaporation to evaporate aluminium, form at source-drain areaThe Al electrode of 100nm is drawn, and has just obtained the TFT device of required preparation.
Experimental result shows, the bottom gate alternating expression thin film transistor (TFT) that the present embodiment obtains, its shutoffElectric current can be higher than 1 × 10-11A, on-off ratio is higher than 7 × 106, mobility can be higher than 5cm2/ (Vs), subthreshold value Slew Rate, lower than 1, is a kind of TFT device of better performances.
Embodiment 2
Fig. 3 is the coplanar formula thin film transistor (TFT) of the present embodiment bottom gate (TFTwithinvertedCoplanarstructure) structural representation, the coplanar formula thin film transistor (TFT) of described bottom gate comprises:Substrate 1, gate electrode 2, gate insulator 3, sull channel layer 4, source area 5 andDrain region 6.
The chemical formula of the sull that described sull channel layer 4 adopts isBa-Zn-Sn-O; The content mol ratio of each element is 0.6:2.2:2. The preparation of this sullMethod is with embodiment 1.
Described gate electrode 2 is arranged on substrate 1 (silicon base) top; Gate insulator 3 coversOn gate electrode 2, and the part not covered by gate electrode 2 with substrate 1 contacts; Source area 5A side above gate insulator 3, the opposite side of drain region 6 above gate insulator 3;Sull channel layer 4 is positioned at source area 5 and drain region 6 and gate insulator 3 tops.Gate electrode, source area and drain region adopt metal Ti material.
According to the architectural feature of the coplanar formula thin film transistor (TFT) of described bottom gate, those skilled in the art holdEasily obtain corresponding preparation method according to embodiment 1, the difference is that:
B: forming gate electrode above described substrate: make grid by lithography above described substrateElectrode district, the Ti conductive film of employing magnetron sputtering technique growth one deck 200 nanometer thickness, usesStripping means forms gate electrode.
C: in described gate electrode and described substrate not by part that described gate electrode coveredTop forms gate insulator: in described gate electrode and described substrate not by described gate electrode instituteThe top of the part covering, the titanium dioxide of employing magnetically controlled sputter method growth one deck 150 nanometer thicknessSilicon is folded gate dielectric layer.
The bottom gate alternating expression thin film transistor (TFT) that the present embodiment obtains has with embodiment 1 same goodPerformance.
Embodiment 3
Fig. 4 is the present embodiment top grid alternating expression thin film transistor (TFT) (TFTwithtopgateStaggeredstructure) structural representation, described top grid alternating expression thin film transistor (TFT) comprises:Substrate 1, gate electrode 2, gate insulator 3, sull channel layer 4, source area 5 and leakagePolar region 6.
The chemical formula of the sull that described sull channel layer 4 adopts isBa-Zn-Sn-O; The content mol ratio of each element is 0.5:2.2:2. The preparation of this sullMethod is with embodiment 1.
Structure between transistorized each parts is as follows:
Described sull channel layer 4 arranges substrate (plastic-substrates) top, source area 5With drain region 6 in sull channel layer 4 both sides and do not contact with each other; Gate insulator 3Be arranged on the top of sull channel layer 4; Gate electrode 2 is arranged on described gate insulator3 top. Gate electrode, source area and drain region adopt tin indium oxide material.
According to the architectural feature of described top grid alternating expression thin film transistor (TFT), those skilled in the art holdEasily obtain corresponding preparation method according to embodiment 1, the difference is that:
B: forming gate electrode above described substrate: make grid by lithography above described substrateElectrode district, the ITO(IndiumTin of employing magnetron sputtering technique growth one deck 100 nanometer thicknessOxides, nano indium tin metal oxide) conductive film, use stripping means to form gate electrode.
C: in described gate electrode and described substrate not by part that described gate electrode coveredTop forms gate insulator: in described gate electrode and described substrate not by described gate electrode instituteThe top of the part covering, adopts ALD(Atomiclayerdeposition, ald)The folded gate dielectric layer of silica of method growth one deck 100 nanometer thickness.
The bottom gate alternating expression thin film transistor (TFT) that the present embodiment obtains has with embodiment 1 same goodPerformance.
Embodiment 4
Fig. 5 is the coplanar formula thin film transistor (TFT) of the present embodiment top grid (TFTwithtopgateCoplanarstructure) structural representation, grid coplanar formula thin film transistor (TFT) in described top comprises:Substrate 1, gate electrode 2, gate insulator 3, sull channel layer 4, source area 5 and leakagePolar region 6.
The oxygen for calcium doping of the sull that described sull channel layer 4 adoptsCompound, the content mol ratio of Ca, Ba, Zn, the each element of Sn is 0.4:0.5:2:2. Other portionsPart material is with embodiment 1. The preparation method of sull is: selective chlorination barium, stannic chloride,Zinc acetate and calcium chloride as presoma, are pressed described presoma in liquid phase EGMEMix according to molar ratio, stir 0.5 hour at temperature 30-60 DEG C, until form in solutionStable vitreosol system, is deposited on this colloidal sol in substrate by spin coating method air atmosphereIn enclosing, be positioned over heat treatment 10-30min at 110-140 DEG C.
Bottom gate described in miscellaneous part in the coplanar formula thin film transistor (TFT) of described top grid and embodiment 1The material that in alternating expression thin film transistor (TFT), miscellaneous part adopts is identical, except described sullOutside the material of channel layer, the difference also having is that the structure between each parts is as follows:
Sull channel layer 4 is arranged on the top of described substrate 1; Source area 5 and drain electrodeDistrict 6 is arranged on the both sides, top of described sull channel layer 4; Gate insulator 43 is establishedPut at described sull channel layer 4 and do not covered by described source area 5 and described drain region 6The top of the part of lid; Gate electrode 2 is arranged on the top of gate insulator 3.
According to the architectural feature of the coplanar formula thin film transistor (TFT) of described top grid, those skilled in the art holdEasily obtain corresponding preparation method according to embodiment 1, therefore, at this to its preparation method no longerRepeat. The bottom gate alternating expression thin film transistor (TFT) that the present embodiment obtains has with embodiment 1 good equallyGood performance.
Comparative example 1
The chemical formula of sull is Ga-ZTO; The content of each element is respectively Ga:Zn:Sn=0.5:2:2. Preparation method is: sol-gal process. Identical with the preparation method of example 1
The performance of the sull obtaining: cut-off current can reach 10-10A, on-off ratio4.35*106, mobility can reach 0.98cm2/ (Vs), subthreshold value Slew Rate is 0.67
Comparative example 2
The chemical formula of existing sull is Ba-IZO; The content of each element is respectively Ba:In:Zn=0.5:2:2. Preparation method is: sputtering method.
The performance of the sull obtaining: cut-off current can reach 10-10A, on-off ratioCan reach 105, mobility can reach 1.43cm2/ (Vs), subthreshold value Slew Rate is 0.94.
Than traditional thin film transistor (TFT) based on In-Ga-Zn-O, of the present invention based onThe thin film transistor (TFT) of Ba-Zn-Sn-O has advantage: adopt the oxidation based on Ba-Zn-Sn-OThing film channel layer, can strengthen the control energy that sull channel layer forms for carrierPower, improves on-off ratio, increases mobility, optimizes sub-threshold slope; Ensureing thin film transistor (TFT)Reliability and electrology characteristic basis on, the sull channel layer of thin film transistor (TFT) is hadMaterial range of choice widely; And by the doping of other elements, can to based onThe characteristic of the sull channel layer of Ba-Zn-Sn-O is modulated, and further improves film crystalline substanceThe reliability of body pipe; Be conducive to form at low temperatures amorphous film, be conducive to ensure deviceThe stability of the uniformity of preparation, the device that improvement is manufactured by low temperature process; Utilize simultaneouslyBa-ZTO can improve the light transmittance of some visible light wave ranges, and forming composite construction with ZTO canTo realize the high light transmittance of whole visible light wave range; The In replacing in traditional scheme with Sn canNot reduce under the prerequisite of device performance, saving resource, reduces costs.
Above embodiment is only for the present invention is described, and limitation of the present invention is not relevantThe those of ordinary skill of technical field, without departing from the spirit and scope of the present invention,Can also make a variety of changes and modification, therefore all technical schemes that are equal to also belong to the present inventionCategory, scope of patent protection of the present invention should be defined by the claims.
Claims (7)
1. contain a transistor for sull, described sull is Ba-Zn-Sn-O sull, and in oxide, the mol ratio of each element is Ba:Zn:Sn=0.4 ~ 0.6:1.8 ~ 2.2:2;
Described transistor is prepared and is obtained by following steps: prepare conductive film with metal or conductive oxide, adopt sol-gal process to prepare sull channel layer, prepare gate insulator with vapour deposition or magnetron sputtering or Atomic layer deposition method, by etching make described conductive film part form gate electrode, part forms source area and drain region;
Wherein, adopt sol-gal process to prepare described sull channel layer, comprise step: selective chlorination barium, stannic chloride and zinc acetate compound are as presoma, in EGME, described presoma is mixed according to molar ratio, stir 15 minutes to 1 hour at temperature 30-60 DEG C, until form stable vitreosol system in solution, this colloidal sol is deposited in substrate by spin coating method, in air atmosphere, is positioned over heat treatment 10-30min at 110-140 DEG C.
2. transistor according to claim 1, it is characterized in that, in described sull, also doped with at least one in metallic element titanium, aluminium, magnesium, zirconium, hafnium, praseodymium, cerium, yttrium, lanthanum or neodymium, and the molar content of the metallic element adulterating is 10 ~ 99% of Ba molar content.
3. transistor according to claim 1, is characterized in that, described transistor is bottom gate alternating expression thin film transistor (TFT); Described bottom gate alternating expression thin film transistor (TFT) comprises: sull channel layer, substrate, gate electrode, gate insulator, source area and drain region; Described sull channel layer, gate electrode, gate insulator, source area and drain region are all arranged on substrate, and described sull channel layer and gate electrode are separated by gate insulator; Described source area and drain region are divided and are located at sull channel layer both sides, and do not contact with each other.
4. transistor according to claim 3, is characterized in that, from described substrate upwards, sets gradually gate electrode, gate insulator, sull channel layer; And gate insulator cover described gate electrode, with described substrate contact; Described source area and drain region are divided and are located at sull channel layer both sides, and do not contact with each other.
5. transistor according to claim 1, is characterized in that, from described substrate upwards, sets gradually sull channel layer, gate insulator, gate electrode; Described source area and drain region are divided and are located at sull channel layer both sides, and with described substrate contact.
6. transistor according to claim 1, is characterized in that, from described substrate upwards, sets gradually sull channel layer, gate insulator, gate electrode; The both sides that are located at sull channel layer top are divided in described source area and drain region, and with described substrate contact.
7. the arbitrary described transistorized method of preparation claim 1-6, comprise step: prepare conductive film with metal or conductive oxide, adopt sol-gal process to prepare described sull channel layer, prepare gate insulator with vapour deposition or magnetron sputtering or Atomic layer deposition method, by etching make described conductive film part form gate electrode, part forms source area and drain region;
Wherein, adopt sol-gal process to prepare described sull channel layer, comprise: selective chlorination barium, stannic chloride and zinc acetate compound are as presoma, in EGME, described presoma is mixed according to molar ratio, stir 15 minutes to 1 hour at temperature 30-60 DEG C, until form stable vitreosol system in solution, this colloidal sol is deposited in substrate by spin coating method, in air atmosphere, is positioned over heat treatment 10-30min at 110-140 DEG C.
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