CN102707219A - Testing device for semiconductor device test - Google Patents
Testing device for semiconductor device test Download PDFInfo
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- CN102707219A CN102707219A CN2012102065976A CN201210206597A CN102707219A CN 102707219 A CN102707219 A CN 102707219A CN 2012102065976 A CN2012102065976 A CN 2012102065976A CN 201210206597 A CN201210206597 A CN 201210206597A CN 102707219 A CN102707219 A CN 102707219A
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- tie point
- test board
- semiconductor devices
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- proving installation
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Abstract
The invention relates to a testing device for a semiconductor device test. A plurality of connecting points are arranged on the lower surface of a semiconductor device. The testing device for the semiconductor device test comprises a testing plate, a testing fixture and a conductive grid, wherein a plurality of connecting points are arranged on the upper surface of the testing plate, the testing fixture is used for clamping the semiconductor device to be tested, and the conductive grid is positioned between the semiconductor device to be tested and the testing plate and is used for connecting the connecting points of the semiconductor device to be tested with the connecting points of the testing plate. By adopting the conductive grid, the contact rate of the connecting points of the semiconductor device to be tested with the connecting points of the testing plate is increased, therefore the testing accuracy is increased.
Description
Technical field
The present invention relates to technical field of semiconductors, particularly a kind of proving installation that is used for semiconducter device testing.
Background technology
As shown in Figure 1, the existing proving installation that is used to test device under test 11 generally includes test board 12, is positioned at the tie point 121 of test board 12 upper surfaces and is positioned at the test fixture 13 on the test board 12 in tie point 121 outsides.Said test fixture 13 is used for clamping device under test 11; The bottom of said test fixture 13 have a plurality of run through said test fixture and with the cylindrical conductor (pogo) 131 of the tie point 121 corresponding connections of test board 12 upper surfaces, the tie point 121 of the xsect of said cylindrical conductor (pogo) 131 and said test board 12 upper surfaces is suitable.
When test; Said device under test 11 is placed in the said test fixture 13; The tie point 111 of said device under test 11 lower surfaces links to each other with the cylindrical conductor 131 of said test fixture 13, needs to guarantee that the tie point 111 on the device under test 11 could satisfy test request with cylindrical conductor 131 corresponding the contacting of test fixture 13.Yet; Along with the chip integration of semicon industry is increasingly high, the tie point on the device under test is more and more intensive, and the tie point on the test board is more and more littler; The diameter of the tie point 121 on the test board 12 is generally at several millimeters; Cause cylindrical conductor 131 loose contacts of the tie point and the test fixture 13 of device under test easily, and then cause testing efficiency low, it is unreliable to test.
Therefore, how to improve the tie point of device under test and the contact rate between the tie point on the test board, become one of technical matters that those skilled in the art need to be resolved hurrily.
Summary of the invention
The purpose of this invention is to provide a kind of proving installation that is used for semiconducter device testing, can increase the contact rate of the tie point of tie point and test board upper surface on the semiconductor devices to be measured, to improve testing efficiency.
Technical solution of the present invention is a kind of proving installation that is used for semiconducter device testing, is used for the test of semiconductor devices to be measured, and the lower surface of said semiconductor devices is provided with a plurality of tie points, and the said proving installation that is used for semiconducter device testing comprises:
One test board is positioned at said semiconductor devices to be measured below, and said test board upper surface is provided with a plurality of tie points;
One is used for the test fixture of the said semiconductor devices to be measured of clamping, is positioned on the test board and is positioned at the tie point outside of said test board;
The said proving installation that is used for semiconducter device testing also comprises: conductive grid between said semiconductor devices to be measured and said test board, and connects the tie point of said semiconductor devices to be measured and the tie point of said test board.
As preferably: said conductive grid is made up of the conductive filament of space parallel arrangement and the insulating material that is encapsulated between the adjacent conductive silk.
As preferably: the cross-sectional area of the insulating material between said conductive filament and the conductive filament is all less than the cross-sectional area of the tie point of the tie point of said semiconductor devices to be measured and said test board.
As preferably: said conductive filament is a right cylinder, and the tie point of said semiconductor devices to be measured and the tie point of said test board are spheroid, hemisphere or right cylinder.
As preferably: the diameter of said conductive filament is much smaller than the diameter of the tie point of the tie point of said semiconductor devices to be measured and said test board, and the spacing between the adjacent conductive silk is much smaller than the diameter of the tie point of the tie point of said semiconductor devices to be measured and said test board.
As preferably: the diameter of said conductive filament is less than 0.1mm.
As preferably: the spacing of said conductive filament is less than 0.01mm.
Compared with prior art; The proving installation that is used for semiconducter device testing of the present invention comprises that one connects the conductive grid of tie point of tie point and the test board upper surface of semiconductor devices lower surface to be measured; Increase the contact rate of tie point of tie point and the test board upper surface of semiconductor devices lower surface to be measured through said conductive grid, thereby improved test accuracy; Further; Conductive grid is made up of the conductive filament of the very thin of space parallel arrangement and the insulating material that is encapsulated in the very thin between the adjacent conductive silk; Make tie point and the tie point of test board upper surface on the said device under test link to each other, increase contact rate through many conductive filaments.
Description of drawings
Fig. 1 is the structural representation that prior art is used for the proving installation of semiconducter device testing;
Fig. 2 is the structural representation of the proving installation that is used for semiconducter device testing of the specific embodiment of the invention;
Fig. 3 is the vertical view of the proving installation conductive grid that is used for semiconducter device testing of the specific embodiment of the invention.
Embodiment
The present invention below will combine accompanying drawing to do further to detail:
A lot of details have been set forth in the following description so that make much of the present invention.But the present invention can implement much to be different from alternate manner described here, and those skilled in the art can do similar popularization under the situation of intension of the present invention, so the present invention does not receive the restriction of following disclosed practical implementation.
Secondly, the present invention utilizes synoptic diagram to be described in detail, when the embodiment of the invention is detailed; For ease of explanation; The sectional view of expression device architecture can be disobeyed general ratio and done local the amplification, and said synoptic diagram is instance, and it should not limit the scope of the present invention's protection at this.The three dimensions size that in actual fabrication, should comprise in addition, length, width and the degree of depth.
Fig. 2 shows the structural representation that the present invention is used for the proving installation of semiconducter device testing.
See also shown in Figure 2; The present invention provides a kind of proving installation that is used for semiconducter device testing; Be used for the test 21 of semiconductor devices to be measured, the lower surface of said semiconductor devices is provided with a plurality of tie points 211, and the said proving installation that is used for semiconducter device testing comprises:
One test board 22 is positioned at said semiconductor devices to be measured 21 belows, and said test board 22 upper surfaces are provided with a plurality of tie points 221;
One is used for the test fixture 23 of the said semiconductor devices to be measured of clamping, is positioned on the test board 22 and is positioned at tie point 221 outsides of said test board 22;
The said proving installation that is used for semiconducter device testing also comprises: conductive grid 24 between said semiconductor devices 21 to be measured and said test board 22, and connects the tie point 211 of said semiconductor devices to be measured 21 and the tie point 221 of said test board 22.
Said conductive grid 24 is made up of the conductive filament 241 of space parallel arrangement and the insulating material 242 that is encapsulated between the adjacent conductive silk 241.The cross-sectional area of the insulating material 242 between said conductive filament 241 and the conductive filament 241 is all less than the cross-sectional area of the tie point 221 of tie point of said semiconductor devices 21 to be measured 211 and said test board 22.
Said conductive filament 241 is a right cylinder, and the tie point 211 of said semiconductor devices 21 to be measured is spheroid, hemisphere or right cylinder with the tie point 221 of said test board 22.The diameter of said conductive filament is much smaller than the diameter of the tie point of the tie point of said semiconductor devices to be measured and said test board, and the spacing between the adjacent conductive silk is much smaller than the diameter of the tie point of the tie point of said semiconductor devices to be measured and said test board.
The diameter of said conductive filament 241 is less than 0.1mm.
The spacing of said conductive filament 241 is less than 0.01mm.
Said insulating material 242 is selected the material of good insulating for use, like organosilicon, condensate or plastics etc.
Because the diameter of the tie point on the test board is generally at several millimeters; And the diameter of said conductive filament is less than 0.1mm; Spacing between the conductive filament is less than 0.01mm; Make the tie point on the test board have many conductive filaments to link to each other, increased its contact rate, guaranteed the reliability of test with tie point on the device under test.
Compared with prior art; The proving installation that is used for semiconducter device testing of the present invention comprises that one connects the conductive grid of tie point of tie point and the test board upper surface of semiconductor devices lower surface to be measured; Increase the contact rate of tie point of tie point and the test board upper surface of semiconductor devices lower surface to be measured through said conductive grid, thereby improved test accuracy; Further; Conductive grid is made up of the conductive filament of the very thin of space parallel arrangement and the insulating material that is encapsulated in the very thin between the adjacent conductive silk; Make tie point and the tie point of test board upper surface on the said device under test link to each other, increase contact rate through many conductive filaments.
The above is merely preferred embodiment of the present invention, and all equalizations of being done according to claim scope of the present invention change and modify, and all should belong to the covering scope of claim of the present invention.
Claims (7)
1. proving installation that is used for semiconducter device testing, the lower surface of said semiconductor devices is provided with a plurality of tie points, and the said proving installation that is used for semiconducter device testing comprises:
One test board is positioned at said semiconductor devices to be measured below, and said test board upper surface is provided with a plurality of tie points;
One is used for the test fixture of the said semiconductor devices to be measured of clamping, is positioned on the test board and is positioned at the tie point outside of said test board;
It is characterized in that: the said proving installation that is used for semiconducter device testing also comprises: conductive grid between said semiconductor devices to be measured and said test board, and connects the tie point of said semiconductor devices to be measured and the tie point of said test board.
2. the proving installation that is used for semiconducter device testing according to claim 1 is characterized in that: said conductive grid is made up of the conductive filament of space parallel arrangement and the insulating material that is encapsulated between the adjacent conductive silk.
3. the proving installation that is used for semiconducter device testing according to claim 2 is characterized in that: the cross-sectional area of the insulating material between said conductive filament and the conductive filament is all less than the cross-sectional area of the tie point of the tie point of said semiconductor devices to be measured and said test board.
4. the proving installation that is used for semiconducter device testing according to claim 3 is characterized in that: said conductive filament is a right cylinder, and the tie point of said semiconductor devices to be measured and the tie point of said test board are spheroid, hemisphere or right cylinder.
5. the proving installation that is used for semiconducter device testing according to claim 4; It is characterized in that: the diameter of said conductive filament is much smaller than the diameter of the tie point of the tie point of said semiconductor devices to be measured and said test board, and the spacing between the adjacent conductive silk is much smaller than the diameter of the tie point of the tie point of said semiconductor devices to be measured and said test board.
6. the proving installation that is used for semiconducter device testing according to claim 5 is characterized in that: the diameter of said conductive filament is less than 0.1mm.
7. the proving installation that is used for semiconducter device testing according to claim 5 is characterized in that: the spacing of said conductive filament is less than 0.01mm.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2012102065976A CN102707219A (en) | 2012-06-21 | 2012-06-21 | Testing device for semiconductor device test |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2012102065976A CN102707219A (en) | 2012-06-21 | 2012-06-21 | Testing device for semiconductor device test |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN102707219A true CN102707219A (en) | 2012-10-03 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2012102065976A Pending CN102707219A (en) | 2012-06-21 | 2012-06-21 | Testing device for semiconductor device test |
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| Country | Link |
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| CN (1) | CN102707219A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104297571A (en) * | 2014-09-28 | 2015-01-21 | 周峰 | Wafer bearing table and Kelvin four-wire test conducting method thereof |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH11204173A (en) * | 1997-12-19 | 1999-07-30 | Molex Inc | Connector for bga |
| CN1257209A (en) * | 1998-11-17 | 2000-06-21 | 埃皮技术公司 | Small interval contactor |
| US6320398B1 (en) * | 1996-08-09 | 2001-11-20 | Advantest Corporation | Semiconductor device testing apparatus |
| CN1265505C (en) * | 2001-02-19 | 2006-07-19 | 株式会社鼎新 | Contact structure with silicone grease contact point and general laminated structure using same |
| CN102081111A (en) * | 2010-12-06 | 2011-06-01 | 上海华岭集成电路技术股份有限公司 | Probe card |
-
2012
- 2012-06-21 CN CN2012102065976A patent/CN102707219A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6320398B1 (en) * | 1996-08-09 | 2001-11-20 | Advantest Corporation | Semiconductor device testing apparatus |
| JPH11204173A (en) * | 1997-12-19 | 1999-07-30 | Molex Inc | Connector for bga |
| CN1257209A (en) * | 1998-11-17 | 2000-06-21 | 埃皮技术公司 | Small interval contactor |
| CN1265505C (en) * | 2001-02-19 | 2006-07-19 | 株式会社鼎新 | Contact structure with silicone grease contact point and general laminated structure using same |
| CN102081111A (en) * | 2010-12-06 | 2011-06-01 | 上海华岭集成电路技术股份有限公司 | Probe card |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104297571A (en) * | 2014-09-28 | 2015-01-21 | 周峰 | Wafer bearing table and Kelvin four-wire test conducting method thereof |
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Application publication date: 20121003 |