CN103426866A - Fence-interval design rule test circuit - Google Patents
Fence-interval design rule test circuit Download PDFInfo
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- CN103426866A CN103426866A CN2012101550118A CN201210155011A CN103426866A CN 103426866 A CN103426866 A CN 103426866A CN 2012101550118 A CN2012101550118 A CN 2012101550118A CN 201210155011 A CN201210155011 A CN 201210155011A CN 103426866 A CN103426866 A CN 103426866A
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Abstract
The invention provides a fence-interval design rule test circuit which comprises an electric conduction layer, a plurality of through holes, MOSFETs and a plurality of conductor layers. The through holes are formed in the electric conduction layer, the through holes are distributed in the electric conduction layer in a column mode, intervals between each through hole and a fence of the electric conduction layer are unequal, grid electrodes of the MOSFETs are electrically connected with the electric conduction layer, drain electrodes of the MOSFETs are electrically connected with a power source input end, source electrodes of the MOSFETs are electrically connected with a power source output end, the conductor layers are electrically connected with the through holes respectively, and the conductor layers are electrically connected with a plurality of control ends respectively. A plurality of test circuits can form a bigger test circuit by connecting the source electrodes of the MOSFETs and the drain electrodes of the MOSFETs in series. The test circuit tests the best fence interval by measuring saturation currents Idsat of the MOSFETs, and the circuit of the best fence interval can not be opened due to the position offset, caused by the error of the manufacturing process, of the conduction layer and the through holes in the actual manufacturing process. According to the fence-interval design rule test circuit, the number of welding pads is reduced, the layout space is saved, and the detection process is simplified.
Description
Technical field
The present invention relates to semiconductor fabrication, particularly the design rule test circuit at the design rule method of testing at the fence interval in a kind of layout design and fence interval.
Background technology
In domain (layout) design of semiconductor technology, a geometric figure (as contact hole contact or through hole via) external boundary is called enclosure to the length of another figure (as polysilicon layer poly or metal level metal) inner boundary, and this paper is called the fence interval.The schematic diagram that Fig. 1 is the Fence structure that forms of the first graph layer and second graph layer, wherein in the first graph layer A(as contact hole or through hole) external boundary and second graph layer B(as polysilicon layer or metal level) inner boundary between the length of horizontal line C be fence interval (enclosure).
In the design rule (Design Rule) of layout design, for contact hole (contact) external boundary to polysilicon layer (poly) inner boundary, contact hole external boundary to metal level (metal) inner boundary, through hole (via) external boundary to metal level inner boundary etc., the precision at fence interval is wherein very crucial and basic design parameter, and the size at fence interval directly has influence on the quality of the performance of made integrated circuit.
As shown in Figure 2, for existing a kind of contact hole external boundary under the 45nm process node to the test structure schematic diagram at the fence interval of polysilicon layer inner boundary.The fence interval to the difference size of polysilicon layer inner boundary for the contact hole external boundary respectively wherein, in embodiment shown in Fig. 2, 12 matrixes 1 have been designed altogether on domain 3, the internal structure of each matrix 1 is all identical, but the size at fence interval wherein is different, fence interval in each matrix 1 is respectively 0nm from left to right, 10nm, 15nm, 20nm, 25nm, 30nm, 35nm, 40nm, 45nm, 50nm, 55nm, 60nm, between each matrix 1, interval connects weld pad (pad) 2, and the outside of fence interval 0nm and the matrix 1 of fence interval 60nm also all is connected weld pad 2, like this, the two ends of each matrix 1 all are connected with weld pad 2, have like this 13 weld pads 2.The enlarged drawing that Fig. 3 is the matrix 1 of fence interval 10nm in Fig. 2, the polysilicon layer of matrix 1 (dashed region in Fig. 2, Fig. 3) 11 is connected to the matrix weld pad 2 of a side in addition, and the contact hole in each matrix unit in matrix 1 all is connected to the matrix weld pad 2 of opposite side in addition by wire 12.The internal structure enlarged drawing that Fig. 4 is a matrix unit in matrix shown in Fig. 3, wherein the fence between contact hole A1 and polysilicon layer 11 is spaced apart 10nm.Because the different meetings at the fence interval between contact hole A1 and polysilicon layer 11 cause the different of leakage current, therefore just can utilize the leakage current of weld pad 2 measure traverse lines-contact hole-polysilicon layer, by the comparison to leakage current, select best fence interval, fence as corresponding as the matrix of leakage current minimum interval.
In prior art, need to repeatedly design with explication various fences interval (as the contact hole external boundary to polysilicon layer inner boundary, contact hole external boundary to metal level inner boundary, through hole external boundary to metal level inner boundary etc.).So just, need to use a large amount of weld pads (as used 13 weld pads in Fig. 2), and these weld pads can not be reused, also need the layout design structure in similar Fig. 2 such as carrying out again the design of through hole to metal level fence interval, but but because the restriction of weld pad need to be used another BT(batch testing) weld pad.
Summary of the invention
In view of this, the invention provides the design rule test circuit at a kind of fence interval, to reduce the use of weld pad, save the domain space, and simplify testing process.
Technical scheme of the present invention is achieved in that
The design rule test circuit at a kind of fence interval comprises:
One conductive layer;
Be located at a plurality of through holes of described conductive layer, described a plurality of through holes are file and distribute on described conductive layer, and each is unequal at the fence interval of each through hole and described conductive layer;
Grid and the MOSFET that described conductive layer is electrically connected to, drain electrode is electrically connected to power input, source electrode is electrically connected to power output end;
A plurality of conductor layers that are electrically connected to described a plurality of through holes respectively, described a plurality of conductor layers are electrically connected to a plurality of control ends respectively.
Further, described conductive layer is polysilicon layer or the metal level that is applied to semiconductor device.
Further, described through hole is 12, and described conductor layer is 12.
Further, the fence interval of each through hole and described conductive layer is respectively 0nm, 10nm, 15nm, 20nm, 25nm, 30nm, 35nm, 40nm, 45nm, 50nm, 55nm, 60nm.
The design rule test circuit at a kind of fence interval comprises:
Be a plurality of conductive layers that horizontally-arranged distributes;
Be located at a plurality of through holes of described a plurality of conductive layers, described a plurality of through hole is array distribution, the all through holes that are positioned at same file in described array are located at same conductive layer, the all through holes that are positioned at same horizontally-arranged in described array are located at respectively different conductive layers, being positioned at the fence interval of each through hole of being located at same conductive layer of same file and this same conductive layer, each is unequal, and each through hole of being located at respectively different conductive layers that is positioned at same horizontally-arranged all equates with the fence interval of its residing conductive layer;
A plurality of MOSFET that equate with described a plurality of conductive layer quantity, the grid of each MOSFET is electrically connected to one to one with each conductive layer, described a plurality of MOSFET is composed in series the MOSFET series circuit by source electrode, drain electrode, the drain electrode of MOSFET in MOSFET series circuit one end is electrically connected to power input, and the source electrode of the MOSFET in the MOSFET series circuit other end is electrically connected to power output end;
A plurality of conductor layers that equate with the horizontally-arranged quantity of through hole, the all through holes that are positioned at same horizontally-arranged all are electrically connected to same conductor layer, the all through holes that are positioned at same file are electrically connected to the different conductor layer respectively, and described a plurality of conductor layer is electrically connected to a plurality of control ends respectively.
Further, described conductive layer is polysilicon layer or the metal level that is applied to semiconductor device.
Further, described conductive layer is 5 ~ 1000, and described MOSFET is 5 ~ 1000, and the file of described through hole is 5 ~ 1000 row.
Further, the horizontally-arranged of described through hole is 12 rows, and described conductor layer is 12.
Further, the fence interval of every exhausting hole and conductive layer is respectively 0nm, 10nm, 15nm, 20nm, 25nm, 30nm, 35nm, 40nm, 45nm, 50nm, 55nm, 60nm.
Further, described MOSFET is N-type MOSFET or P type MOSFET.
From such scheme, can find out, the design rule test circuit at fence of the present invention interval, using the formed Fence structure of conductive layer and through hole as the gate switch circuit of MOSFET, measure the fence interval corresponding MOSFET saturation current I of conductive layer and through hole
Dsat, and then obtain fence interval and MOSFET saturation current I
DsatCorresponding relation, according to saturation current I
DsatThe selected best fence gap size of variation as the fence spacing parameter in layout design, this best fence interval can not make due to the error of manufacturing process the skew of position in the Practical manufacturing process of conductive layer and through hole produce to open circuit, with existing measuring technology, compare, reduced the use of weld pad, save the domain space, and simplify testing process.
The accompanying drawing explanation
The schematic diagram that Fig. 1 is Fence structure;
Fig. 2 be in prior art the contact hole external boundary to the test structure schematic diagram at the fence interval of polysilicon layer inner boundary;
The enlarged drawing that Fig. 3 is the matrix of fence interval 10nm in Fig. 2;
The internal structure enlarged drawing that Fig. 4 is a matrix unit in matrix shown in Fig. 3;
The design rule test circuit schematic diagram that Fig. 5 is fence of the present invention interval;
Design rule test circuit the first embodiment schematic diagram that Fig. 6 is fence of the present invention interval;
Design rule test circuit the second embodiment schematic diagram that Fig. 7 is fence of the present invention interval.
Embodiment
For making purpose of the present invention, technical scheme and advantage clearer, referring to the accompanying drawing embodiment that develops simultaneously, the present invention is described in further detail.
In following execution mode, unified with title " through hole ", represent contact hole (contact) in art technology and through hole (via) etc., be somebody's turn to do " through hole " title not in order to the restriction to through hole (via), the contact hole (contact) of its representative and through hole (via) etc. known to those skilled in the art can promote according to this " through hole " title.
In following execution mode, title " conductive layer " can be the functional layer for conduction such as the polysilicon layer that is applied to semiconductor device, metal level.
" through hole " is for the electrical connection between the semiconductor device of designed production and each " conductive layer " of being stacked up and down of circuit (for the functional layer of conduction), for known in the field.
Thought of the present invention is:
Research is found, as shown in Figure 5, the Fence structure formed for conductive layer 4 and through hole 5, conductive layer 4 is electrically connected to the grid of a MOSFET 6, through hole 5 is electrically connected to a control end K by a conductor layer 7, the drain electrode of MOSFET 6 and source electrode be respectively with after power input F1 and power output end F2 are electrically connected to, when at the power input F1 access input utmost point (as V
Dd), at power output end F2 access output stage (as GND), and at the control end K access control utmost point (as V
Gg) after, MOSFET6 just can conducting.Saturation current I during MOSFET 6 conducting
DsatThe fence interval of the Fence structure that forms of size and conductive layer 4 and through hole 5 exist and contact: in semiconductor fabrication, due to the error that has manufacturing process, when the fence interval too hour, with regard to likely making conductive layer 4, with through hole 5, skew occurs and opens circuit in the position in the Practical manufacturing process, make and control pole tension (stream) and can't be applied to the grid of MOSFET 6 and make the transistor can't conducting, and then can't form saturation current Idsat in MOSFET 6, thereby electric current between power input F1 and power output end F2 is become very little.Based on this thought, the invention provides the design rule test circuit at a kind of fence interval.
As shown in Figure 6, be the first embodiment schematic diagram of the design rule test circuit at fence of the present invention interval.This circuit comprises: a conductive layer 4; Be located at a plurality of through holes of this conductive layer 4, the first through hole 51 as shown in Figure 6, the second through hole 52 ..., m through hole 5m(m is greater than 1 positive integer), the plurality of through hole is file and distributes on this conductive layer 4, and each is unequal at the fence interval of each through hole and conductive layer 4, in Fig. 6, the first through hole 51 is from top to bottom file to m through hole 5m and distributes on conductive layer 4, from the fence interval of the first through hole 51 to m through hole 5m and conductive layer 4, increases gradually; One MOSFET 6, the grid of MOSFET 6 is electrically connected to conductive layer 4, drain electrode is electrically connected to power input F1, source electrode is electrically connected to power output end F2; A plurality of conductor layers, with a plurality of through holes, be electrically connected to respectively, in Fig. 6, conductor layer No.1 71 is electrically connected to the first through hole 51, the second conductor layer 72 is electrically connected to the second through hole 52 ..., m conductor layer 7m is electrically connected to m through hole 5m, a plurality of conductor layers also are electrically connected to a plurality of control ends respectively, in Fig. 6, conductor layer No.1 71 is electrically connected to the first control end K1, the second conductor layer 72 is electrically connected to the second control end K2 ..., m conductor layer 7m is electrically connected to m control end Km.
The design rule test that utilizes the embodiment circuit shown in Fig. 6 to carry out the fence interval is carried out by the following method.The power input F1 access input utmost point is (as V
Dd), at power output end F2 access output stage (as GND); The first control end K1 access control utmost point corresponding with the first through hole 51 is (as V
Gg), other control ends are vacant, record the saturation current I of the MOSFET now 6 corresponding with the fence interval of the first through hole 51 and conductive layer 4
DsatThe second control end K2 access control utmost point corresponding with the second through hole 52 is (as V
Gg), other control ends are vacant, record the saturation current I of the MOSFET now 6 corresponding with the fence interval of the second through hole 52 and conductive layer 4
Dsat The m control end Km access control utmost point corresponding with m through hole 5m is (as V
Gg), other control ends are vacant, record the saturation current I of the MOSFET now 6 corresponding with the fence interval of m through hole 5m and conductive layer 4
DsatAccording to recorded all fences interval and corresponding saturation current I with it
DsatRelation, select best saturation current I
DsatCorresponding fence interval is as the fence interval of design rule.Fence interval and corresponding saturation current I with it
DsatRelation, can mean by a coordinate system sign saturation current I as upper as the transverse axis at a coordinate system (x axle)
Dsat, at the upper sign of the longitudinal axis (y axle) of this coordinate system fence interval, by recorded fence interval and the saturation current I of correspondence with it
DsatBe marked in this coordinate system, just can obtain fence interval and saturation current I
DsatCurve relation figure, and select applicable fence interval according to this graph of a relation.
Corresponding with the prior art shown in Fig. 2, in the present embodiment, m is desirable 12, shown in Fig. 6 in circuit, total: 12 through holes, be respectively the first through hole 51, the second through hole 52 ..., the 12 through hole 512; 12 conductor layers, be respectively conductor layer No.1 71, the second conductor layer 72 ..., the 12 conductor layer 712; 12 control ends, be respectively the first control end K1 electrical connection, the second control end K2 ..., the 12 control end K12; From the first through hole 51 to the 12 through holes 512, with the fence interval of conductive layer 4, be respectively 0nm, 10nm, 15nm, 20nm, 25nm, 30nm, 35nm, 40nm, 45nm, 50nm, 55nm, 60nm; MOSFET 6 can adopt N-type MOSFET, and the voltage of the input utmost point of power input F1 access is 2.5V, power output end F2 ground connection; The voltage of the control utmost point that each control end accesses respectively is 2.5V.Adopt above-mentioned parameter, but utilize test MOS FET saturation current I
DsatThe saturation current tester just can obtain the above-mentioned corresponding saturation current I in each fence interval
Dsat, and then can be according to these saturation currents I
DsatSelect best fence interval.MOSFET also can adopt P type MOSFET, adjusts the control pole tension of control end access according to the turn-on condition of P type MOSFET, makes P type MOSFET conducting, also can carry out saturation current I
DsatMeasurement.
MOSFET of middle employing embodiment illustrated in fig. 6 is measured the Fence structure of a conductive layer 4 and through hole wherein, and comprise a large amount of semiconductor device at integrated circuit, utilize the circuit of the Fence structure that only comprises a conductive layer 4 and through hole wherein shown in Fig. 6, due to the very few test that is not enough to carry out fence interval design rule of sampling, therefore need other execution modes to make saturation current I
DsatCan survey.
As shown in Figure 7, be the second embodiment schematic diagram of the design rule test circuit at fence of the present invention interval.With Fig. 6, compare, embodiment illustrated in fig. 7 is the series connection form of Fig. 6, and this circuit concrete structure is as follows.
This circuit comprises: be a plurality of conductive layers that horizontally-arranged distributes, the first conductive layer 41 as shown in Figure 7, the second conductive layer 42 ..., n conductive layer 4n, be located at a plurality of through holes of the plurality of conductive layer, in Fig. 7, a plurality of through holes are located at the first conductive layer 41 to n conductive layer 4n, a plurality of through holes are array distribution, the all through holes that are positioned at same file in this array are located at same conductive layer, the first through hole 51 as the first conductive layer 41, the second through hole 52, m through hole 5m is positioned at same file, the first through hole 51 of the second conductive layer 42, the second through hole 52, m through hole 5m is positioned at same file, the first through hole 51 of n conductive layer 4n, the second through hole 52, m through hole 5m is positioned at same file, the all through holes that are positioned at same horizontally-arranged in this array are located at respectively different conductive layers, as all the first through holes 51 in Fig. 7 are positioned at same horizontally-arranged and are arranged at respectively the first conductive layer 41 to n conductive layer 4n, all the second through holes 52 are positioned at same horizontally-arranged and are arranged at respectively the first conductive layer 41 to n conductive layer 4n, all m through hole 5m are positioned at same horizontally-arranged and are arranged at respectively the first conductive layer 41 to n conductive layer 4n, being positioned at the fence interval of each through hole of being located at same conductive layer of same file and this same conductive layer, each is unequal, in Fig. 7, being positioned at the fence interval of each through hole of the first conductive layer 41 and this first conductive layer 41, each is unequal and increase gradually from the fence interval of the first through hole 51 to m through hole 5m and the first conductive layer 41, being positioned at the fence interval of each through hole of the second conductive layer 42 and this second conductive layer 42, each is unequal and increase gradually from the fence interval of the first through hole 51 to m through hole 5m and this second conductive layer 42, being positioned at the fence interval of each through hole of n conductive layer 4n and this n conductive layer 4n, each is unequal and increase gradually from the fence interval of the first through hole 51 to m through hole 5m and this n conductive layer 4n, each through hole of being located at respectively different conductive layers that is positioned at same horizontally-arranged all equates with the fence interval of its residing conductive layer, in Fig. 7, the first through hole 51 that is positioned at same horizontally-arranged is arranged at respectively the first conductive layer 41 to n conductive layer 4n, and the first conductive layer 41 to the first through hole 51 of each conductive layer of n conductive layer 4n all equates with the fence interval of this conductive layer, the second through hole 52 that is positioned at same horizontally-arranged is arranged at respectively the first conductive layer 41 to n conductive layer 4n, and the first conductive layer 41 to the second through hole 52 of each conductive layer of n conductive layer 4n all equates with the fence interval of this conductive layer, the m through hole 5m that is positioned at same horizontally-arranged is arranged at respectively the first conductive layer 41 to n conductive layer 4n, and the first conductive layer 41 all equates with the fence interval of this conductive layer to the m through hole 5m of each conductive layer of n conductive layer 4n, a plurality of MOSFET that equate with the plurality of conductive layer quantity, the grid of each MOSFET is electrically connected to one to one with each conductive layer, as a MOSFET 61 in Fig. 7 is electrically connected to the first conductive layer 41 by grid, the 2nd MOSFET 62 is electrically connected to the second conductive layer 42 by grid, n MOSFET 6n is electrically connected to n conductive layer 4n by grid, the plurality of MOSFET passes through source electrode, drain electrode is composed in series the MOSFET series circuit, the source electrode of a MOSFET 61 is connected with the drain electrode of the 2nd MOSFET 62, the source electrode of the 2nd MOSFET 62 is not shown with the 3rd MOSFET(Fig. 7) drain electrode be connected, n-1MOSFET(Fig. 7 is not shown) source electrode with the drain electrode of n MOSFET 6n, be connected, the drain electrode of MOSFET in MOSFET series circuit one end is electrically connected to power input, the source electrode of MOSFET in the MOSFET series circuit other end is electrically connected to power output end, as the drain electrode of the MOSFET 61 in MOSFET series circuit one end in Fig. 7 is electrically connected to power input F1, the source electrode of n MOSFET 6n in the MOSFET series circuit other end is electrically connected to power output end F2, a plurality of conductor layers that equate with the horizontally-arranged quantity of through hole, each conductor layer is electrically connected to all through holes of each horizontally-arranged respectively, the all through holes that are positioned at same horizontally-arranged all are electrically connected to same conductor layer, the all through holes that are positioned at same file are electrically connected to the different conductor layer respectively, and described a plurality of conductor layer is electrically connected to a plurality of control ends respectively, as the conductor layer of m in Fig. 7, wherein conductor layer No.1 71 respectively with on same horizontally-arranged and all the first through holes 51 that are positioned at different conductive layers be electrically connected to, the second conductor layer 72 respectively with on same horizontally-arranged and all the second through holes 52 that are positioned at different conductive layers be electrically connected to, m conductor layer 7m respectively with on same horizontally-arranged and all m through hole 5m that are positioned at different conductive layers be electrically connected to, conductor layer No.1 71 is electrically connected to the first control end K1, the second conductor layer 72 is electrically connected to the second control end K2, m conductor layer 7m is electrically connected to m control end Km.
With the circuit of Fig. 6, compare, the expansion that the circuit of Fig. 7 is circuit shown in Fig. 6, it is the series connection form of circuit shown in Fig. 6, any one unit in Fig. 7 wherein, as the first through hole 51 of i MOSFET, i conductive layer and i conductive layer integer that is 1 to n to m through hole 5m(i) circuit structure unit that forms is circuit structure as shown in Fig. 6.Being shown in Fig. 7 in circuit, is at least 1 conductive layer if a plurality of conductive layer will be expressed the meaning, as a special case, if, when 1 conductive layer (being n=1) is wherein only arranged, its structure is consistent with Fig. 6.
In structure, power input F1 access is inputted to the utmost point (as V shown in Fig. 7
Dd), at power output end F2 access output stage (as GND), not shown with j through hole 5j(Fig. 7) corresponding j control end Kj(Fig. 7 is not shown) (integer that j is 1 to m) access control utmost point is (as V
Gg) time, this j control end Kj is not shown by j conductor layer 7j(Fig. 7) be electrically connected to each j through hole 5j and can make all MOSFET all conductings simultaneously, so just can measure the saturation current I of the corresponding power input F1 in fence interval of j through hole 5j that this j control end Kj connects and conductive layer to the MOSFET series circuit of power output end F2
Dsat.
With embodiment illustrated in fig. 6, compare, Fig. 7 has adopted the series system of a plurality of Fig. 6 structures, has increased the Fence structure of a plurality of conductive layers and through hole wherein, and then has increased a large amount of samplings, makes the test of fence interval design rule more accurate, for example:
While utilizing the circuit of Fig. 6 to carry out the test of fence interval design rule, due to the error of manufacturing process, just this kind of situation may appear: at j
1The j that through hole is corresponding
1After control end access control extremely, can measure the saturation current I of MOSFET 6
Dsat, and at j
1The j that through hole to the m through hole is corresponding
1All can measure the saturation current I of MOSFET 6 after the access control extremely of control end to the m control end
Dsat, and at j
1The j that-1 through hole is corresponding
1-1 control end is even than j
1-1 through hole after control end access control extremely corresponding to the through hole of corresponding less Fence structure, all can not measure the saturation current I of MOSFET 6
Dsat, can select j
1The corresponding fence gap size of through hole is as the design rule parameter at fence interval.But in circuit structure shown in Fig. 6, only by a Fence structure, carry out MOSFET 6 grids and the access of controlling the utmost point, just exist sampling very few (only by a Fence structure) to cause and test inaccurate problem.
And for circuit shown in Fig. 7, only have all MOSFET grids all with control the utmost point and connect the series circuit conducting that guarantee MOSFET forms and produce saturation current I
Dsat.Therefore, due to the error of manufacturing process, just this kind of situation may appear: at i
1J on conductive layer
1Skew occurs and opens circuit in the position of through hole in the Practical manufacturing process, makes i
1The i that conductive layer is corresponding
1MOSFET does not meet turn-on condition, but on other conductive layers j
1Through hole does not open circuit and makes other MOSFET meet turn-on condition, due to i
1MOSFET does not meet series circuit that turn-on condition makes all MOSFET form can't conducting, thereby can't detect the saturation current I of the series circuit that all MOSFET form
Dsat, this just illustrates j
1The corresponding fence gap size of through hole is not suitable as the design rule parameter at fence interval.Only appear at this j on all conductive layers
1The fence interval that through hole is corresponding guarantees under the error of manufacturing process, can make all MOSFET all can the access control utmost point and then the series circuit conducting that makes MOSFET form and produce saturation current I
Dsat, this j of guarantee
1The fence gap size that through hole is corresponding can be used as the design rule parameter at fence interval.
Therefore the embodiment of Fig. 7 and Fig. 6 compares, more accurate for the test of fence interval design rule.
For circuit shown in Fig. 7, during practical application, the quantity of n can be set to 5 ~ 1000 as required, and corresponding conductive layer quantity is 5 ~ 1000, and MOSFET is 5 ~ 1000, and the file that is the through hole of array distribution is 5 ~ 1000 row.The quantity of n is difficult for very few and affects the sampling of Fence structure.Below corresponding with the prior art shown in Fig. 2, introduce to adopt circuit shown in Fig. 7 to carry out saturation current I
DsatMeasurement and select the embodiment at best fence interval.
In the present embodiment, m desirable 12, be shown in Fig. 7 in circuit, in the array formed at through hole, the horizontally-arranged of through hole is 12 rows altogether, the first conductive layer 41 to each conductive layer in n conductive layer 4n all has 12 through holes, be respectively the first through hole 51, the second through hole 52 ..., the 12 through hole 512(Fig. 7 is not shown); Conductor layer is 12, be respectively conductor layer No.1 71, the second conductor layer 72 ..., the 12 conductor layer 712(Fig. 7 is not shown); 12 control ends, be respectively the first control end K1 electrical connection, the second control end K2 ..., the 12 control end K12(Fig. 7 is not shown); From the horizontally-arranged of horizontally-arranged to the 12 through holes 512 of the first through hole 51, the fence interval of every exhausting hole and each conductive layer is respectively 0nm, 10nm, 15nm, 20nm, 25nm, 30nm, 35nm, 40nm, 45nm, 50nm, 55nm, 60nm; N gets 500, and MOSFET is 500, and conductive layer is 500, and all MOSFET all adopt N-type MOSFET, and the voltage of the input utmost point of power input F1 access is 2.5V, power output end F2 ground connection; It is extremely vacant that the voltage of the control utmost point that each control end accesses respectively is 2.5V(other controls simultaneously).Adopt above-mentioned parameter, utilization can be tested saturation current I
DsatThe saturation current tester just can obtain the saturation current I of above-mentioned each corresponding series circuit formed by 500 MOSFET in fence interval
Dsat, and then can be according to these saturation currents I
DsatSelect best fence interval.These MOSFET also can adopt P type MOSFET, adjust the control pole tension of control end access according to the turn-on condition of P type MOSFET, make P type MOSFET conducting, also can carry out saturation current I
DsatMeasurement.
With prior art shown in Fig. 2, compare, above-mentioned test circuit of the present invention, using the formed Fence structure of conductive layer and through hole as the gate switch circuit of MOSFET, measures the fence interval corresponding MOSFET saturation current I of conductive layer and through hole
Dsat, and then obtain fence interval and MOSFET saturation current I
DsatCorresponding relation, according to saturation current I
DsatThe selected best fence gap size of variation as the fence spacing parameter in layout design, this best fence interval can not make due to the error of manufacturing process the skew of position in the Practical manufacturing process of conductive layer and through hole produce to open circuit, with existing measuring technology, compare, circuit of the present invention need to not arrange weld pad between the Fence structure different at each, thereby reduced the use of weld pad, save the domain space, and simplify testing process.
The foregoing is only preferred embodiment of the present invention, in order to limit the present invention, within the spirit and principles in the present invention not all, any modification of making, be equal to replacement, improvement etc., within all should being included in the scope of protection of the invention.
Claims (10)
1. the design rule test circuit at a fence interval, is characterized in that, comprising:
One conductive layer;
Be located at a plurality of through holes of described conductive layer, described a plurality of through holes are file and distribute on described conductive layer, and each is unequal at the fence interval of each through hole and described conductive layer;
Grid and the MOSFET that described conductive layer is electrically connected to, drain electrode is electrically connected to power input, source electrode is electrically connected to power output end;
A plurality of conductor layers that are electrically connected to described a plurality of through holes respectively, described a plurality of conductor layers are electrically connected to a plurality of control ends respectively.
2. the design rule test circuit at fence according to claim 1 interval, it is characterized in that: described conductive layer is polysilicon layer or the metal level that is applied to semiconductor device.
3. the design rule test circuit at fence according to claim 1 interval, it is characterized in that: described through hole is 12, described conductor layer is 12.
4. the design rule test circuit at fence according to claim 3 interval, it is characterized in that: the fence interval of each through hole and described conductive layer is respectively 0nm, 10nm, 15nm, 20nm, 25nm, 30nm, 35nm, 40nm, 45nm, 50nm, 55nm, 60nm.
5. the design rule test circuit at a fence interval, is characterized in that, comprising:
Be a plurality of conductive layers that horizontally-arranged distributes;
Be located at a plurality of through holes of described a plurality of conductive layers, described a plurality of through hole is array distribution, the all through holes that are positioned at same file in described array are located at same conductive layer, the all through holes that are positioned at same horizontally-arranged in described array are located at respectively different conductive layers, being positioned at the fence interval of each through hole of being located at same conductive layer of same file and this same conductive layer, each is unequal, and each through hole of being located at respectively different conductive layers that is positioned at same horizontally-arranged all equates with the fence interval of its residing conductive layer;
A plurality of MOSFET that equate with described a plurality of conductive layer quantity, the grid of each MOSFET is electrically connected to one to one with each conductive layer, described a plurality of MOSFET is composed in series the MOSFET series circuit by source electrode, drain electrode, the drain electrode of MOSFET in MOSFET series circuit one end is electrically connected to power input, and the source electrode of the MOSFET in the MOSFET series circuit other end is electrically connected to power output end;
A plurality of conductor layers that equate with the horizontally-arranged quantity of through hole, the all through holes that are positioned at same horizontally-arranged all are electrically connected to same conductor layer, the all through holes that are positioned at same file are electrically connected to the different conductor layer respectively, and described a plurality of conductor layer is electrically connected to a plurality of control ends respectively.
6. the design rule test circuit at fence according to claim 5 interval, it is characterized in that: described conductive layer is polysilicon layer or the metal level that is applied to semiconductor device.
7. the design rule test circuit at fence according to claim 5 interval, it is characterized in that: described conductive layer is 5 ~ 1000, and described MOSFET is 5 ~ 1000, and the file of described through hole is 5 ~ 1000 row.
8. the design rule test circuit at fence according to claim 5 interval, it is characterized in that: the horizontally-arranged of described through hole is 12 rows, described conductor layer is 12.
9. the design rule test circuit at fence according to claim 8 interval, it is characterized in that: the fence interval of every exhausting hole and conductive layer is respectively 0nm, 10nm, 15nm, 20nm, 25nm, 30nm, 35nm, 40nm, 45nm, 50nm, 55nm, 60nm.
10. the design rule test circuit at fence according to claim 5 interval, it is characterized in that: described MOSFET is N-type MOSFET or P type MOSFET.
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