CN102684064A - 光模块的制造方法 - Google Patents
光模块的制造方法 Download PDFInfo
- Publication number
- CN102684064A CN102684064A CN2012100700777A CN201210070077A CN102684064A CN 102684064 A CN102684064 A CN 102684064A CN 2012100700777 A CN2012100700777 A CN 2012100700777A CN 201210070077 A CN201210070077 A CN 201210070077A CN 102684064 A CN102684064 A CN 102684064A
- Authority
- CN
- China
- Prior art keywords
- mentioned
- optical element
- optical
- load
- substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 230000003287 optical effect Effects 0.000 title claims abstract description 86
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 39
- 239000000758 substrate Substances 0.000 claims abstract description 82
- 239000002184 metal Substances 0.000 claims abstract description 6
- 229910052751 metal Inorganic materials 0.000 claims abstract description 6
- 230000008878 coupling Effects 0.000 claims description 20
- 238000010168 coupling process Methods 0.000 claims description 20
- 238000005859 coupling reaction Methods 0.000 claims description 20
- 238000013459 approach Methods 0.000 claims description 15
- 230000004913 activation Effects 0.000 claims description 11
- 239000000853 adhesive Substances 0.000 claims description 9
- 230000001070 adhesive effect Effects 0.000 claims description 9
- 239000004065 semiconductor Substances 0.000 description 37
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 35
- 229910052710 silicon Inorganic materials 0.000 description 35
- 239000010703 silicon Substances 0.000 description 35
- 238000000034 method Methods 0.000 description 34
- 239000013307 optical fiber Substances 0.000 description 25
- 230000008569 process Effects 0.000 description 21
- 238000012360 testing method Methods 0.000 description 20
- 238000012546 transfer Methods 0.000 description 20
- 239000010931 gold Substances 0.000 description 18
- 238000009434 installation Methods 0.000 description 13
- 229920002120 photoresistant polymer Polymers 0.000 description 10
- 239000011347 resin Substances 0.000 description 10
- 229920005989 resin Polymers 0.000 description 10
- 230000000694 effects Effects 0.000 description 9
- 239000000463 material Substances 0.000 description 6
- 230000015572 biosynthetic process Effects 0.000 description 5
- 238000007599 discharging Methods 0.000 description 5
- 239000000203 mixture Substances 0.000 description 5
- 238000012545 processing Methods 0.000 description 5
- 229910004298 SiO 2 Inorganic materials 0.000 description 4
- 238000006243 chemical reaction Methods 0.000 description 4
- 238000001514 detection method Methods 0.000 description 4
- 238000005530 etching Methods 0.000 description 4
- 238000010438 heat treatment Methods 0.000 description 4
- 239000003550 marker Substances 0.000 description 4
- 239000010936 titanium Substances 0.000 description 4
- 230000006870 function Effects 0.000 description 3
- 229920001187 thermosetting polymer Polymers 0.000 description 3
- 238000007740 vapor deposition Methods 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 230000008859 change Effects 0.000 description 2
- GQYHUHYESMUTHG-UHFFFAOYSA-N lithium niobate Chemical compound [Li+].[O-][Nb](=O)=O GQYHUHYESMUTHG-UHFFFAOYSA-N 0.000 description 2
- 238000001039 wet etching Methods 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 240000007643 Phytolacca americana Species 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- 230000006978 adaptation Effects 0.000 description 1
- 239000012298 atmosphere Substances 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 239000007767 bonding agent Substances 0.000 description 1
- 238000001816 cooling Methods 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000002474 experimental method Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 238000011835 investigation Methods 0.000 description 1
- 210000001503 joint Anatomy 0.000 description 1
- 230000000737 periodic effect Effects 0.000 description 1
- 230000000644 propagated effect Effects 0.000 description 1
- 230000001902 propagating effect Effects 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
- H01L2224/29001—Core members of the layer connector
- H01L2224/2901—Shape
- H01L2224/29016—Shape in side view
- H01L2224/29018—Shape in side view comprising protrusions or indentations
- H01L2224/29019—Shape in side view comprising protrusions or indentations at the bonding interface of the layer connector, i.e. on the surface of the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
- H01L2224/29001—Core members of the layer connector
- H01L2224/29099—Material
- H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/29101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
- H01L2224/29111—Tin [Sn] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
- H01L2224/29001—Core members of the layer connector
- H01L2224/29099—Material
- H01L2224/2919—Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/3205—Shape
- H01L2224/32057—Shape in side view
- H01L2224/32059—Shape in side view comprising protrusions or indentations
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/32238—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the layer connector connecting to a bonding area protruding from the surface of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
- H01L2224/75—Apparatus for connecting with bump connectors or layer connectors
- H01L2224/759—Means for monitoring the connection process
- H01L2224/7592—Load or pressure adjusting means, e.g. sensors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/8119—Arrangement of the bump connectors prior to mounting
- H01L2224/81192—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/8138—Bonding interfaces outside the semiconductor or solid-state body
- H01L2224/81399—Material
- H01L2224/814—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/81438—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/81444—Gold [Au] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/818—Bonding techniques
- H01L2224/81894—Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces
- H01L2224/81895—Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces between electrically conductive surfaces, e.g. copper-copper direct bonding, surface activated bonding
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/83053—Bonding environment
- H01L2224/83095—Temperature settings
- H01L2224/83099—Ambient temperature
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8319—Arrangement of the layer connectors prior to mounting
- H01L2224/83193—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed on both the semiconductor or solid-state body and another item or body to be connected to the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/832—Applying energy for connecting
- H01L2224/83201—Compression bonding
- H01L2224/83208—Compression bonding applying unidirectional static pressure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8338—Bonding interfaces outside the semiconductor or solid-state body
- H01L2224/83385—Shape, e.g. interlocking features
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8338—Bonding interfaces outside the semiconductor or solid-state body
- H01L2224/83399—Material
- H01L2224/834—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/83438—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/83444—Gold [Au] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/838—Bonding techniques
- H01L2224/83894—Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces
- H01L2224/83895—Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces between electrically conductive surfaces, e.g. copper-copper direct bonding, surface activated bonding
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01005—Boron [B]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01006—Carbon [C]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01023—Vanadium [V]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01029—Copper [Cu]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01033—Arsenic [As]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01075—Rhenium [Re]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/0132—Binary Alloys
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/014—Solder alloys
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/12—Passive devices, e.g. 2 terminal devices
- H01L2924/1204—Optical Diode
- H01L2924/12042—LASER
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/12—Passive devices, e.g. 2 terminal devices
- H01L2924/1204—Optical Diode
- H01L2924/12043—Photo diode
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T156/00—Adhesive bonding and miscellaneous chemical manufacture
- Y10T156/10—Methods of surface bonding and/or assembly therefor
- Y10T156/1002—Methods of surface bonding and/or assembly therefor with permanent bending or reshaping or surface deformation of self sustaining lamina
- Y10T156/1039—Surface deformation only of sandwich or lamina [e.g., embossed panels]
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Optical Couplings Of Light Guides (AREA)
- Semiconductor Lasers (AREA)
- Optical Modulation, Optical Deflection, Nonlinear Optics, Optical Demodulation, Optical Logic Elements (AREA)
Abstract
本发明的目的在于提供一种不管接合用凸出的弹性恢复如何,都可以高精度地进行光学元件之间的光学定位的光模块的制造方法。光模块(1)的制造方法的特征在于具有以下步骤:在衬底(10)上形成由金属构成的接合用凸出(19);通过施加使上述接合用凸出比上述第1光学元件和上述第2光学元件最高效率地进行光耦合的位置进一步变形那样的规定量(F)的负荷后释放负荷,在上述接合用凸出上接合上述第2光学元件。
Description
技术领域
本发明涉及光模块的制造方法,特别涉及包含利用接合用凸出进行接合的多个光学元件的光模块的制造方法。
背景技术
已知有安装半导体激光元件后,用接合用凸出将光电二极管接合在铜散热器上,高精度地进行半导体激光元件和光电二极管的光学定位的方法(例如,参照专利文献1)。
在上述的方法中,当用接合用凸出接合光电二极管的情况下,事先调查施加在接合用凸出上的加压力,和依照加压力而变形的接合用凸出的高度的关系,依照上述关系选择适宜的加压力。
[专利文献1]特开平10-208269号公报(图1)
但是,通过压垮接合用凸出以亚微米级进行光学元件的高度方向的定位的方法并不存在。
进而,如果在接合用凸出上施加负荷使之变形后释放负荷,则在变形后的接合用凸出上,因接合用凸出的弹性而从变形的位置要恢复到原来位置的力发生作用。因而,在对接合用凸出给予负荷的状态下,即使进行光学元件之间的定位,其后如果释放负荷(如果去除所施加的负荷),则因为接合用凸出要恢复到变形前的状态而再次变形,所以存在光学元件间的相对位置发生变化的问题。
而且,把释放负荷后接合用凸出要恢复到变形前的状态而再次变形这一点称为“接合用凸出的弹性恢复”,把其变形量称为“弹性恢复量”。而且,“弹性恢复量”与所施加的负荷量、接合用凸出的材质、接合用凸出的形状等相应地变化。
发明内容
因而本发明的目的在于提供一种用于解决上述课题的光模块的制造方法。
另外,本发明的目的在于提供一种不管接合用凸出的弹性恢复如何,都可以高精度地进行光学元件之间的光学定位的光模块的制造方法。
本发明的光学模块的制造方法的特征在于具有如下步骤:在衬底上形成由金属构成的接合用凸出,通过施加使接合用凸出比第1光学元件和第2光学元件最高效率地进行光耦合的位置进一步变形那样的规定量的负荷后释放负荷,在上述接合用凸出上接合上述第2光学元件。
如果采用本发明,则因为考虑接合用凸出的弹性恢复量,在接合用凸出上接合第2光学元件,所以即使在释放负荷的状态下,也可以高精度地进行第1光学元件和第2光学元件的光学定位。
附图说明
图1是表示半导体激光模块1的图。
图2是用于说明半导体激光模块1的制造过程的流程图。
图3是表示半导体激光模块1的制造过程的图(1)。
图4是表示半导体激光模块1的制造过程的图(2)。
图5是表示半导体激光模块1的制造过程的图(3)。
图6是表示LD元件20和PPLN元件30的位置关系的图。
图7是表示检测器102的输出电压和用调芯安装器103施加的负荷的关系的曲线图。
图8是表示半导体激光模块1的制造过程的另一例子的图。
图9是用于说明其他的微凸出的图。
图10是用于说明另一半导体激光模块2的制造过程的图。
图11是表示另一半导体激光模块2的制造过程的图。
图12是用于说明衬底10和子衬底40的接合的图。
图13是表示PPLN元件30和光纤50的位置关系的图。
图14是表示半导体激光模块1的制造过程的图(4)。
附图标记说明
10:硅衬底;18、18′、19、19′、53:微凸出;20:LD元件;30:PPLN元件;40:子衬底;50:光纤;70:接合用树脂;100:调芯安装装置;101:控制部;102:检测部;103:调芯安装器;104:驱动部。
具体实施方式
以下参照附图说明本发明的光模块的制造方法。但是,本发明的技术范围并不限于这些实施方式,请注意权利要求范围中记载的发明和涉及其均等物这一点。
图1(a)是表示作为光模块的一例表示的半导体激光模块1的侧视图,图1(b)是半导体激光模块1的Y轴方向的侧面图。
半导体激光模块1的构成包含:硅衬底10、LD(激光二极管)元件20、对从LD元件20射出的光进行波长变换用的PPLN(Periodicaly Poled Lithium Niobate:周期性极化铌酸锂)元件30、由硅或者玻璃组成的子衬底40以及光纤50。例如,半导体激光模块1具有将从LD元件20射出的波长1064nm的单模激光近红外光在PPLN元件30中波长变换为532nm的绿色激光并射出的功能。而且,其构成是从PPLN元件30射出的光经由子衬底40在与硅衬底10接合的单模(SMF)光纤50中传播。
在半导体激光模块1中,以从LD元件20射出的光能够高效率地入射到PPLN元件中的方式进行光耦合,但为了提高光耦合效率,在两元件间始终要求高精度定位。图1(a)中的硅衬底10上的水平方向(XY平面)的位置精度在通过将校准标志等的基准标志设置在硅衬底10上进行实际安装时,用安装装置进行调整。
但是,一般,在图1(a)中的高度方向(Z方向)的精度直接以硅衬底10和LD元件20以及PPLN元件30之间的接触点决定安装高度。因而,在硅衬底10上形成作为以后说明的接合用凸出的微凸出,在微凸出上安装PPLN元件30时施加规定的负荷,使微凸出变形,由此实施确保高度方向(Z方向)的精度那样的处理。
而且,当对硅衬底10安装LD元件20以及PPLN元件30的情况下,还可以使用称为树脂、AuSn或者焊锡的接合材料。但是在这种接合材料处于液化中,可以上下移动元件进行位置的调整,但如果冷却固化,则接合材料因为不可预测地缩小、变形,所以难以进行高精度的高度方向(Z方向)的位置调整。
半导体激光模块1是表示本发明的光模块的一例,光模块并不限定于半导体激光模块1的解释。涉及本发明的光模块也非常适合于具有进行光耦合的2个以上的光学元件的其他的模块。例如,如以后说明的那样,也可以用于LD元件20和PPLN元件30之间的光耦合,或者PPLN元件30和固定在子衬底40上的光纤50之间的光耦合。而且,所谓光耦合是指以从一方的光学元件输出的光能够直接入射到另一方的光学元件中的方式,相互决定位置关系。
用图2~图5说明在作为光模块一例的半导体激光模块1的制造过程内,与LD元件20以及PPLN元件30的接合有关的部分。图2是用于说明半导体激光模块1的制造过程的流程图,图3~图5是用于更详细地说明图2所示的半导体激光模块1的制造过程的图。
最初,准备硅衬底10。图3(a)是硅衬底10的剖面图。
接着,在氧化性氛围气体中加热硅衬底10全体,在硅衬底10上形成SiO2(二氧化硅)薄膜11。另外,在SiO2薄膜11上通过蒸镀形成Ti(钛)薄膜12。进而,在Ti薄膜12上通过蒸镀形成厚度3μm的Au层13(S10)(参照图3(b))。Au层13除了蒸镀外,还可以通过溅镀或者电镀法等形成。而且,SiO2薄膜11作为绝缘硅衬底10和后面说明的微凸出18之间的绝缘层而发挥功能。另外,为了提高SiO2薄膜11和Au层13的密合性而形成Ti薄膜12。
以下,在Au层13上形成光刻胶层14,配置掩膜层15,以形成与掩膜层15对应的光刻胶14′的方式进行紫外线照射(S11)(参照图3(c))。
接着,用干蚀刻对形成有光刻胶14′的部分以外的Au层13以及Ti薄膜12进行蚀刻,形成Au层图案13′(S12)(参照图13(d))。而且,代替干蚀刻也可以用湿蚀刻形成Au层图案13′。
接着,在除去光刻胶14′后,再次形成光刻胶层15,配置掩膜层16,以下以形成与掩膜层16对应的光刻胶15′的方式进行紫外线照射(S13)(参照图4(a))。
接着,通过干蚀刻对形成有光刻胶15′的部分以外的Au层图案13′进行半蚀刻,形成微凸出18以及19(S14)(参照图4(b))。而且,代替干蚀刻也可以用湿蚀刻形成微凸出18以及19。而且,所谓半蚀刻是指:不完全除去形成有光刻胶15′的部分以外的部分,而是以一部分留下的方式进行蚀刻。在本例子中,在形成有光刻胶15′的部分以外的部分,进行蚀刻直至Au层图案13′的厚度变成1μm。
接着,除去光刻胶15′,在硅衬底上形成微凸出18以及19的步骤完成(S15)(参照图4(c))。微凸出18以及19是多个高度为2μm直径为5μm的圆柱形的突起以10~25μm间距左右均等地配置而成。而且,突起的形状、高度、宽度、间距等是一个例子,并不限于上述的情况。微凸出18以及19基于通过溅镀所形成的Au层13(S10),并且通过用半蚀刻而形成(S14),因此包含在微凸出18以及19中的全部的突起的高度都被高精度地均匀化。
以下,通过对覆盖凸出18以及19的表面的氧化膜或者污染等的惰性层进行等离子洗净处理而进行表面活性化(S16)。通过表面活性化,因为能够让表面能量高的原子之间接触,所以可以利用原子间的凝聚力在常温下牢固接合。本接合方法因为不需要特别加热,所以由热膨胀系数差的残余应力引起的各零件的位置偏差难以发生,因而能够进行高精度的定位安装。另外,还具备因热膨胀系数差的残余应力引起的零件破坏难以发生,对零件不产生疲劳而向使功能劣化少等的优点。
接着,将LD元件20安装在进行了表面活性化的微凸出18上(S17)(参照图5(a))。在LD元件20的接合面上也形成Au层,对其表面实施活性化处理。因而,只在微凸出18的上部施加规定的负荷安装LD元件20,LD元件20就在微凸出18上进行表面活性化结合而被固定。另外,LD元件20能够以经由微凸出18接收驱动电流的供给的方式而构成。此时,只要在用于形成微凸出18的Au层图案13′上实施提供驱动电流用的规定的图案形成步骤即可。
LD元件20的安装用将未图示的电子零件安装在电路衬底上的安装器进行。而且,也可以利用在以后说明的S18中使用的调芯安装器103进行LD元件20的安装。
接着,将PPLN元件30调芯安装在进行了表面活性化的微凸出19上(S18)(参照图5(b)),并结束一连串的处理。在PPLN元件30的接合面上也形成Au层,对其表面实施活性化处理。因而,只在微凸出19的上部施加规定的负荷安装PPLN元件30,PPLN元件30就在微凸出19上进行表面活性化结合而被固定。
S18中的调芯安装用调芯安装装置100进行。调芯安装装置100的构成包含:由包含CPU以及规定的存储器等的PC等组成的控制部101、检测从PPLN元件30输出的波长变换后的激光的强度,输出与强度相应的检测输出电压V(mV)的检测部102、将电子零件安装在硅衬底20上的规定的位置并且可以在安装时施加与控制量相应的负荷(N)的调芯安装器103,以及驱动LD元件20使之射出激光的驱动部104等。
控制部101控制驱动部104驱动LD元件20让激光入射到PPLN元件30,用检测部102检测从PPLN元件30射出的波长变换后的激光的强度。进而,控制部101一边监视用检测部102检测出的检测输出电压V,一边控制调芯安装器103控制施加在PPLN元件30上的负荷。
图6是表示LD元件20和PPLN元件30的位置关系的图。
从LD元件20的发光中心21射出的波长λ1的激光从PPLN元件30的入射位置31入射,从PPLN元件30的射出中心32成为波长λ2的激光射出。如图6所示那样,LD元件20以及PPLN元件30因为用调芯安装器103安装在硅衬底10上,所以LD元件20的发光中心21和PPLN元件30的入射位置31的平面上的位置关系(X-Y轴方向的位置关系)可以高精度地进行定位。但是,需要高精度地决定硅衬底10的高度方向(Z轴方向)的位置关系。而且,在图6中,箭头A表示用调芯安装器103在PPLN元件30上施加负荷的方向。
图7是表示检测器102的输出电压和用调芯安装器103施加的负荷的关系的曲线图。
在图7中,曲线B表示施加负荷的状态中的、检测器102的输出电压(mV)和用调芯安装器103施加的负荷(N)的关系。另外,曲线C表示释放负荷后的、检测器102的输出电压(mV)和用调芯安装器103施加的最终负荷(N)的关系。在图7的例子中,在施加负荷的状态下,当负荷是400(N)的情况下,检测器102的输出电压(mV)变成最大值(参照点D)。但是在释放负荷后,当最终负荷是400(N)的情况下,检测器102的输出电压(mV)未成为最大值(参照点E)。
点D例如是通过在PPLN元件30上施加负荷,让微凸出19变形,在将PPLN元件30的入射位置31设置成和LD元件20的发光中心最高效率地进行光耦合那样的位置(参照图6的位置P2)的状态,对应于释放负荷的情况。微凸出19具有如下特性:如果施加负荷则变形(压垮)收缩,而由于弹性回力的作用,如果释放负荷,则要恢复原状的力起作用,只恢复弹性恢复量。即,点E与如下情况对应:如果在点D的状态中释放负荷,则因弹性恢复的作用,PPLN元件30的入射位置31移动到其他的位置(例如,参照图6的位置P1)。
在释放负荷的状态下(实际上半导体激光模块1所利用的状态),需要将PPLN元件30的入射位置31设置成和LD元件20的发光中心21最高效率进行光耦合的位置(参照图6的P2)。因而,在S18的调芯安装中,控制部101这样控制调芯安装器103:在将PPLN元件30配置在微凸出19的规定位置上后,一边增加所施加的负荷,一边在来自检测部102的输出电压V变成最大值后,以进一步让微凸出19变形的方式施加规定的负荷量,之后释放负荷。
即,控制部101在来自检测部102的输出电压V变成最大值后(参照点D),进一步施加规定的负荷量(F:200(N)),其后释放负荷。进一步施加规定的负荷F以使PPLN元件30的入射位置31与LD元件20的发光中心21相比,变成更加下压了如图6所示的距离W1的位置(参照图6的位置P3)。其后,通过释放负荷,PPLN元件30的入射位置31因弹性恢复作用而恢复到和LD元件20的发光中心21最高效率地进行光耦合的位置(参照图6的P2)(参照图5(c))。
上述的规定的负荷量(F:200(N))因调芯安装器103、施加负荷的PPLN元件30的形状、微凸出19的材质以及形状等不同而不同,所以通过进行求图7所示的曲线B以及C的实验可以计算出。另外,在S18的调芯安装中,控制部101以在来自检测部102的输出电压V变成最大值后,施加规定的负荷的方式控制调芯安装器103。但是,用户也可以一边监视观测来自检测部102的输出电压V,一边进行调芯安装器103的控制。
图8是表示半导体激光模块1的制造过程的另一例子的图。
用图8说明另一PPLN元件30的调芯安装。在图5(b)(图2的S18)的例子中,控制部101控制调芯安装器103,使得在来自检测部102的输出电压V为最大值后,施加规定的负荷。但是,如果是在一定的基准下制造的微凸出18以及19、LD元件20,以及PPLN元件30,则并不一定需要分别让LD元件20发光,与来自检测部102的输出电压相应地进行调芯安装。
因而,在图8的例子中,预先设想来自检测部102的输出电压V变成最大值的负荷(参照图7的点D),在该负荷(例如,400(N))上进一步施加上述的规定负荷量(F:200(N))(总体例如是600(N))。由此,在PPLN元件30的入射位置31变成比LD元件20的发光中心21更加下压了如图6所示的距离W1的位置(参照图6的位置P3)后,释放负荷。于是,PPLN元件30的入射位置31因弹性恢复作用恢复到和LD元件20的发光中心21最高效率地进行光耦合的位置(参照图6的P2)。即,在图8的例子中,不使用图5(b)所示的控制部101、检测部102、驱动部104,只使用调芯安装器103设定PPLN元件30和LD元件20之间的高度方向(Z轴方向)位置关系。
在图8所示的方法中,只是在调芯安装步骤(图2的S18)中不使用控制部101、检测部102、驱动部104,只使用调芯安装器103进行的这一点和图2所示的半导体激光模块1的制造过程不同。因为其他方面特别是微凸出18以及19的制造过程、LD元件20以及PPLN元件30和微凸出18以及19的接合方法完全相同,所以省略其说明。
图9是用于说明其他的微凸出的图。
图4以及图5所示的微凸出18以及19是包含多个高度2μm并且直径5μm的圆柱形以10~25μm间距左右均匀配置的突起而成。但是,图9所示的其他的微凸出18′以及19′包含多个圆台型的突起。图9(a)是包含与图4(c)对应的微凸出18′以及19′的剖面图,图9(b)是包含在微凸出18′以及19′中的突起部分60的剖面图,图9(c)是表示包含在微凸出18′以及19′中的压垮的突起部分61的一个例子的图。
如图9(b)所示,圆台型的突起部分60是底面为直径S1(例如,2μm)的圆形,上面为直径S2(例如,1μm)的圆形,高度T1(例如,2μm)。另外,微凸出18′以及19′包含以2μm间隔在左右均匀配置的突起部分60。
图9(c)表示在调芯安装了PPLN元件30的情况下压垮的突起部分61的一个例子。圆台型突起部分61的底面为直径S1(例如,2μm)的圆形,高度为T2(例如,1μm)。因而,这种情况下,通过调芯安装,圆台型的突起部分只压垮距离W2(例如,1μm)。
与图4以及图5所示的,具有圆柱形的突起的微凸出18以及19相比,上面具有微小的圆台型的突起的微凸出18′以及19′的一方在施加了同样的负荷的情况下,容易压垮,因而,具有容易进行用于调芯的控制(因为调芯安装器103不施加高的负荷也可以)的效果。
使用图10以及图11说明在作为光模块一例的半导体激光模块1的制造过程内,涉及LD元件20以及PPLN元件30的接合的部分的其它方法。图10是用于说明半导体激光模块2的制造过程的流程图,图11是用于进一步详细说明图10所示的半导体激光模块2的制造过程的图。
半导体激光模块2和上述的半导体激光模块1的不同点在于,在半导体激光模块2中,PPLN元件30和微凸出19用热硬化性的接合用树脂固定。因而,在PPLN元件30的微凸出一侧的衬底上不形成Au层。在半导体激光模块2中,因为不需要向PPLN元件30提供电流,所以不使用成本高的Au层,用热硬化性的接合用树脂固定在微凸出19上。在半导体激光模块2中,其他方面完全和半导体激光模块1一样。因而,图10所示的半导体激光模块2的制造过程中的S20~S25以及S27因为和图2所示的半导体激光模块1的制造过程中的S10~S15以及S17完全相同,所以省略说明。
在图10所示的半导体激光模块2的制造过程中,在S26中,只对微凸出18的表面实施洗净以及/或者利用了等离子的处理,进行表面活性化。而且,对于微凸出19也进行表面活性化处理。
在S27中,和图2的S17一样在进行LD元件20的安装后,在微凸出19上涂抹接合用树脂70(参照图11(a))。作为接合用树脂70可以利用光学零件用的热硬化性树脂或者UV硬化性树脂等。
接着,在接合用树脂70上进行PPLN元件30的加热调芯安装(S29)(参照图1(b))。S29中的调芯安装的方法和图2的S18以及图5(b)所示的调芯安装完全相同。因而,控制部101预先考虑微凸出19的弹性恢复量,对PPLN元件30,在来自检测部102的输出电压V变成最大值后(参照D点),进一步施加规定的负荷量(F:200(N))。即,进一步施加规定的负荷以使PPLN元件30的入射位置31与LD元件20的发光中心21相比变成更加下压了如图11(b)所示的距离W3的位置。但是,在加热调芯安装中,进一步在施加负荷的状态下进行加热,使接合用树脂70硬化。
接着,如果释放负荷,则PPLN元件30的入射位置31因为由于弹性恢复作用恢复到和LD元件20的发光中心21最高效率地进行光耦合的位置(参照图11(c)),所以结束一连串的步骤。
如上所述,使用图10以及图11说明利用了接合用粘接材料70的PPLN元件30和硅衬底10的接合。但是,也可以使用接合用粘接材料70接合LD元件20和硅衬底10。而且,当需要通过微凸出18取得LD元件20和硅衬底10的导通的情况下,只要设置成微凸出18戳破接合用粘接材料70的构成即可。进而,当需要用粘接剂取得LD元件20和硅衬底10的导通的情况下,只要利用导电性粘接材料接合LD元件20和硅衬底10即可。
进而,即使在利用粘接材料接合LD元件20或者PPLN元件30和硅衬底10的情况下,也如用图8说明的那样,在芯调安装步骤(图2的S18)中,可以不使用控制部101、检测部102、驱动部104,只使用调芯安装器103进行。
使用图12~图14说明在作为光模块一个例子的半导体激光模块1的制造过程内的子衬底40的接合。图12是用于说明衬底10和子衬底40的接合的图,图13是表示PPLN元件30和光纤50的位置关系的图,图14是用于说明子衬底40的调芯安装的图。
如图12所示,在子衬底40上形成有凹槽51,在凹槽51中嵌入光纤50的前端部58,用粘接材料57固定。代替凹槽51也可以将V槽形成在子衬底40上,在该V槽中嵌入光纤50的前端部58并固定。在子衬底40的接合面上设置有金属膜54以及校准标志56。另外,在硅衬底10的与子衬底40对应的部分上设置光纤逃逸槽52、微凸出53,以及校准标志55。
子衬底40如以后说明的那样用调芯安装加重安装器103安装在硅衬底10上,在安装子衬底40时,用校准标志55以及56决定大致的位置,其后一边用检测器102检测来自光纤50的输出,一边以亚微米级决定X轴方向、Y轴方向以及Z轴方向的位置,接合在硅衬底10上。形成在子衬底40的接合面以及硅衬底10上的微凸出53在实施了等离子洗净处理后,通过从调芯安装加重安装器103施加的加重,进行表面活性接合。而且,用形成在硅衬底10上的金构成的微凸出53用和前面说明的微凸出18以及19同样的方法形成在硅衬底10上。
图13(a)是图1的BB′剖面图。如图13(a)所示那样,在子衬底40的凹槽51上用粘接材料57固定的光纤50通过调芯安装加重器103让子衬底40在X轴方向以及Y轴方向上移动,可以在设置于硅衬底10上的光纤逃逸槽52内移动。即,在光纤逃逸槽52的宽度W4的范围内,可以调整X轴以及Y轴方向的位置。而且,在图13(a)中,微凸出52等省略。
图13(b)是图1的CC′剖面图。如图13(b)所示,固定在子衬底40上的光纤50的前端部58和PPLN元件30的射出中32进行高精度光耦合,接收从PPLN元件30的射出中32射出的经过波长变换的532nm的绿色激光。在光纤50的前端部58上接收到的532nm的绿色激光在光纤50中传播。在图13(b)中,微凸出53等省略记载,但Z方向上的PPLN元件30的射出中32和光纤50的前端部58的定位通过微凸出53来控制。
用图14说明子衬底40的芯调安装。在图5(b)(图2的S18)的例子中,说明了PPLN元件30的调芯安装,但在图14中,用同样的方法以PPLN元件30的射出中32和光纤50的前端部58高精度地进行光耦合的方式进行子衬底40的芯调安装。在进行图14所示的调芯安装之前,设在子衬底40的接合面一侧的金属膜54以及硅衬底10的微凸出53的表面上实施等离子洗净处理。
图14中的调芯安装和图5(b)的情况一样使用调芯安装装置100进行。控制部101控制驱动部104驱动LD元件20让激光入射到PPLN元件30,从PPLN元件30射出,用检测部102检测在光纤50中传播的激光的强度。
最初,控制部101一边监视由检测部102检测出的检测输出电压V,一边控制调芯安装器103,让子衬底40在X轴方向以及Y轴方向上移动,决定输出电压V最高的位置(第1阶段)。如上所述,光纤50因为在光纤逃逸槽52的宽度W4内的范围内可以移动,所以在该范围中调芯安装器103让子衬底40在X轴以及Y轴方向上移动。
接着,控制部101控制调芯安装器103,在第1阶段输出电压V最高的位置上将子衬底40配置在微凸出53上。
接着,控制部101一边监视由检测部102检测出的检测输出电压V,一边控制调芯安装器103控制施加在子衬底40上的负荷,进行子衬底40的Z方向的定位(第2阶段)。在此,控制部101在来自检测部102的输出电压V变成最大值后,进一步施加规定的负荷量,其后释放负荷。进一步施加规定的负荷以使固定在子衬底40上的光纤50的前端部58与PPLN元件30的射出中心32相比变成更加下压了规定距离的位置。其后,通过释放负荷,固定在子衬底40上的光纤50的前端部58因弹性恢复作用而恢复到和PPLN元件30的射出中心32进行最高效率地光耦合的位置。而且,以上所述是基于和用于进行用图5~图7说明的PPLN元件30和LD元件20的光耦合的调芯安装同样的理论。这样,子衬底40在第1阶段进行X轴以及Y轴方向的定位,作为第2阶段进行Z轴方向的定位。
而且,在用图12~图14说明的子衬底40的接合方法中,如用图8说明的那样,在芯调安装步骤(图14)中,可以不使用控制部101、检测部102、驱动部104,而只使用调芯安装器103,进行预先设定的负荷的施加。另外,在用图12~图14说明的子衬底40的接合方法中,可以利用不同于图9所示的微凸出18′以及19′一样的微凸出,将子衬底40和硅衬底10接合。进而,在用图12~图14说明的子衬底40的接合方法中,如用图10以及图11说明的那样,可以利用粘接材料将子衬底40和硅衬底10接合。
在上述的例子中,作为接合用凸出的例子,说明了具有由Au形成的圆柱形的突起的微凸出18、19以及53(参照图4(c)),以及具有由Au形成的圆台形状的突起的微凸出18′以及19′(参照图9)。但是,如果是由具有高精度形成的形状的金属组成构成的接合用凸出,则也可以利用其它的接合用凸出。在接合用凸出中要求的条件是具有施加一定的负荷时的变形量、施加一定负荷后释放负荷时的弹性恢复量始终大致为一定那样的材质以及形状。
在上述的例子中,光模块1是固定了LD元件20、PPLN元件30、光纤50的子衬底40利用微凸出通过表面活性化接合与硅衬底10接合。但是,也可以是只是LD元件20以及PPLN元件30,或者只是固定有PPLN元件30以及光纤50的子衬底40以良好地进行光耦合的方式利用微凸出并通过表面活性化接合与硅衬底10接合。
Claims (8)
1.一种光模块的制造方法,上述光模块包含接合于衬底上的第1光学元件以及第2光学元件其特征在于具有以下步骤:
在上述衬底上形成由金属构成的接合用凸出,
通过施加使上述接合用凸出比上述第1光学元件和上述第2光学元件最高效率地进行光耦合的位置进一步变形那样的规定量的负荷后释放负荷,在上述接合用凸出上接合上述第2光学元件。
2.根据权利要求1所述的光模块的制造方法,其特征在于:在接合上述第2光学元件的步骤中,利用检测从上述第1光学元件经由上述第2光学元件射出的光的光检测器,一边增加施加在上述第2光学元件上的负荷,一边检测上述第1光学元件和上述第2光学元件最高效率地进行光耦合的位置。
3.根据权利要求2所述的光模块的制造方法,其特征在于:在接合上述第2光学元件的步骤中,在检测出上述第1光学元件和上述第2光学元件最高效率地进行的光耦合的位置后,经由上述第2光学元件施加使上述接合用凸出进一步变形那样的规定量的负荷。
4.根据权利要求1~3的任意一项所述的光模块的制造方法,其特征在于还包括:将上述第1光学元件接合在上述衬底上的步骤。
5.根据权利要求1~4的任意一项所述的光模块的制造方法,其特征在于:上述第2光学元件利用表面活性化结合接合在上述衬底上。
6.根据权利要求1~4的任意一项所述的光模块的制造方法,其特征在于:上述第2光学元件利用粘接材料接合在上述衬底上。
7.根据权利要求1~6的任意一项所述的光模块的制造方法,其特征在于:上述接合用凸出包含多个突起。
8.根据权利要求1~7的任意一项所述的光模块的制造方法,其特征在于:上述接合用凸出由Au构成。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2011060916A JP5636319B2 (ja) | 2011-03-18 | 2011-03-18 | 光モジュールの製造方法 |
JP2011-060916 | 2011-03-18 |
Publications (2)
Publication Number | Publication Date |
---|---|
CN102684064A true CN102684064A (zh) | 2012-09-19 |
CN102684064B CN102684064B (zh) | 2016-12-14 |
Family
ID=45936772
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201210070077.7A Expired - Fee Related CN102684064B (zh) | 2011-03-18 | 2012-03-16 | 光模块的制造方法 |
Country Status (4)
Country | Link |
---|---|
US (1) | US9214446B2 (zh) |
EP (1) | EP2500757B1 (zh) |
JP (1) | JP5636319B2 (zh) |
CN (1) | CN102684064B (zh) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN102890317A (zh) * | 2011-07-21 | 2013-01-23 | 西铁城控股株式会社 | 光模块 |
Families Citing this family (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP5230829B1 (ja) * | 2012-03-09 | 2013-07-10 | 株式会社フジクラ | 水分の除去方法、光ファイバの半田付け方法、及び、半導体レーザモジュールの製造方法 |
JP5925062B2 (ja) * | 2012-06-18 | 2016-05-25 | シチズンホールディングス株式会社 | 光モジュール及び光モジュールの製造方法 |
DE102015002176A1 (de) * | 2015-02-24 | 2016-08-25 | Jenoptik Laser Gmbh | Verfahren zum Herstellen eines Diodenlasers und Diodenlaser |
US10126504B2 (en) * | 2015-05-27 | 2018-11-13 | The United States Of America, As Represented By The Secretary Of The Navy | Antireflective surface structures for active and passive optical fiber |
CN105711224B (zh) * | 2016-03-25 | 2017-11-24 | 湖南新中合光电科技股份有限公司 | 一种光分路器晶圆贴片系统 |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5700987A (en) * | 1994-06-16 | 1997-12-23 | Lucent Technologies Inc. | Alignment and bonding techniques |
JP2001189339A (ja) * | 1999-10-20 | 2001-07-10 | Fujitsu Ltd | 半導体チップ素子、半導体チップ素子実装装置及び実装方法 |
JP2007133011A (ja) * | 2005-11-08 | 2007-05-31 | Nec Corp | 光結合構造およびその製造方法、光モジュール |
US20080245843A1 (en) * | 2004-01-22 | 2008-10-09 | Bondtech Inc. | Joining Method and Device Produced by this Method and Joining Unit |
Family Cites Families (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5393697A (en) * | 1994-05-06 | 1995-02-28 | Industrial Technology Research Institute | Composite bump structure and methods of fabrication |
JPH10208269A (ja) | 1997-01-28 | 1998-08-07 | Toshiba Corp | 光ピックアップヘッド及びその製造方法並びに製造装置 |
JP2002111113A (ja) * | 2000-09-28 | 2002-04-12 | Hitachi Ltd | 光モジュール |
JP4349475B2 (ja) * | 2009-03-19 | 2009-10-21 | 三菱電機株式会社 | 光モジュールの製造方法 |
-
2011
- 2011-03-18 JP JP2011060916A patent/JP5636319B2/ja active Active
-
2012
- 2012-03-15 EP EP12159734.8A patent/EP2500757B1/en not_active Not-in-force
- 2012-03-16 CN CN201210070077.7A patent/CN102684064B/zh not_active Expired - Fee Related
- 2012-03-16 US US13/422,656 patent/US9214446B2/en not_active Expired - Fee Related
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5700987A (en) * | 1994-06-16 | 1997-12-23 | Lucent Technologies Inc. | Alignment and bonding techniques |
JP2001189339A (ja) * | 1999-10-20 | 2001-07-10 | Fujitsu Ltd | 半導体チップ素子、半導体チップ素子実装装置及び実装方法 |
US20080245843A1 (en) * | 2004-01-22 | 2008-10-09 | Bondtech Inc. | Joining Method and Device Produced by this Method and Joining Unit |
JP2007133011A (ja) * | 2005-11-08 | 2007-05-31 | Nec Corp | 光結合構造およびその製造方法、光モジュール |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN102890317A (zh) * | 2011-07-21 | 2013-01-23 | 西铁城控股株式会社 | 光模块 |
US8920047B2 (en) | 2011-07-21 | 2014-12-30 | Citizen Holdings Co., Ltd. | Optical module |
CN102890317B (zh) * | 2011-07-21 | 2015-04-22 | 西铁城控股株式会社 | 光模块 |
Also Published As
Publication number | Publication date |
---|---|
JP5636319B2 (ja) | 2014-12-03 |
EP2500757A1 (en) | 2012-09-19 |
US20120234458A1 (en) | 2012-09-20 |
US9214446B2 (en) | 2015-12-15 |
CN102684064B (zh) | 2016-12-14 |
EP2500757B1 (en) | 2018-06-27 |
JP2012198295A (ja) | 2012-10-18 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
CN102684064A (zh) | 光模块的制造方法 | |
EP3308206B1 (en) | Self-alignment for apparatus comprising photonic device | |
CN102890317B (zh) | 光模块 | |
Szelag et al. | Hybrid III–V/silicon technology for laser integration on a 200-mm fully CMOS-compatible silicon photonics platform | |
Roelkens et al. | Micro-transfer printing for heterogeneous Si photonic integrated circuits | |
JP6731911B2 (ja) | 転送基板および対応する樹脂を使用してチップをターゲットウエハに接合するための方法 | |
US10998352B2 (en) | Integration of microdevices into system substrate | |
US20010048705A1 (en) | Wavelength-variable semiconductor laser, optical integrated device utilizing the same, and production method thereof | |
Liu et al. | III–V/silicon-on-insulator nanophotonic cavities for optical network-on-chip | |
US20230078708A1 (en) | Integration of microdevices into system substrate | |
Ye et al. | Transfer print integration of waveguide-coupled germanium photodiodes onto passive silicon photonic ICs | |
Luo et al. | Wafer-scale dies-transfer bonding technology for hybrid III/V-on-silicon photonic integrated circuit application | |
Barkai et al. | Integrated silicon photonics for optical networks | |
Hashimoto et al. | Hybrid integration of spot-size converted laser diode on planar lightwave circuit platform by passive alignment technique | |
Paniccia et al. | Integrated photonics | |
Stampoulidis et al. | The European BOOM project: Silicon photonics for high-capacity optical packet routers | |
Kapulainen et al. | Hybrid integration of InP lasers with SOI waveguides using thermocompression bonding | |
JP5908698B2 (ja) | レーザ光源およびレーザ光源の製造方法 | |
Song et al. | Grating coupler embedded silicon platform for hybrid integrated receivers | |
Song et al. | Micromachined silicon optical bench for the low-cost optical module | |
Corbett et al. | Transfer-printing for heterogeneous integration | |
Aalto et al. | Integration of InP-based optoelectronics with silicon waveguides | |
JP3890281B2 (ja) | 光素子の搭載方法及びその装置 | |
Shubin et al. | Alignment and integration of a hybrid, external-cavity InP-SOI laser | |
WO2022254127A1 (fr) | Procédé de fabrication d'un dispositif électronique comprenant une phase de liaison |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
C06 | Publication | ||
PB01 | Publication | ||
SE01 | Entry into force of request for substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
C14 | Grant of patent or utility model | ||
GR01 | Patent grant | ||
CP01 | Change in the name or title of a patent holder | ||
CP01 | Change in the name or title of a patent holder |
Address after: Tokyo, Japan Patentee after: Citizen Watch Co., Ltd. Address before: Tokyo, Japan Patentee before: Citizen Watch Co., Ltd. |
|
CF01 | Termination of patent right due to non-payment of annual fee | ||
CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20161214 Termination date: 20190316 |