CN102683312B - 半导体器件和用于制造半导体器件的方法 - Google Patents

半导体器件和用于制造半导体器件的方法 Download PDF

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CN102683312B
CN102683312B CN201210057624.8A CN201210057624A CN102683312B CN 102683312 B CN102683312 B CN 102683312B CN 201210057624 A CN201210057624 A CN 201210057624A CN 102683312 B CN102683312 B CN 102683312B
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contact
metal
silicon substrate
layer
semiconductor device
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CN102683312A (zh
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倪其聪
王乙翕
李欣桂
苏钦豪
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
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    • B81—MICROSTRUCTURAL TECHNOLOGY
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    • B81C1/00015—Manufacture or treatment of devices or systems in or on a substrate for manufacturing microsystems
    • B81C1/00261—Processes for packaging MEMS devices
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Abstract

本发明提供了一种制造集成电路的方法，并且更具体地制造具有金属合金的半导体器件的方法。半导体器件的示例结构包括具有第一触点的第一硅衬底，该第一触点包括在该衬底和第一金属层之间的硅化物层；具有第二触点的第二硅衬底，该第二触点包括第二金属层；以及在第一触点的第一金属层和第二触点的第二金属层之间的金属合金。

Description

半导体器件和用于制造半导体器件的方法
技术领域
本发明涉及集成电路制造，并且更具体地涉及具有金属合金的半导体器件。
背景技术
微机电系统(MEMS)技术是安装在硅衬底内部的非常小的机械器件的集成，例如传感器、阀、齿轮、反射镜、以及计算机上的驱动器。因此，MEMS器件通常被称为智能机器。为了防止运行期间的外部干扰，需要接合覆盖衬底以气密地密封MEMS器件，以形成半导体器件。而且，在很多应用中，还希望被接合的衬底包括集成电路(IC)器件。
不过，在MEMS或IC器件制造中实现这些部件和工艺时，存在着一些挑战。例如，在“衬底接合”工艺中，由于在接合衬底之间的界面中产生高接触电阻材料，所以很难实现接合衬底之间的低接触电阻接合，从而增加了半导体器件不稳定和/或失效的可能性。
相应地，需要一种在接合衬底之间形成低接触电阻接合的方法。
发明内容
在一个实施例中，半导体器件包括具有第一触点的第一硅衬底，该第一触点包括在该衬底和第一金属层之间的硅化物层；具有第二触点的第二衬底，该第二触点包括第二金属层；以及在第一触点的第一金属层和第二触点的第二金属层之间的金属合金。
在另一个实施例中，一种用于制造半导体器件的方法，包括设置具有第一触点的第一硅衬底，该第一触点包括在该衬底和第一金属层之间的硅化物层；设置具有第二触点的第二硅衬底，该第二触点包括第二金属层；设置第一触点和第二触点，使它们接触；以及加热第一和第二金属层以形成金属合金，从而该金属合金将第一触点与第二触点相结合。
下面参照附图，通过以下实施例详细说明。
附图说明
当结合附图进行阅读时，根据下面详细的描述可以更好地理解本发明。应该强调的是，根据工业中的标准实践，各种部件没有被按比例绘制并且仅仅用于说明的目的。实际上，为了清楚的讨论，各种部件的数量和尺寸可以被任意增加或减少。
图1是描绘了根据本公开多个方面的包括金属合金的半导体器件的制造方法的流程图；
图2A-2F示出了根据本公开多个方面半导体器件的金属合金在多个制造阶段的示意截面图；以及
图3是利用图2A-2F中示出的步骤制造的具有金属合金的半导体器件的截面图。
具体实施方式
可以理解的是，以下公开提供了多种不同实施例或实例，用于实现本发明的不同特征。以下将描述组件和布置的特定实例以简化本发明。当然，这些仅是实例并且不旨在限制本发明。例如，在以下描述中，在第二部件上方或上形成第一部件可以包括第一部件和第二部件直接接触的实施例，也可以包括其他部件可以形成在第一部件和第二部件之间使得第一部件和第二部件不直接接触的实施例。为了简化和清楚起见，可以以不同比例随意地绘出各部件。另外，本发明可以在多个实例中重复参考符号和/或字符。这种重复用于简化和清楚，并且其本身不表示所述多个实施例和/或配置之间的关系。
参见图1，描绘了根据本公开多个方面的用于制造包括金属合金的半导体器件的方法100的流程图。方法100从步骤102开始，该步骤设置具有第一触点的第一硅衬底，该第一触点包括在该衬底和第一金属层之间的硅化物层。方法100进行到步骤104，该步骤设置具有第二触点的第二硅衬底，该第二触点包括第二金属层。方法100继续至下一步106，该步骤使第一触点和第二触点接触。方法100继续至下一步108，该步骤加热第一和第二金属层以形成金属合金，由此使金属合金使得第一触点与第二触点相结合。以下论述描绘了根据图1中方法的实施例。
图2A-2F示出了根据本公开多个方面的半导体器件200的金属合金220的在多个制造阶段的示意截面图。可以注意到，图1的方法没有生产出成品半导体器件200。相应地，可以理解的是，还可以在图1的方法100之前、期间和之后提供另外的工艺，并且此处仅仅简单描述部分其他工艺。另外，简化了图2A-2F以更好的理解本公开的发明思想。例如，虽然图形描绘了半导体器件200的金属合金220，可以理解的是，半导体器件200可以是集成电路的一部分，该集成电路进一步包括多个其他元件，例如底部填充件、引线框架等。
参见图2A-2D，提供第一硅衬底202。提供第一硅衬底202的步骤可以进一步包括部分地制造第一触点210，该触点包括在衬底202和第一金属层206之间的硅化物层208。第一硅衬底202可以包括纯硅衬底。在另一实施例中，第一硅衬底202可以是绝缘体上半导体，例如绝缘体上硅(SOI)或蓝宝石上硅。在其他实施例中，衬底202可以包括掺杂外延(epi)层、梯度半导体层，和/或进一步包括覆盖在另一不同类型半导体层上的半导体层，例如硅锗层上的硅层。
在一个实施例中，第一硅衬底202可以进一步包括多个微机电系统(MEMS)器件(未示出)。MEMS器件是安装在第一硅衬底202内部的非常小的机械器件的集成，例如传感器、阀、齿轮、反射镜、以及计算机上的驱动器。因此，MEMS器件可以用于多种器件，包括振荡器、电路、泵、加速计、以及过滤器。可以利用表面微观力学、沉积、或蚀刻技术制造MEMS器件。
在另一实施例中，第一硅衬底202可以进一步包括多个隔离部件(未示出)，例如浅沟隔离(STI)部件或硅的局部氧化(LOCOS)部件。这些隔离部件可以限定并隔离各种微电子元件(未示出)。
可以在第一硅衬底202中形成的各种微电子元件的示例包括晶体管(例如p-沟道/n-沟道金属氧化物半导体场效应晶体管(pMOSFET/nMOSFET)、双极结型晶体管(BJT)、高压晶体管、高频晶体管等)、二极管、电阻器、电容器、感应器、保险丝、和其他适合的元件。被执行以形成各种微电子元件的各种工艺包括沉积、光刻法、注入、蚀刻、热处理、和其他适合的工艺。使微电子元件相互连接以形成集成电路(IC)器件，例如逻辑器件、存储器件(例如静态随机存取存储器或SRAM)、无线射频(RF)器件、输入/输出(I/O)器件、片上系统(SoC)器件、以及其组合，和其他适合类型的器件。
衬底202进一步包括层间绝缘(ILD)层、金属间绝缘(IMD)层以及覆盖在IC器件上的金属化结构。金属化结构中的IMD层包括低-k绝缘材料、未掺杂硅酸盐玻璃(USG)、氟掺杂硅酸盐玻璃(FSG)、碳掺杂硅酸盐玻璃、氮化硅、氮氧化硅、或其他材料。低-k绝缘材料的介电常数(k值)可以大约小于3.9，或大约小于2.3。金属化结构中的金属线可以由铝、铝合金、铜、铜合金、或其他导电材料形成。本领域普通技术人员能够认识到金属化结构的形成细节。
仍然参见图2A，第一硅衬底202进一步包括凸起部分202a，该部分用于使MEMS器件或IC器件与外部触点电连接，并且包括较低部分202b以容纳MEMS器件的检测质量。被执行以形成凸起部分202a的多个工艺包括光刻法、蚀刻以及其他适合的工艺。虽然描绘了在第一硅衬底202中只形成一个凸起部分202a，应该理解的是，可以在第一硅衬底202a中形成任意数量的凸起部分202a。
参见图2B，在凸起部分202a的形成工艺之后，接着在较低部分202b上方沉积第一金属层206，并使其延伸出较低部分202b并且直至凸起部分202a上。在一个实施例中，第一金属层206包括选自由Ti、Co、Ni、W以及Pt组成的组的材料。第一金属层206可以由化学汽相沉积(CVD)、物理汽相沉积(PVD)、或其他适合的技术形成。在本实施例中，第一金属层206的厚度t1的范围为300至1000埃。
参见图2C，在第一金属层206沉积在较低部分202b上方并且延伸出该较低部分并到凸起部分202a上之后，对图2B中的中间半导体器件200执行热处理工艺，以在第一硅衬底202和第一金属层206之间形成硅化物层208。可以在例如熔炉、快速热处理(RTA)系统或其他热系统中执行热处理工艺，其中，该其他热系统适于提供用于在第一硅衬底202和第一金属层206之间的反应的热处理，以形成硅化物层208。从而，硅化物层208在第一金属化层206上。在部分实施例中，可以在RTA系统中，在约为650℃至900℃的温度下，执行热处理工艺大约30秒。
在一个实施例中，硅化物层208包括选自Ti、Co、Ni、W以及Pt的组的材料。在本实施例中，硅化物层208包括选自硅化钛、硅化钴、以及硅化镍的材料。硅化物层208能够在衬底202和第一金属化层206之间提供低电阻通路，以用于较好的整体导电性。在一个实施例中，硅化物层208的厚度t2的范围为300至600埃。由于形成硅化物层208的消耗，由此得到的第一金属层206的厚度被变薄至厚度t3。在本实施例中，第一金属化层206与硅化物层208的厚度比(t3/t2)约为1至2。
然后，通过适合的工艺(例如旋涂)在第一金属层206上方形成光刻胶层(未示出)，并且通过恰当的光刻图案法图案化该光刻胶层以形成图案化的光刻胶部件。该图案化光刻胶部件的宽度范围为30至80um。然后，利用干蚀刻工艺将图案化的光刻胶部件转印至下面的层(即，第一金属层206和硅化物层208)，以形成第一触点210(图2D中示出)。第一触点210被用于接合工艺中，以电连接相应硅衬底中的MEMS器件或IC器件和外部部件，例如第二硅衬底302(图2E中示出)的第二触点310。第一触点210的宽度W1的范围约为30至80um。之后，可以除去该光刻胶层。
然后，将第一硅衬底202接合在第二硅衬底302上，以形成半导体器件200。图2E的结构示出了翻转第一硅衬底202并在底部与第二硅衬底302连接。第二硅衬底302可以包括纯硅衬底。在另一实施例中，第二硅衬底302可以是绝缘体上半导体，例如绝缘体上硅(SOI)或蓝宝石上硅。在其他实施例中，第二硅衬底302可以包括掺杂的外延层(epi层)、梯度半导体层，和/或进一步包括覆盖在另一不同类型半导体层上的半导体层，例如硅锗层上的硅层。
在一个实施例中，第二硅衬底302可以进一步包括多个微机电系统(MEMS)器件(未示出)。MEMS器件是安装在第二硅衬底302内部的非常小的机械器件的集成，例如传感器、阀、齿轮、反射镜、以及计算机上的驱动器。因此，MEMS器件可以用于多种器件，包括振荡器、电路、泵、加速计、以及过滤器。可以利用表面微观力学、沉积、或蚀刻技术制造MEMS器件。
在另一实施例中，第二硅衬底302可以进一步包括多个隔离部件(未示出)，例如浅沟隔离(STI)部件或硅的局部氧化(LOCOS)部件。这些隔离部件可以限定并隔离各种微电子元件(未示出)。
可以在第二硅衬底302中形成的各种微电子元件的示例包括晶体管(例如p-沟道/n-沟道金属氧化物半导体场效应晶体管(pMOSFET/nMOSFET)、双极结型晶体管(BJT)、高压晶体管、高频晶体管等)、二极管、电阻器、电容器、感应器、保险丝、和其他适合的元件。被执行以形成各种微电子元件的各种工艺包括沉积、光刻法、注入、蚀刻、热处理、和其他适合的工艺。使微电子元件相互连接以形成集成电路(IC)器件，例如逻辑器件、存储器件(例如静态随机存取存储器或SRAM)、无线射频(RF)器件、输入/输出(I/O)器件、片上系统(SoC)器件、以及其组合，和其他适合的器件种类。
第二硅衬底302进一步包括层间绝缘(ILD)层、金属间绝缘(IMD)层以及层叠在集成电路器件上的金属化结构(未示出)。金属化结构中的IMD层包括低-k绝缘材料、未掺杂硅酸盐玻璃(USG)、氟掺杂硅酸盐玻璃(FSG)、碳掺杂硅酸盐玻璃、氮化硅、氮氧化硅、或其他通常使用的材料。低-k绝缘材料的介电常数(k值)可以大约小于3.9，或大约小于2.3。金属化结构中的金属线可以由铝、铝合金、铜、铜合金、或其他导电材料形成。本领域普通技术人员能够认识到金属化结构的形成细节。
第二硅衬底302进一步包括第二触点310。第二触点310是在顶层IMD层中形成的顶部金属化层，该层是导电通路的一部分并且具有经过平面化工艺(例如化学机械抛光(CMP))处理的暴露面(如果必要的话)。第二触点310用于接合工艺中，以电连接相应硅衬底中的MEMS器件或IC器件和外部部件，例如第一硅衬底202的第一触点210。换句话说，设置第一触点210与第二触点310，使它们接触(图2E中示出)。在一个实施例中，第二触点310的第二宽度W2大于第一触点210的第一宽度W1。在另一实施例中，第二触点310的第二宽度W2小于第一触点210的第一宽度W1。在本实施例中，第一触点210和第二触点310的宽度比(W1/W2)约为0.12至1.2。
第二触点310可以包括第二金属层306。用于第二金属层306的合适的材料包括，但不仅限于，例如，Al、Al合金、或其他导电材料。可以通过化学汽相沉积(CVD)、物理汽相沉积(PVD)、或其他适合的技术形成第二金属层306。在本实施例中，第二金属层306的厚度t4的范围为7500至8500埃。在一个实施例中，第二金属层306和硅化物层208的厚度比(t4/t2)约为12至25。
在设置第一触点210与第二触点310接触之前，由于暴露在空气中，在第一金属层206露出的顶面以及第二金属层306的顶面上会形成原生氧化层(未示出)。因为由于在第一和第二金属层206、306之间的原生氧化层使得第一和第二金属层206、306不会彼此形成合金，所以需要清除该原生氧化层(例如移除)。
在本公开的实施例中，利用还原气体(例如氢或NH3)、以及惰性气体(例如氩、氦、或氮)，在预清除腔室中执行预清除工艺以移除原生氧化层。还原气体和惰性气体的比率取决于如使用的具体反应腔室以及使用的具体气体等因素。
在一个实施例中，还原气体是氢并且惰性气体是氦。通过还原原生氧化层，氢反应预清除工艺可以有利地移除原生氧化层，而不需要物理轰击(bombardment)。因此，可以移除原生氧化层，而不会破坏第一金属层206露出的顶面，以及第二金属层306的顶面。因为第一金属层206和第二金属层306都相对保持平滑，这便于尝试在两个硅衬底202、302之间形成精确的间隔距离，并且保持该距离。
截至于此的工艺步骤提供了具有清洁且平滑的表面的硅衬底202、302，以使得第一金属层206和第二金属层306相互形成合金更为容易。这可以减少接合的硅衬底202、302之间的交界面中产生的缺陷，并且能够改进半导体器件的性能。
参见图2F，在使第一触点210和第二触点310接触之后，加热第一和第二金属层206、306以形成金属合金220，从而金属合金220接合第一触点210和第二触点310。尽管其他压力也是可以的，两个硅衬底202、302被约为45至55KN的压力压在一起，在第一触点210和第二触点310之间形成较弱的接合。
然后，将受压的硅衬底202、302放置在热处理腔室中。随后通过在热处理腔室中改变温度，在半导体器件200的结构上执行接合工艺，从而，通过使第一和第二金属层206、306形成合金以形成金属合金220，该金属合金连接两个硅衬底202、302。在这点上，一旦将受压硅衬底202、302放置在热处理腔室中，热处理腔室的温度会在约60秒内增加至480℃。当热处理腔室中的温度改变时，该温度可以线性变化(即，使温度倾斜)，但是这对于执行本发明不是必要的。
在本实施例中，在约为450℃至500℃的温度下且在约为45至55KN的压力下执行该加热步骤约40分钟。应该说明的是，也可以使用其他热处理温度和持续时间以在硅衬底202、302之间形成充足接合。在半导体器件200的正常运行期间，接合能够维持第一硅衬底202对准第二硅衬底302，对本公开的目的来说，该接合就是“充足的”。
在维持所述时间的热处理温度之后，热处理腔室中的温度在约6分钟内下降至低于约100℃。本领域普通技术人员能够认识到可以用于接合工艺的其他温度和时间。
此时，金属合金220可以接合第一和第二金属层206、306，并且足以使第一硅衬底202和第二硅衬底302保持连接和对齐。也就是说，金属合金220为半导体器件200提供机械支持和低电阻连接，其他导电材料例如硅化物层208提供了第一硅衬底202的MEMS器件和第二硅衬底302的IC器件之间的电连接。在一个实施例中，第一或第二硅衬底202、302之一包括微机电系统(MEMS)器件，并且另一个衬底包括集成电路(IC)器件。在另一实施例中，第一硅衬底202包括微机电系统(MEMS)器件，并且第二硅衬底302包括集成电路(IC)器件。相应地，申请人的制造半导体器件200的方法可以制造用于接合硅衬底202、302的低电阻金属合金，并且能够改进半导体器件的性能。
在本实施例中，金属合金220包括第一和第二金属层206、306的合金。金属合金220可以包括金属化合物。在本实施例中，金属化合物含有Al。在一个实施例中，金属化合物可以包括TixAly，例如TiAl或TiAl3，其中第一金属层206包括Ti，并且第二金属层306包括Al。在另一实施例中，金属化合物可以包括NixAly，例如，NiAl3、Ni2Al3、NiAl、或Ni3Al，其中第一金属层206包括Ni，并且第二金属层306包括Al。在又一实施例中，金属化合物可以包括CoxAly，例如Co2Al5或Co4Al13，其中第一金属层206包括Co，并且第二金属层306包括Al。在再一实施例中，金属化合物可以包括AlxWy，例如Al12W、Al5W或Al4W，其中第一金属层206包括W，并且第二金属层306包括Al。在再一实施例中，金属化合物可以包括PtxAly，例如Pt2Al3，其中第一金属层206包括Pt，并且第二金属层306包括Al。在本实施例中，金属合金220的厚度t5的范围为500至1500埃。在一个实施例中，金属合金220与硅化物层208的厚度比(t5/t2)约为0.8至5。
图3是半导体器件300的截面图，该半导体器件300具有利用图2A-2F中所示步骤制造的金属合金220。支撑机构(未示出)弹性地支撑MEMS器件320的检测质量，例如第一硅衬底202上的镜子，其中该镜子从第一硅衬底202漂移，以便镜子能够以任意方向倾斜。另一方面，MEMS器件320的检测质量(例如转动体)可以在第二硅衬底302上方漂移，并且可以被驱动结构(未示出)控制。应该理解的是，半导体器件300可以经受进一步的IC工艺以形成各种部件，例如底部填充件、引线框架等。
虽然以示例和以上相关实施例的方式描述了本公开，可以理解的是本发明不限于公开的实施例。相反地，本发明试图覆盖各种修改和类似布置(正如对于本领域普通技术人员显而易见的)。而且，应给予随附的权利要求最广泛的解释，以便涵盖所有这样的修改和类似布置。

Claims (18)

1.一种半导体器件，包括：
第一硅衬底，具有第一触点，所述第一触点包括在所述衬底和第一金属层之间的硅化物层，其中，所述第一硅衬底包括凸起部分，所述硅化物层形成在所述第一硅衬底的表面，并使所述硅化物层延伸出所述第一硅衬底的较低部分并且直至所述凸起部分；
第二硅衬底，具有第二触点，所述第二触点包括第二金属层；以及
金属合金，所述金属合金在所述第一触点的第一金属层和所述第二触点的第二金属层之间，所述金属合金通过所述第一金属层和所述第二金属层的相互接合形成，并且在所述相互接合之前对所述第一金属层和所述第二金属层均进行移除原生氧化层，使所述第一金属层和所述第二金属层具有平滑的表面；
其中所述第一触点和所述第二触点的宽度比为0.12至1.2；
其中所述金属合金和所述硅化物层的厚度比为0.8至5。
2.根据权利要求1所述的半导体器件，其中所述硅化物层包括选自Ti、Co、Ni、W以及Pt所构成的组的材料。
3.根据权利要求1所述的半导体器件，其中所述第一金属层包括选自Ti、Co、Ni、W以及Pt所构成的组的材料。
4.根据权利要求1所述的半导体器件，其中所述第一金属层和所述硅化物层的厚度比为1至2。
5.根据权利要求1所述的半导体器件，其中所述硅化物层在所述第一金属层上。
6.根据权利要求1所述的半导体器件，其中由所述第一硅衬底和所述第一金属层的反应得到所述硅化物层。
7.根据权利要求1所述的半导体器件，其中所述第二金属层包括Al或Al合金。
8.根据权利要求1所述的半导体器件，其中所述第二金属层和所述硅化物层的厚度比为12至25。
9.根据权利要求1所述的半导体器件，其中所述金属合金包括所述第一金属层和所述第二金属层的合金。
10.根据权利要求1所述的半导体器件，其中所述金属合金包括金属化合物。
11.根据权利要求10所述的半导体器件，其中所述金属化合物含有Al。
12.根据权利要求1所述的半导体器件，其中所述第一硅衬底或所述第二硅衬底中的一个包括微机电系统(MEMS)器件，另一个衬底包括集成电路(IC)器件。
13.根据权利要求1所述的半导体器件，其中所述第一硅衬底包括微机电系统(MEMS)器件，所述第二硅衬底包括集成电路(IC)器件。
14.一种用于制造半导体器件的方法，包括：
设置具有第一触点的第一硅衬底，所述第一触点包括在所述衬底和第一金属层之间的硅化物层，其中，所述第一硅衬底包括凸起部分，所述硅化物层形成在所述第一硅衬底的表面，并使所述硅化物层延伸出所述第一硅衬底的较低部分并且直至所述凸起部分；
设置具有第二触点的第二硅衬底，所述第二触点包括第二金属层；
设置所述第一触点和所述第二触点接触；以及
加热所述第一金属层和所述第二金属层，以形成金属合金，由此所述金属合金使得所述第一触点与所述第二触点接合，在形成所述金属合金之前对所述第一金属层和所述第二金属层均进行移除原生氧化层，使所述第一金属层和所述第二金属层具有平滑的表面；
其中所述第一触点和所述第二触点的宽度比为0.12至1.2；
其中所述金属合金和所述硅化物层的厚度比为0.8至5。
15.根据权利要求14所述的方法，其中在为450℃至500℃的温度下执行所述加热步骤。
16.根据权利要求14所述的方法，其中在为45KN至55KN的压力下执行所述加热步骤。
17.根据权利要求14所述的方法，其中由所述第一硅衬底和所述第一金属层的反应形成所述硅化物层。
18.根据权利要求17所述的方法，其中在为650℃至900℃的温度下执行形成所述硅化物层的步骤。
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