TWI451553B - 半導體裝置及其製造方法 - Google Patents

半導體裝置及其製造方法 Download PDF

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Publication number
TWI451553B
TWI451553B TW100123818A TW100123818A TWI451553B TW I451553 B TWI451553 B TW I451553B TW 100123818 A TW100123818 A TW 100123818A TW 100123818 A TW100123818 A TW 100123818A TW I451553 B TWI451553 B TW I451553B
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Taiwan
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contact
layer
metal layer
metal
substrate
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TW100123818A
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English (en)
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TW201238025A (en
Inventor
Chyi Tsong Ni
I Shi Wang
Hsin Kuei Lee
Ching Hou Su
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Taiwan Semiconductor Mfg
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Publication of TW201238025A publication Critical patent/TW201238025A/zh
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    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C1/00—Manufacture or treatment of devices or systems in or on a substrate
    • B81C1/00015—Manufacture or treatment of devices or systems in or on a substrate for manufacturing microsystems
    • B81C1/00261—Processes for packaging MEMS devices
    • B81C1/00269—Bonding of solid lids or wafers to the substrate
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Description

半導體裝置及其製造方法
本發明係關於積體電路的製造，尤其是關於具有金屬合金的半導體裝置。
微機電系統(Micro-electro-mechanical system,MEMS)技術係安裝於矽基板內部之非常微小的機械裝置之整合，例如感測器(sensors)、閥(valves)、齒輪(gears)、反射鏡、以及電腦上的驅動器(drivers)。因此，微機電系統裝置常被稱作智慧型機器(intelligent machines)。為了避免在運作期間的內部干擾，其可能需要與覆蓋基板(cap substrate)接合來密封微機電系統裝置，以形成一半導體裝置。此外，在許多的應用中，接合的基板尚需要包括積體電路裝置。
然而，在微機電系統或積體電路(integrated circuit，IC)裝置的製造上，欲實現這樣的功能及製程仍存在許多挑戰。例如，在”基板接合(substrate bonding)”製程中，由於在接合的基板之間會產生高接觸電阻的材料(high-contact resistance materials)，進而增加半導體裝置的不穩定性及/或半導體儀之器故障的可能性，因此在接合的基板之間要達到低接觸電阻接合(low-contact-resistance bond)是很困難的。
因此，業界亟需一種在接合的基板之間形成低接觸電阻接合的方法。
依據本發明的一或多個實施例，揭示一種半導體裝置，包括：一第一矽基板，具有一第一接點，該第一接點包括一介於該基板及一第一金屬層之間的一矽化物層；一第二矽基板，具有一第二接點，該第二接點包括一第二金屬層；以及一金屬合金，介於該第一接點的該第一金屬層與該第二接點的該第二金屬層之間。
依據本發明的一或多個實施例，揭示一種半導體裝置的製造方法，包括：提供一第一矽基板，其具有一第一接點，該第一接點包括介於該基板及一第一金屬層之間的矽化物層；提供一第二矽基板，其具有一第二接點，該第二接點包括一第二金屬層；配置該第一接點，使該第一接點與該第二接點接觸；以及加熱該第一與該第二金屬層，以形成一金屬合金，藉由該金屬合金將該第一接點接合至該第二接點。
為讓本發明之上述和其他目的、特徵、和優點能更明顯易懂，下文特舉出較佳實施例，並配合所附圖式，作詳細說明如下：
本發明接下來將會提供許多不同的實施例以實施本發明中不同的特徵。各特定實施例中的組成及配置將會在以下作描述以簡化本發明。這些為實施例並非用於限定本發明。此外，一第一元件形成於一第二元件“上方”、“之上”、“下方”或“之下”可包含實施例中的第一元件與第二元件直接接觸，或也可包含第一元件與第二元件之間更有其他額外元件使第一元件與第二元件無直接接觸。各種元件可能以任意不同比例顯示以使圖示清晰簡潔。此外，在本發明各種不同的範例中，為了簡化與清晰的目的，將重複地使用元件符號及字母，然而其本身並不決定各種實施例及/或結構配置之間的關係。
第1圖係說明在本發明之各種不同的實施例中，包含金屬合金之半導體裝置的製造方法100之流程圖。方法100開始於步驟102，其中提供一第一基板具有一第一接點，此第一接點包括一介於基板與第一金屬層之間的矽化物層。方法100繼續進行到步驟104，其中提供一第二矽基板，其具有包括第二金屬層的第二接點。方法100繼續進行到步驟106，其中將第一接點配置與第二接點相接觸。方法100繼續進行到步驟108，其中加熱第一及第二金屬層以形成金屬合金，藉此金屬合金將第一接點接合至第二接點。上述討論配合所述方法之實施例係根據第1圖。
第2A至2F圖係說明在本發明之各種不同的實施例中，不同製造階段的半導體裝置200之金屬合金220的剖面示意圖。值得注意的是，第1圖中的方法並非生產完整的半導體裝置200。因此，需瞭解的是，可在第1圖的方法之前、之間、以及之後，增加製程，且在本說明書中僅簡短地描述了一些其他的製程。同樣地，第2A至2F圖為了使本發明的概念更容易瞭解而被簡化。例如，雖然圖式說明了半導體裝置200的金屬合金220，應可瞭解的是，半導體裝置200可為積體電路的一部分，積體電路更包括許多其他的組件，像是底部填充(under-fill)、引線框架(lead-frame)…等等。
參閱第2A至2D圖，係提供第一矽基板202。提供第一矽基板202的步驟可更包括部分製造第一接點210，上述第一接點210包括介於基板202及第一金屬層206之間的矽化物層208。第一矽基板202可包括一純的矽基板(pure silicon substrate)。在另一個實施例中，第一矽基板202可為一在絕緣體上的半導體，例如絕緣體上矽晶(silicon on insulator，SOI)或藍寶石上矽晶(silicon on sapphire)。在其他的實施例中，基板202可包括一摻雜的磊晶層(epitaxial(epi) layer)、一梯度半導體層(gradient semiconductor layer)、及/或可更包括一半導體層置於另一個不同類型之半導體層上，例如矽層位於矽鍺層上。
在一實施例中，第一矽基板202可更包括複數個微機電系統裝置(未顯示)。微機電系統裝置係安裝於矽基板202內部之非常微小的機械裝置之整合，例如感測器(sensors)、閥(valves)、齒輪(gears)、反射鏡、以及電腦上的驅動器(drivers)。因此，微機電系統裝置可用於各種裝置，包括震動器(oscillators)、通道(channels)、泵、加速度計(accelerometers)、以及濾片(filters)。可利用表面微機械(micromechanics)、沉積、或蝕刻技術，來製造微機電系統裝置。
在另一個實施例中，第一矽基板202可更包括複數個隔離元件(isolation features)(未顯示)，例如淺溝槽隔離(shallow trench isolation，STI)元件，或矽的局部氧化(local oxidation of silicon，LOCOS)元件。隔離元件可定義及隔離各種不同的微電子元件(microelectronic elements)(未顯示)。
可形成於第一矽基板202中之各種不同的微電子元件之實施例包括電晶體(例如p通道/n通道金氧半場效電晶體(p-channel/n-channel metal oxide semiconductor field effect transistors，pMOSFETs/nMOSFETs)、雙極性接面電晶體(bipolar junction transistors，BJT)、高壓電晶體(high voltage transistors)、高頻電晶體(high frequency transistors)…等等)；二極體；電阻；電容；電感(inductors)；引線(fuses)；以及其他合適的元件。用以形成各種不同的微電子元件所進行之各種不同的步驟，包括沉積製程、微影製程、植入、蝕刻、退火製程(annealing)、以及其他合適的製程。微電子元件之間互相連結以形成積體電路(integrated circuit，IC)裝置，例如邏輯裝置(logic device)、記憶裝置(memory device)(例如靜態隨機存儲記憶體(static random access memory，SRAM))、無線電頻率(radio frequency，RF)裝置、輸入/輸出(input/output，I/O)裝置、單晶片系統(system-on-chip，SoC)裝置、上述之組合、以及其他合適類型的裝置。
基板202更包括：層間介電層(inter-layer dielectric (ILD) layers)、金屬間介電層(inter-metal dielectric(IMD) layers)、以及在積體電路裝置上方的金屬結構。上述在金屬結構中的金屬間介電層，包括低介電常數(low-k)的介電材料、未摻雜的矽酸鹽玻璃(un-doped silicate glass，USG)，氟摻雜的矽酸鹽玻璃(fluorine-doped silicate glass，FSG)、碳摻雜的矽酸鹽玻璃(carbon-doped silicate glass)、氮化矽(silicon nitride)、氮氧化矽(silicon oxynitride)、或其他的材料。低介電常數的介電材料之介電常數(k value)可小於約3.9或小於約2.3。在金屬結構中的金屬導線可由鋁、鋁合金、銅、銅合金、或其他導電材料所形成。所屬技術領域中具有通常知識者應可瞭解金屬結構的形成細節。
繼續參閱第2A圖，第一矽基板202更包括一升高的部分202a，用來將微機電系統裝置或積體電路裝置電性連結至外部接點，以及一降低的部分202b以提供(accommodate)微機電系統裝置的保證質量(proof mass)。用以形成上述升高的部分202a所進行之各種不同的步驟，包括微影製程、蝕刻製程、以及其他合適的製程。雖然僅舉例說明一個升高的部分202a形成於第一矽基板202a中，但需瞭解第一矽基板202中可形成任意數量之升高的部分202a。
參閱第2B圖，在升高的部分202a形成製程之後，第一金屬層206沉積於降低的部分202b之上，並延伸超出降低的部分202b，且延伸至升高的部分202a。在一實施例中，第一金屬層206包括一材料，其擇自由下列所組成之群組：Ti、Co、Ni、W、以及Pt。可藉由化學氣相沉積(chemical vapor deposition，CVD)、物理氣相沉積(physical vapor deposition，PVD)、或其他合適的技術，來形成第一金屬層206。在本發明的實施例中，第一金屬層206的厚度t1 之範圍介於300至1000。
參閱第2C圖，在第一金屬層206沉積於降低的部分202b之上，並延伸超出降低的部分202b，且延伸至升高的部分202a之後，對第2B圖所示之半導體裝置200的中間體(intermediate)進行一退火製程，以在第一矽基板202及第一金屬層206之間形成一矽化物層208。上述退火製程可進行於，例如：在加熱爐(furnace)中、在快速熱退火系統(rapid thermal anneal(RTA) system)、或其他適合的熱系統(thermal system)中，其中上述其他適合的熱系統用來提供第一矽基板202與第一金屬層206之間之形成矽化物層208的反應之熱處理。因此，矽化物層208位於第一金屬層206上。在一些實施例中，退火製程可於攝氏約650度至900度的溫度下進行，於快速熱退火系統中維持約30秒。
在一實施例中，矽化物層208包括一材料，其擇自由下列所組成之群組：Ti、Co、Ni、W、以及Pt。在本發明的實施例中，矽化物層208可包括一材料擇自：矽化鈦(titanium silicide)、矽化鈷(cobalt silicide)、矽化鎳(nickel silicide)、矽化鎢(Tungsten silicide)、以及矽化鉑(Platium silicide)。矽化物層208可包括一介於基板202與第一金屬層206之間的低電阻通道(low-resistance path)，用以維持良好的整體導電率(overall electrical conductivity)。在一實施例中，矽化物層208的厚度t2 範圍介於約300至600。第一金屬層206的最終厚度，由於在形成矽化物層208中會被消耗，因而被薄化至厚度t3 。在本發明的實施例中，第一金屬層206與矽化物層208之間的厚度比(t3 /t2 )介於約1至2。
接著，藉由合適的製程，例如旋轉式塗佈(spin-on coating)，在第一金屬層206上方形成一光阻層(未顯示)，並且藉由適當的微影技術之圖案化方法(lithography patterning method)，將上述光阻層圖案化，以形成一經圖案化的光阻特徵(patterned photoresist feature)。上述經圖案化的光阻特徵的寬度範圍介於約30至80 μm。然後可利用乾蝕刻製程將上述經圖案化的光阻元件轉移至下層(亦即，第一金屬層206以及矽化物層208)，以形成第一接點210(如第2D圖中所示)。第一接點210係用於接合製程中，以便在個別的矽基板上將微機電系統裝置或積體電路裝置電性連結至外部元件(external features)，例如第二矽基板302的第二接點310(如第2E圖中所示)。第一接點210的第一寬度W1 範圍介於約30-80μm。在此之後，可將光阻層剝除(stripped)。
接著，將第一矽基板202接合至第二矽基板302，以形成半導體裝置200。第2E圖中所示結構係第一矽基板202上下反轉(flipped upside down)，並且在底部與第二矽基板302相銜接(engaged with)。第二矽基板302可包括一純矽基板。在另一實施例中，第二矽基板302可為一在絕緣體上的半導體，例如在絕緣體上的矽(silicon on insulator，SOI)或在藍寶石上的矽。在另一實施例中，第二矽基板302可包括一摻雜的磊晶層(epitaxial(epi) layer)、一梯度半導體層(gradient semiconductor layer)、及/或可更包括一半導體層置於另一個不同類型之半導體層上，例如矽層位於矽鍺層上。
在一實施例中，第二矽基板302可更包括複數個微機電系統(microelectromechanical system，MEMS)裝置(未顯示)。微機電系統裝置係安裝於第二矽基板302內部之非常微小的機械裝置之整合，例如感測器(sensors)、閥(valves)、齒輪(gears)、反射鏡、以及電腦上的驅動器(drivers)。因此，微機電系統裝置可用於各種裝置，包括震動器(oscillators)、通道(channels)、泵、加速度計(accelerometers)、以及濾片(filters)。可利用表面微機械(micromechanics)、沉積、或蝕刻技術，來製造微機電系統裝置。
在另一個實施例中，第二矽基板302可更包括複數個隔離元件(isolation features)(未顯示)，例如淺溝槽隔離(shallow trench isolation，STI)元件，或矽的局部氧化(local oxidation of silicon，LOCOS)元件。隔離元件可定義及隔離各種不同的微電子元件(microelectronic elements)(未顯示)。
可形成於第二矽基板302中之各種不同的微電子元件之實施例包括電晶體(例如p通道/n通道金氧半場效電晶體(p-channel/n-channel metal oxide semiconductor field effect transistors，pMOSFETs/nMOSFETs)、雙極性接面電晶體(bipolar junction transistors，BJT)、高壓電晶體(high voltage transistors)、高頻電晶體(high frequency transistors)…等等)；二極體；電阻；電容；電感(inductors)；引線(fuses)；以及其他合適的元件。用以形成各種不同的微電子元件所進行之各種不同的步驟，包括沉積製程、微影製程、植入、蝕刻、退火製程(annealing)、以及其他合適的製程。微電子元件之間互相連結以形成積體電路(integrated circuit，IC)裝置，例如邏輯裝置(logic device)、記憶裝置(memory device)(例如靜態隨機存儲記憶體(static random access memory，SRAM))、無線電頻率(radio frequency，RF)裝置、輸入/輸出(input/output，I/O)裝置、單晶片系統(system-on-chip，SoC)裝置、上述之組合、以及其他合適類型的裝置。
第二矽基板302更包括：層間介電層(inter-layer dielectric(ILD) layers)、金屬間介電層(inter-metal dielectric(IMD) layers)、以及在積體電路裝置上方的金屬結構(未顯示)。上述在金屬結構中的金屬間介電層，包括低介電常數(low-k)的介電材料、未摻雜的矽酸鹽玻璃(un-doped silicate glass，USG)、氟摻雜的矽酸鹽玻璃(fluorine-doped silicate glass，FSG)、碳摻雜的矽酸鹽玻璃(carbon-doped silicate glass)、氮化矽(silicon nitride)、氮氧化矽(silicon oxynitride)、或其他的材料。低介電常數的介電材料之介電常數(k value)可小於約3.9或小於約2.3。在金屬結構中的金屬導線可由鋁、鋁合金、銅、銅合金、或其他導電材料所形成。所屬技術領域中具有通常知識者應可瞭解金屬結構的形成細節。
第二矽基板302更包括一第二接點310。第二接點310為形成於頂層金屬間介電層(top-level IMD layer)的頂金屬層(top metallization layer)，其中上述頂金屬層為導電線的一部分，且若有需要，上述頂金屬層可具有暴露的表面，此暴露的表面經過如化學機械研磨拋光(chemical mechanical polishing，CMP)等的平坦化製程(planarization process)的處理。第二接點310係用於接合製程中，以便在個別的矽基板上將微機電系統裝置或積體電路裝置電性連結至外部元件(external features)，例如第一矽基板202的第一接點210。換句話說，第一接點210被配置與第二接點310相接觸(如第2E圖中所示)。在一實施例中，第二接點310的第二寬度W2 大於第一接點210的第一寬度W1 。在另一實施例中，第二接點310的第二寬度W2 小於第一接點210的第一寬度W1 。在本實施例中，第一接點210的第一寬度W1 與第二接點310的第二寬度W2 的寬度比(W1 /W2 )介於約0.12-1.2。
第二接點310可包括第二金屬層306。適合作為第二金屬層306的材料可包括，但不限於，例如鋁、鋁合金、或其他導電材料。可藉由化學氣相沉積(chemical vapor deposition，CVD)、物理氣相沉積(physical vapor deposition，PVD)、或其他合適的技術，來形成第二金屬層306。在本發明的實施例中，第二金屬層306的厚度t4 之範圍介於7500至8500。在一實施例中，第二金屬層306與矽化物層208之厚度比(t4 /t2 )範圍介於約12至25。
在將第一接點210配置與第二接點310相接觸之前，原生氧化物(native oxides)(未顯示)可形成於第一金屬層206之暴露的頂面上，且第二金屬層306由於暴露在空氣中，故也會有相同的現象。由於當有原生氧化物存在時，第一及第二金屬層206、306彼此之間不會形成合金，因此需清理原生氧化物(亦即，將原生氧化物移除)。
在本發明的實施例中，利用像是氫氣或NH3 等的還原性氣體(reducing gas)、以及像是氬氣、氦氣或氮氣等的惰性氣體，於一預清理室(pre-clean chamber)中進行原生氧化物移除的預清理製程(pre-clean process)。還原性氣體與惰性氣體的比值取決於例如所使用的特定反應室以及所使用的特定氣體等變因。
在一實施例中，上述還原性的氣體為氫氣，以及上述惰性氣體為氦氣。氫反應之預清理製程(hydrogen reactive pre-clean process)可有利於藉由將原生氧化物還原來移除原生氧化物，而不需物理撞擊(physical bombardment)。因此，可移除原生氧化物而不破壞第一金屬層206之暴露的頂面以及第二金屬層306的頂面。如此一來，由於第一金屬層206與第二金屬層306兩者皆保持相對的平滑，可有助於介於兩矽基板202、302之間的精確間距之形成與維持。
上述製程步驟進行到這裡，已提供了具有新鮮且光滑表面的矽基板202、203，使得第一金屬層206與第二金屬層306彼此之間較容易形成合金。這樣一來，可減少在接合的矽基板202、302之間的界面之缺陷的產生，並且提升半導體裝置的性能。
參閱第2F圖，在將第一接點210配置與第二接點310相接觸之後，加熱第一與第二金屬層206、306以形成一金屬合金220，以便讓此金屬合金220將第一接點210接合至第二接點310。雖然也可能為其他壓力，兩個矽基板202、203在約45至55 kN的壓縮力下被同時擠壓在一起，以在第一接點210與第二接點310之間形成一微弱的接合。
上述經擠壓後的矽基板202、203被放置於退火室(annealing chamber)中。然後，為了藉由第一及第二金屬層產生的合金將兩個矽基板202、203耦合，來形成金屬合金220，可利用改變在退火室中的溫度，在半導體裝置220的結構上進行接合製程。就這一點而言，一旦經擠壓後的矽基板202、203被置於退火室之中，即在約60秒內將退火室的溫度升高至約攝氏480度。雖然實施本發明並不絕對需要以下條件，但是當改變退火室的溫度時，可以線性方式來改變溫度(亦即，使溫度呈現一”坡度變化”)。
在本實施例中，加熱的步驟在約45至55 kN的壓力下，以及攝氏約450度至500度的溫度下持續進行約40分鐘。須注意的是，也可能採用其他退火的溫度以及持續的時間，在矽基板202、302之間形成足夠充分的接合。此處的”充分”接合是指，當在半導體儀器200的正常運作期間，能夠維持第一矽基板202與第二矽基板302對位的目的。
在退火溫度維持一段規定的時間後，退火室的溫度在6秒內下降至攝氏約100度以下。本技術領域中具有通常知識者應可瞭解接合製程亦可能採用其他的溫度及時間。
這個時候，金屬合金220可接合第一及第二金屬層206、306，並且足夠將第一矽基板202維持黏附並對齊至第二矽基板302。換句話說，金屬合金220提供了具有機械支撐(mechanical support)及低電阻連結(low-resistance connection)的半導體裝置200，且其他的導電材料，如矽化物層208，提供了一介於第一矽基板202的微機電系統裝置與第二矽基板302的積體電路裝置之間的電性連結。在一實施例中，第一或第二矽基板202、203的其中之一包括一微機電系統裝置，以及其他的基板包括一積體電路裝置。在另一個實施例中，第一矽基板202包括一微機電系統裝置，以及第二矽基板302包括一積體電路裝置。因此，本發明所提供之半導體裝置200的製造方法，可製造接合矽基板202、203之低電阻的金屬合金，並且提升半導體裝置的性能。
在本實施例中，金屬合金220包括第一及第二金屬層206、306的合金。金屬合金220可包括一金屬化合物。在本實施例中，上述金屬化合物包括鋁(Al)。在一實施例中，上述金屬化合物可包括Tix Aly ，例如TiAl或TiAl3 ，其中第一金屬層206包括鈦(Ti)以及第二金屬層306包括鋁(Al)。在另一實施例中，上述金屬化合物可包括Nix Aly ，例如NiAl3 、Ni2 Al3 、NiAl、或Ni3 Al，其中第一金屬層206包括鎳(Ni)以及第二金屬層306包括鋁(Al)。在又一實施例中，上述金屬化合物可包括Cox Aly ，例如Co2 Al5 或Co4 Al13 ，其中第一金屬層206包括鈷(Co)以及第二金屬層306包括鋁(Al)。在更一實施例中，上述金屬化合物可包括Alx Wy ，例如Al12 W、Al5 W、或Al4 W，其中第一金屬層206包括鎢(W)以及第二金屬層306包括鋁(Al)。在另一實施例中，上述金屬化合物可包括Ptx Aly ，例如Pt2 Al3 ，其中第一金屬層206包括鉑(Pt)以及第二金屬層306包括鋁(Al)。在本實施例中，金屬合金220的厚度t5 範圍介於500至1500。在一實施例中，金屬合金220與矽化物層208的厚度比(t5 /t2 )介於約0.8至5。
第3圖係說明具有利用第2A至2F圖中所示之步驟來製造的金屬合金220之半導體裝置300的剖面示意圖。一支撐機構(未顯示)彈性支撐微機電系統裝置320的保證質量(mass proof)，例如在第一矽基板202上的鏡子，其中上述鏡子自第一矽基板202浮置(floats)，如此一來上述鏡子能夠以任意方向傾斜。另一方面，微機電系統裝置320的質量保證，例如一旋轉器(rotor)，可在第二矽基板302上浮置，並且由一驅動結構(driving structure)(未顯示)控制。應可瞭解，可對半導體裝置300更進一步進行積體電路製程，以形成各種不同的元件，例如底部填充(under-fill)、引線框架(lead-frame)…等等。
雖然本發明已詳細描述並參照其具體實施例，然可瞭解的是，以上描述係為性質上的示範與說明，其旨在說明本發明與其最佳實施例。透過常規的試驗，任何所屬技術領域中具有通常知識者，在不脫離本發明之精神和範圍內，當可作各種不同之更動與潤飾。因此本發明之保護範圍並不限於以上描述，當視後附之申請專利範圍所界定者為準。
100．．．方法
102．．．步驟
104．．．步驟
106．．．步驟
108．．．步驟
200．．．半導體裝置
202．．．第一矽基板
202a．．．矽基板升高的部分
202b．．．矽基板降低的部分
206．．．第一金屬層
208．．．矽化物層
210．．．第一接點
220．．．金屬合金
300‧‧‧半導體裝置
302‧‧‧第二矽基板
306‧‧‧第二金屬層
310‧‧‧第二接點
320‧‧‧微機電系統裝置
t1 ‧‧‧第一金屬層的厚度
t2 ‧‧‧矽化物層的厚度
t3 ‧‧‧第一金屬層的最終厚度
t4 ‧‧‧第二金屬層的厚度
t5 ‧‧‧接合墊
W1 ‧‧‧第一接點的第一寬度
W2 ‧‧‧第二接點的第二寬度
第1圖係說明在本發明之各種不同的實施例中，製造包含金屬合金之半導體裝置的流程圖。
第2A至2F圖係說明在本發明之各種不同的實施例中，不同製造階段的半導體裝置之金屬合金的剖面示意圖。
第3圖係說明具有利用第2A至2F圖中所示之步驟來製造的金屬合金之半導體裝置的剖面示意圖。
202．．．第一矽基板
206．．．第一金屬層
208．．．矽化物層
210．．．第一接點
220．．．金屬合金
300．．．半導體裝置
302．．．第二矽基板
306．．．第二金屬層
310．．．第二接點

Claims (10)

  1. 一種半導體裝置，包括：一第一矽基板，具有一第一接點，該第一接點包括一介於該基板及一第一金屬層之間的一矽化物層，其中該第一金屬層與該矽化物層的厚度比介於1至2之間；一第二矽基板，具有一第二接點，該第二接點包括一第二金屬層；以及一金屬合金，介於該第一接點的該第一金屬層與該第二接點的該第二金屬層之間。
  2. 如申請專利範圍第1項所述之半導體裝置，其中該第一接點與該第二接點的寬度比介於約0.12至1.2之間。
  3. 如申請專利範圍第1項所述之半導體裝置，其中該矽化物層包括一材料，其擇自由下列所組成之群組：Ti、Co、Ni、W、以及Pt，且其中該第一金屬層包括一材料，其擇自由下列所組成之群組：Ti、Co、Ni、W、以及Pt。
  4. 如申請專利範圍第1項所述之半導體裝置，其中該第一金屬層與該第二金屬層的厚度比介於約1至2之間。
  5. 如申請專利範圍第1項所述之半導體裝置，其中該第二金屬層與該矽化物層的厚度比介於約12至25之間。
  6. 如申請專利範圍第1項所述之半導體裝置，其中該金屬合金與該矽化物層的厚度比介於約0.8至5之間。
  7. 如申請專利範圍第1項所述之半導體裝置，其中該第一或該第二矽基板的其中之一包括一微機電系統裝置，以及另一基板包括一積體電路裝置。
  8. 一種半導體裝置的製造方法，包括： 提供一第一矽基板，其具有一第一接點，該第一接點包括介於該基板及一第一金屬層之間的矽化物層，其中該第一金屬層與該矽化物層的厚度比介於1至2之間；提供一第二矽基板，其具有一第二接點，該第二接點包括一第二金屬層；配置該第一接點，使該第一接點與該第二接點接觸；以及加熱該第一與該第二金屬層，以形成一金屬合金，藉由該金屬合金將該第一接點接合至該第二接點。
  9. 如申請專利範圍第8項所述之半導體裝置的製造方法，其中該加熱的步驟於攝氏約450度至500度的溫度及約45至55KN的壓力下進行。
  10. 如申請專利範圍第8項所述之半導體裝置的製造方法，其中該矽化物層由該第一矽基板及該第一金屬層的反應所形成，且其中形成該矽化物層的步驟於攝氏約650度至900度的溫度下進行。
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Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20140260704A1 (en) * 2013-03-15 2014-09-18 Invensense, Inc. Device and system for integrated sensor system (iss)
US9254999B2 (en) * 2013-11-21 2016-02-09 Taiwan Semiconductor Manufacturing Co., Ltd Mechanisms for forming micro-electro mechanical device
SG10201800546XA (en) 2018-01-22 2019-08-27 Mastercard International Inc Electronic transaction data processing systems and methods

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5217922A (en) * 1991-01-31 1993-06-08 Hitachi, Ltd. Method for forming a silicide layer and barrier layer on a semiconductor device rear surface
US20060249847A1 (en) * 2005-05-03 2006-11-09 Rosemount Aerospace Inc. Substrate with bonding metallization
US7442570B2 (en) * 2005-03-18 2008-10-28 Invensence Inc. Method of fabrication of a AL/GE bonding in a wafer packaging environment and a product produced therefrom
US20090250736A1 (en) * 2008-04-08 2009-10-08 Jae-Man Yoon Semiconductor device
TW201034227A (en) * 2008-12-22 2010-09-16 Du Pont Compositions and processes for forming photovoltaic devices

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE69123175T2 (de) * 1990-05-31 1997-04-03 Canon Kk Verfahren zur Verdrahtung einer Halbleiterschaltung
US5102821A (en) * 1990-12-20 1992-04-07 Texas Instruments Incorporated SOI/semiconductor heterostructure fabrication by wafer bonding of polysilicon to titanium
US5290715A (en) * 1991-12-31 1994-03-01 U.S. Philips Corporation Method of making dielectrically isolated metal base transistors and permeable base transistors
JP3584635B2 (ja) * 1996-10-04 2004-11-04 株式会社デンソー 半導体装置及びその製造方法
JP4029473B2 (ja) * 1997-12-15 2008-01-09 セイコーエプソン株式会社 固体接合方法およびその装置、導体接合方法、パッケージ方法
US6362078B1 (en) * 1999-02-26 2002-03-26 Intel Corporation Dynamic threshold voltage device and methods for fabricating dynamic threshold voltage devices
US6740567B2 (en) * 2001-06-20 2004-05-25 Taiwan Semiconductor Manufacturing Co., Ltd Laminating method for forming integrated circuit microelectronic fabrication
US20030006062A1 (en) * 2001-07-06 2003-01-09 Stone William M. Interconnect system and method of fabrication
EP1296374B1 (en) * 2001-09-14 2012-09-05 STMicroelectronics Srl Process for bonding and electrically connecting microsystems integrated in several distinct substrates
US6969667B2 (en) * 2002-04-01 2005-11-29 Hewlett-Packard Development Company, L.P. Electrical device and method of making
EP1600249A1 (en) * 2004-05-27 2005-11-30 Koninklijke Philips Electronics N.V. Composition of a solder, and method of manufacturing a solder connection
US20080246152A1 (en) * 2007-04-04 2008-10-09 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device with bonding pad
US8304324B2 (en) * 2008-05-16 2012-11-06 Corporation For National Research Initiatives Low-temperature wafer bonding of semiconductors to metals
US8058143B2 (en) * 2009-01-21 2011-11-15 Freescale Semiconductor, Inc. Substrate bonding with metal germanium silicon material
US10040681B2 (en) * 2009-08-28 2018-08-07 Miradia Inc. Method and system for MEMS devices

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5217922A (en) * 1991-01-31 1993-06-08 Hitachi, Ltd. Method for forming a silicide layer and barrier layer on a semiconductor device rear surface
US7442570B2 (en) * 2005-03-18 2008-10-28 Invensence Inc. Method of fabrication of a AL/GE bonding in a wafer packaging environment and a product produced therefrom
US20060249847A1 (en) * 2005-05-03 2006-11-09 Rosemount Aerospace Inc. Substrate with bonding metallization
US20090250736A1 (en) * 2008-04-08 2009-10-08 Jae-Man Yoon Semiconductor device
TW201034227A (en) * 2008-12-22 2010-09-16 Du Pont Compositions and processes for forming photovoltaic devices

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