CN102637576B

CN102637576B - Semiconductor structure and preparation method thereof

Info

Publication number: CN102637576B
Application number: CN201110035886.XA
Authority: CN
Inventors: 吕函庭; 萧逸璇
Original assignee: Macronix International Co Ltd
Current assignee: Macronix International Co Ltd
Priority date: 2011-02-10
Filing date: 2011-02-10
Publication date: 2015-03-04
Anticipated expiration: 2031-02-10
Also published as: CN102637576A

Abstract

The invention discloses a semiconductor structure and a preparation method thereof. The preparation method comprises the following steps of: forming a first silicon-containing conducting material on a substrate; forming a second silicon-containing conducting material on the first silicon-containing conducting material, wherein the first and second silicon-containing conducting materials have different doping conditions; and thermally oxidizing the first and second silicon-containing conducting materials to convert the whole first silicon-containing conducting material to an insulation oxide structure and convert the second silicon-containing conducting material to a silicon-containing conducting structure and an insulation oxide layer.

Description

Semiconductor structure and manufacture method thereof

Technical field

The present invention relates to semiconductor structure and manufacture method thereof, particularly relate to characteristic good and the semiconductor structure that size is little and manufacture method thereof.

Background technology

Storage device is used in many products, such as, in the memory element of MP3 player, digital camera, computer archive etc.Along with the increase of application, the demand for storage device also tends to less size, larger memory capacity.In response to this demand, need the storage device manufacturing high component density.

It is use three-dimensional stacked storage device that designers develop a kind of method improving density of memory devices, for reaching higher memory capacity, reduces the cost of each bit simultaneously.But the micro limit of the memory cell size of this kind of storage device is still greater than 50nm at present, is difficult to great breakthrough.The element material that the usefulness of storage device can also can be used and limiting to some extent.

Summary of the invention

The object of the invention is to a kind of semiconductor structure and manufacture method thereof, can the good and semiconductor structure that size is little of Formation and characteristics.

For reaching above-mentioned purpose, the invention provides a kind of manufacture method of semiconductor structure.Its method comprises the following steps.Substrate forms the first siliceous electric conducting material.First siliceous electric conducting material forms the second siliceous electric conducting material.First siliceous electric conducting material has different doping conditions from the second siliceous electric conducting material.The siliceous electric conducting material of thermal oxidation first and the second siliceous electric conducting material, to make the first siliceous electric conducting material all be transformed into insulating oxide structure, the second siliceous electric conducting material is transformed into siliceous conductive structure and insulating oxide.

A kind of semiconductor structure is provided.Semiconductor structure comprises substrate, insulating oxide structure, siliceous conductive structure and insulating oxide.Insulating oxide structure is formed in substrate.Siliceous conductive structure and insulating oxide are formed in insulating oxide structure.Insulating oxide structure and insulating oxide one of at least have beak profile.。

Preferred embodiment cited below particularly, and coordinate appended accompanying drawing, be described in detail below:

Accompanying drawing explanation

Fig. 1 to Fig. 4 is the manufacture method of semiconductor structure in one embodiment of the invention;

Fig. 5 is the semiconductor device of one embodiment of the invention.

Main element symbol description

2: substrate

4: the first siliceous electric conducting materials

6: the second siliceous electric conducting materials

8,22,122: stacked structure

16: insulating oxide structure

18,118: siliceous conductive structure

20: insulating oxide

124: dielectric element

126: conductor wire

128,130,132: dielectric layer

D: the width of stacked structure

W: the distance between stacked structure

Embodiment

Fig. 1 to Fig. 4 illustrates the manufacture method of semiconductor structure in an embodiment.Please refer to Fig. 1, stacking first siliceous electric conducting material 4 and the second siliceous electric conducting material 6 in substrate 2.Second siliceous electric conducting material 6 is separated from each other by the first siliceous electric conducting material 4.For example, the thickness T1 of the first siliceous electric conducting material 4 is about 20nm.The thickness T2 of the second siliceous electric conducting material 6 is about 40nm.

Please refer to Fig. 1, in one embodiment, substrate 2 is monocrystalline silicon, and the first siliceous electric conducting material 4 and the second siliceous electric conducting material 6 are the monocrystalline silicon formed from substrate 2 epitaxial growth.For example, substrate 2 is monocrystalline silicon; First siliceous electric conducting material 4 is the monocrystalline silicon formed from substrate 2 epitaxial growth; Second siliceous electric conducting material 6 is the monocrystalline silicon formed from the first siliceous electric conducting material 4 epitaxial growth; First siliceous electric conducting material 4 is again the monocrystalline silicon formed from the second siliceous electric conducting material 6 epitaxial growth.Therefore the first siliceous electric conducting material 4 and the second siliceous electric conducting material 6 can have the very good monocrystalline silicon of structure.This monocrystalline silicon has good conductive characteristic again, therefore can promote the usefulness of semiconductor structure.

The siliceous electric conducting material of patterning first 4 and the second siliceous electric conducting material 6, to form stacked structure 8 as shown in Figure 2.Please refer to Fig. 2, each of stacked structure 8 comprises the first siliceous electric conducting material 4 and the second siliceous electric conducting material 6 be staggeredly stacked.The method of patterning comprises the first siliceous electric conducting material 4 and the second siliceous electric conducting material 6 utilizing etching process to remove part.In one embodiment, the first siliceous electric conducting material 4 is similar material such as silicon to the second siliceous electric conducting material 6, and therefore etching process is identical to the first siliceous electric conducting material 4 with the etch-rate of the second siliceous electric conducting material 6 haply.Therefore etching process accurately can control the first siliceous electric conducting material 4 and the second siliceous electric conducting material 6 has meticulous profile or high depth-width ratio (aspect ratio) after patterning.For example, the width W of stacked structure 8 is about 20nm.Distance D between two adjoining stacked structures 8 is about 130nm.

The each first siliceous electric conducting material 4 (Fig. 2) of thermal oxidation and the second siliceous electric conducting material 6, insulating oxide structure 16 is all transformed into make the first siliceous electric conducting material 4, second siliceous electric conducting material 6 is transformed into siliceous conductive structure 18 and insulating oxide 20, wherein insulating oxide 20 be positioned at siliceous conductive structure 18 surface on and contact with siliceous conductive structure 18, as shown in Figure 3.Please refer to Fig. 3, insulating oxide structure 16 and insulating oxide 20 have beak profile.For example, thermal-oxidative production process comprises the first siliceous electric conducting material 4 (Fig. 2) and the second siliceous electric conducting material 6 to be placed in oxygenous environment and carries out high-temperature heating, makes oxygen enter from the diffusion into the surface of the first siliceous electric conducting material 4 and the second siliceous electric conducting material 6 and react and produces oxide isolated material such as silica.

In an embodiment, first siliceous electric conducting material 4 (Fig. 2) has different doping conditions from the second siliceous electric conducting material 6, therefore in the thermal oxidation process of the same terms, or in the process of the siliceous electric conducting material of thermal oxidation first simultaneously 4 and the second siliceous electric conducting material 6, the first siliceous electric conducting material 4 can have different oxide-diffused speed from the second siliceous electric conducting material 6.In an embodiment, the first siliceous electric conducting material 4 and the second siliceous electric conducting material 6 have variable concentrations and the doping of same conductivity.For example, first siliceous electric conducting material 4 and the second siliceous electric conducting material 6 all have N-type doping, and the doping concentration of N-type of the first siliceous electric conducting material 4 is greater than the doping concentration of N-type of the second siliceous electric conducting material 6, such as differ 2 grade to 3 grades, therefore the oxide-diffused speed of the first siliceous electric conducting material 4 is greater than the oxide-diffused speed of the second siliceous electric conducting material 6.N-type doping comprises the 5A such as P, As (VA) race element.Or the first siliceous electric conducting material 4 and the second siliceous electric conducting material 6 all have P type doping, and the doping concentration of P type of the first siliceous electric conducting material 4 is different from the doping concentration of P type of the second siliceous electric conducting material 6.P type doping comprises the 3A such as B (IIIA) race element.Parameter such as heating-up temperature, heating time etc. that the oxidation states of the first siliceous electric conducting material 4 and the second siliceous electric conducting material 6 is also oxidized manufacture craft by modulation suitably control.

Remove insulating oxide 20, to form stacked structure 22 as shown in Figure 4.In an embodiment, use to there is the etching process of etching selectivity to remove insulating oxide 20 to insulation oxide (such as silica) and siliceous conducting objects (such as monocrystalline silicon), therefore in the process removing insulating oxide 20, also can remove the insulating oxide structure 16 of part simultaneously, the size of insulating oxide structure 16 is diminished, and siliceous conductive structure 18 can not be damaged haply.Etching process comprises such as dry-etching and Wet-type etching.

Fig. 5 illustrates the semiconductor device of an embodiment.Please refer to Fig. 5, in an embodiment, form dielectric element 124 on the stacked structure 122 that the stacked structure 22 to Fig. 4 is similar, and conductor wire 126 is formed on dielectric element 124, to form three-dimensional perpendicular gate memory devices (3D vertical gate memorydevice), such as, comprise anti-and grid (NAND) type flash body or antifuse memory bank etc.For example, in stacked structure 22 the siliceous conductive structure 118 of different levels respectively as the bit line (BL) of different memory plane.Conductor wire 126 comprises such as polysilicon.Conductor wire 126 can be used as wordline (WL), ground connection selects line (GSL) or tandem selects line (SSL).Dielectric element 124 can have sandwich construction, such as that (its structure can with reference to U. S. application case number 11/419 for ONO composite bed or ONONO composite bed or BE-SONOS composite bed, 977, the patent No. 7414889), or comprise such as dielectric layer 128,130,132.In one embodiment, dielectric layer 128 is silica, and dielectric layer 130 is silicon nitride, and dielectric layer 132 is silica.In other embodiments, dielectric element 124 is simple layer dielectric material (not shown)s, comprises silicon nitride or silica such as silicon dioxide, silicon oxynitride.

Although disclose the present invention in conjunction with above preferred embodiment; but itself and be not used to limit the present invention, any person that is familiar with technique, without departing from the spirit and scope of the present invention; can do a little change and retouching, what therefore protection scope of the present invention should define with the claim of enclosing is as the criterion.

Claims

1. a manufacture method for semiconductor structure, comprising:

A substrate forms one first siliceous electric conducting material;

This first siliceous electric conducting material forms one second siliceous electric conducting material, and wherein this first siliceous electric conducting material and this second siliceous electric conducting material have variable concentrations and the doping of same conductivity;

This first siliceous electric conducting material of etching part and this second siliceous electric conducting material, with this first siliceous electric conducting material of patterning and this second siliceous electric conducting material; And

This first siliceous electric conducting material of thermal oxidation and this second siliceous electric conducting material, an insulating oxide structure is all transformed into make this first siliceous electric conducting material, this second siliceous electric conducting material is transformed into a siliceous conductive structure and an insulating oxide, and wherein this insulating oxide structure and this insulating oxide all have beak profile.

2. the manufacture method of semiconductor structure as claimed in claim 1, wherein this first siliceous electric conducting material and this second siliceous electric conducting material thermal oxidation simultaneously.

3. the manufacture method of semiconductor structure as claimed in claim 1, wherein in the process of thermal oxidation, the oxide-diffused speed of this first siliceous electric conducting material is greater than the oxide-diffused speed of this second siliceous electric conducting material.

4. the manufacture method of semiconductor structure as claimed in claim 1, wherein this substrate is monocrystalline silicon, and this first siliceous electric conducting material is the monocrystalline silicon formed from this substrate epitaxial growth.

5. the manufacture method of semiconductor structure as claimed in claim 1, wherein this first siliceous electric conducting material and this second siliceous electric conducting material are all silicon.

6. the manufacture method of semiconductor structure as claimed in claim 1, wherein form most these first siliceous electric conducting materials and majority this second siliceous electric conducting material, those second siliceous electric conducting materials are separated from each other by those first siliceous electric conducting materials.

7. a semiconductor structure, comprising:

Substrate;

Insulating oxide structure, is formed in this substrate; And

Siliceous conductive structure and an insulating oxide, be formed in this insulating oxide structure, wherein this insulating oxide be positioned at this siliceous conductive structure surface on and contact with this siliceous conductive structure, this insulating oxide structure and this insulating oxide all have beak profile.