CN105280590B - Semiconductor structure and its manufacturing method - Google Patents
Semiconductor structure and its manufacturing method Download PDFInfo
- Publication number
- CN105280590B CN105280590B CN201410332407.4A CN201410332407A CN105280590B CN 105280590 B CN105280590 B CN 105280590B CN 201410332407 A CN201410332407 A CN 201410332407A CN 105280590 B CN105280590 B CN 105280590B
- Authority
- CN
- China
- Prior art keywords
- conductive
- hole
- stripe
- semiconductor structure
- conductive material
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Landscapes
- Semiconductor Memories (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
The invention discloses a kind of semiconductor structure and its manufacturing methods.Semiconductor structure includes a conductive layer, a conductive stripe, a dielectric layer and a conducting element.Conductive layer has one first conductive material.Conductive stripe and conductive layer are located at identical stratum, and have one second conductive material.Second conductive material is the first different conductive material of adjacent conduction property.Conducting element is interconnected with conductive stripe, and is divided in conductive stripe by dielectric layer.
Description
Technical field
The invention relates to a kind of semiconductor structure and its manufacturing methods, and in particular to a kind of memory and its
Manufacturing method.
Background technique
The structure of semiconductor element is constantly changing in recent years, and the memory storage capacity of element is also continuously increased.It deposits
Storage device is to be used in many products, such as in the storage element of MP3 player, digital camera, computer archives etc..
With the increase of application, lesser size, biggish memory capacity are also tended to for the demand of storage device.In response to this need
It asks, is to need to manufacture high component density and the storage device with small size.
Therefore, designers are dedicated to developing a kind of three-dimensional memory devices invariably, not only have many lamination planes and reach
To higher memory storage capacity, there is more small size, be provided simultaneously with good characteristic and stability.
Summary of the invention
According to an embodiment, a kind of semiconductor structure is disclosed comprising a conductive layer, a conductive stripe, a dielectric layer, with
One conducting element.Conductive layer has one first conductive material.Conductive stripe and conductive layer are located at identical stratum, and with one the
Two conductive materials.Second conductive material is the first different conductive material of adjacent conduction property.Conducting element and conductive stripe are handed over
Mispairing is set, and is divided in conductive stripe by dielectric layer.
According to another embodiment, a kind of manufacturing method of semiconductor structure is disclosed comprising following steps.In a lamination knot
A first through hole is formed in structure, to expose the conductive film that laminated construction has one first conductive material.Formed a dielectric layer in
In first through hole.First through hole is filled with a conductive plunger.It is formed in laminated construction and exposes the one the of dielectric layer and conductive film
Two through-holes.The partially electronically conductive film of the second through-hole exposing is removed, to be formed by the outwardly extending hole of the second through-hole.With one second
Conductive material filling pore.The second through-hole is filled with a dielectric plugs.
Detailed description of the invention
Figure 1A to Fig. 9 is painted the manufacturing method of semiconductor structure according to the embodiment.
[symbol description]
102: laminated construction
104: conductive film
106: dielectric film
108: memory array region
110: first through hole
112: dielectric layer
114: conductive plunger
116: upper surface
118: side wall
120: bottom surface
122: mask layer
124: opening
126: the second through-holes
128: side wall
130: side wall
132: conductive stripe profile
134: hole
136: connection pad area
138: conductive layer
140: conductive stripe
142: dielectric plugs
144: being conductively connected
146: conducting element
148: side wall
150: side wall
152: opening
Specific embodiment
Figure 1A to Fig. 9 is painted the manufacturing method of semiconductor structure according to the embodiment.
The top view and sectional view of Figure 1A and Figure 1B are please referred to, laminated construction 102 is stacked in substrate including interaction and (does not draw
Show) on conductive film 104 and dielectric film 106.Wherein for the sake of clarity, the diagram that the present invention is denoted as " A " is only painted conductive film 104
The wherein structure in a stratum.Substrate may include Silicon Wafer, the epitaxial layer being formed on silicon materials or cover on doped layer, insulating layer
The suitable semiconductor materials such as silicon (SOI).Conductive film 104 is formed with the first conductive material.Dielectric film 106 is with oxide shape
At.
A and Fig. 2 B referring to figure 2., performs etching step using photoetching technique, the lamination knot in memory array region 108
The middle formation first through hole 110 (being wherein denoted as the structure being illustrated as near first through hole 110 of " B ") of structure 102.It can be according to quarter
Erosion time control first through hole 110 stops on the dielectric film 106 of the bottom.
A and Fig. 3 B referring to figure 3. forms conductive film 104 and dielectric film 106 that dielectric layer 112 exposes in first through hole 110
On.With conductive material filling first through hole 110 to form conductive plunger 114.In some embodiments, using chemical mechanical grinding
(CMP) the conductive material (not shown) being formed on the upper surface 116 of laminated construction 102 is removed.As shown in Figure 3B, dielectric layer
112 are located on the side wall 118 and bottom surface 120 of conductive plunger 114.Dielectric layer 112 can be ONO structure, ONONO structure,
ONONONO structure or by tunneling material (tunneling material)/capture material (trapping material)/blocking
The multilayered structure that material (blocking material) is constituted is applied to the storage material of NAND gate (NAND).Wherein, from interior
The oxide (O1N1O2) of several first layer oxides and nitride and the second layer is tunneling material, second layer nitridation outward
Object (N2) is capture material, third layer oxide (O3) or third layer oxide/nitride or the 4th layer of oxide (O3/N3/
It O4) is barrier material.
A to Fig. 4 C referring to figure 4. forms patterned mask layer 122 (for the sake of clarity, being not depicted in Fig. 4 A) in lamination knot
On structure 102, and the pattern openings 124 that mask layer 122 is located at memory array region 108 are transferred to downwards in laminated construction 102,
To form the second through-hole 126 (being wherein denoted as the structure being illustrated as near the second through-hole 126 of " C ").Mask layer 122 may include
Photoresist or other suitable materials, such as silicon nitride, perform etching step using photoetching technique and are patterned.
A referring to figure 4., the second through-hole 126 of formation abuts between first through hole 110 in z-direction, and at least exposes
Dielectric layer 112 in first through hole 110.In some embodiments, the second through-hole 126 can more expose the conduction in first through hole 110
Plug 114.So far step, it is fixed between 128,130 groups of side wall that first through hole 110 and the second through-hole 126 are connected in z-direction
Justice goes out the conductive stripe profile 132 extended toward Z-direction.
A to Fig. 5 C referring to figure 5. removes what conductive film 104 was exposed in memory array region 108 by the second through-hole 126
Part is extended outwardly and from the side wall 130 (that is, side wall 130 of dielectric film 106) of the second through-hole 126 between dielectric with being formed
Hole 134 between film 106；And the conductive film 104 in the connection pad area 136 not overlapped with memory array region 108 is left, with
Form conductive layer 138.It is that conductive film 104 is removed by an etch step, this etching step is for conductive film 104 in embodiment
The etch rate of (or first conductive material) is higher than for dielectric layer 112, conductive plunger 114, dielectric film 106 and/or mask layer
122 etch rate, or do not remove dielectric layer 112, conductive plunger 114, dielectric film 106 and/or mask layer 122 substantially.It carves
It can be equal to etching technics, including wet etching or dry etching method etc. for losing step.It for example, is more in the first conductive material
In the example of crystal silicon, removing method may include CF4/O2/N2The dry etching of mixed gas, or use tetramethyl ammonium hydroxide
(tetramethylammonium hydroxide；) or the wet etching of hot ammonium hydroxide (hot ammonia) TMAH.Hole 134
External periphery outline is not limited to rectangle as shown in the figure, and can become other profiles according to etching situation, such as annular or does not advise
Shape etc. then.
In some embodiments, although hole 134 is that large area is formed, due in first through hole 110 dielectric layer 112 with
Conductive plunger 114 can support the dielectric film 106 of the upper and lower side of hole 134 to be separated from each other, and other the not formed holes of laminated construction 102
The region (such as connection pad area 136) of gap 134 also provides the effect of support, thus in memory array region 108 different estate Jie
Electrolemma 106 can maintain desired disconnected position, that is, hole 134 can have desired spatial shape.
Fig. 6 A to Fig. 6 C is please referred to, with the second conductive material filling pore 134, is extended with formation toward Z axis and separated from each other
Conductive stripe 140.In embodiment, the conductive stripe 140 of different estate is formed simultaneously using identical depositing operation, therefore
With substantially uniform material properties.In some embodiments, annealing process, such as laser annealing technique can be also carried out, to mention
Rise the property of the second conductive material.
As shown in Figure 6A, the second conductive material being filled in hole 134 be adjacent conductive film 104 leave part (or
Conductive layer 138), therefore the conductive stripe 140 in memory array region 108 is electrically connected to the conductive layer in connection pad area 136
138.Each conduction stratum includes conductive layer 138 and conductive stripe 140.In some embodiments, also using mask layer 122 carry out etc. to
Property etching technics exposes be deposited in the second through-hole 126 or on the side wall 130 of dielectric film 106 to remove mask layer 122
Two conductive material (not shown)s are shorted each other to avoid the second conductive material being filled in different estate hole 134.
Fig. 7 A to Fig. 7 C is please referred to, the second through-hole 126 is filled using dielectric material, to form dielectric plugs 142.Such as Fig. 7 A
Shown, conductive stripe 140 is to be defined by adjacent dielectric layer 112 with dielectric plugs 142.In one embodiment, dielectric plugs
142 be oxide.
Fig. 8 A to Fig. 8 C is please referred to, chemical mechanical grinding can be carried out, by Jie of 116 top of upper surface of laminated construction 102
Electric material (not shown) is removed with mask layer 122 (Fig. 7 B and Fig. 7 C).In other embodiments, mask layer 122 can also retain,
Or it is removed in other suitable steps.
Fig. 8 A and Fig. 8 B are please referred to, is formed toward X-direction extension and conductive connection 144 separated from each other is in conductive plunger 114
On, and across the conductive stripe 140 between conductive plunger 114.Adjacent conductive connection 144 is led with the composition of conductive plunger 114
Electric device 146, it is interconnected with conductive stripe 140, and conductive stripe 140 is divided in by dielectric layer 112.It is conductively connected
144 can be formed with conductive plunger 114 with third conductive material.The forming method for being conductively connected 144 may include that deposition third is conductive
Then material performs etching step using photoetching technique to pattern third conductive material and is formed on laminated construction 102.
The semiconductor structure of embodiment is three-dimensional perpendicular grid nand flash memory lamination, wherein in memory array region 108, toward Z
The conductive stripe 140 that direction extends is used as bit line, and the conducting element 146 extended toward X-direction is used as wordline.
In some comparative examples, the formation of bit line is the laminated construction by pattern conductive film and dielectric film, disposably
Landform growth strip opening and define.In other words, the feelings that whole face side wall exposes opening can occur in bit line forming process
Condition.However, include bit line high-aspect-ratio (aspect ratio) striped lamination, two sides be all opening and not by other
In the case that element supports, be easy by other stress (such as in immersion liquid cleaning step, full of liquid in the opening, or leaching,
Pull stress caused by making) it influences and bends (bending), so that structural damage even forms undesirable short circuit,
Reduce product yield.
In an embodiment of the present invention, the profile of each stratum's conductive stripe 140 is the through-hole (packet formed using different step
Include first through hole 110 and the second through-hole 126) define, in the process the second conductive material to form conductive stripe 140 be by
To support.For example, in the step described in Fig. 6 A to Fig. 6 C, the second conductive material being filled in hole 134, be by
Dielectric film 106 is supported with the dielectric layer 112 in first through hole 110 with conductive plunger 114.Therefore, compared to comparative example, implement
Example has more stable structure feature, it is not easy to the problem of deformation occurs, and product reliability is high.
In order in response to the demand in device electrical property, first for conductive layer 138 (or conductive film 104 leave part) is led
Electric material, the second conductive material of conductive stripe 140 can have different conductions from the third conductive material of conducting element 146
Property.In some designs, lifting the conductive layer 138 in region (pick-up region) its resistance as bit line should be less than being generally
The resistance of the bit line of closed state (normally off), therefore the resistance of the first conductive material need to be less than the second conductive material.
In one embodiment, the first conductive material is the material of doping, such as the N-type polycrystalline silicon (N+poly) of heavy doping.Second leads
Electric material is undoped material or essential silicon materials (intrinsic silicon), such as undoped polysilicon.The
Three conductive materials are the P-type silicon germanium (P+SiGe) of heavy doping.
Conducting element 146 (wordline) is located at the conductive plunger 114 in the opposing sidewalls 148,150 of conductive stripe 140, is
Filling first through hole 110 is formed self-aligned (as described in the content referring to Fig. 3 A and Fig. 3 B), therefore can have accurate expection
Structure, to improve product yield.
In referring to as described in the content of Fig. 6 A to Fig. 6 C, the second conductive material system of different estate utilizes identical deposition work
Skill is formed simultaneously, therefore the conductive stripe 140 formed has substantially uniform material properties, so that each storage unit in array
Bit line channel can have substantially the same electrical property, whereby improve device efficiency.
It please refers to Fig. 9, in other embodiments, forms the opening of different depth in the laminated construction 102 in connection pad area 136
152, to expose the conductive layer 138 of different estate respectively.
Other techniques not shown can be also carried out later.Such as with dielectric medium (not shown) filling opening 152, and it is being situated between
It is electrically connected in electric matter to the contact plunger of conductive layer 138.And it is electrically connected above laminated construction 102 to contact
Other of plug or wordline conductive member, such as conductive contact or metal layer such as M1, M2 etc..It, also can be in some embodiments
Intert the forming step of other elements between above-mentioned steps, or suitably changes the sequence of step.
The present invention is not limited to embodiments described above, also can according to actual needs or other design is suitably adjusted
Become.In another embodiment, for example, the first conductive material of conductive layer 138 is the N-type SiGe (N+ using heavy doping
SiGe), the second conductive material of conductive stripe 140 is using essence or undoped SiGe, and the third of conducting element 146 is led
Electric material is the p-type polysilicon using heavy doping.Wherein the first conduction material of SiGe (SiGe) in removing memory array region 108
It, can be for example using pure CF in the step of material4Gas is etched as the chemical plasma of etching gas；It is etched using HCl；Or make
Use HF/HNO3/CH3The wet etching of COOH etching agent.Conductive material also may include metal, such as TiN, Ti, TaN, Ta, Au, W
Deng or suitable metal silicide.Dielectric medium for dielectric film, dielectric layer, dielectric plugs or other insulation components can be distinguished
Including oxide, nitride, nitrogen oxides, such as silica, silicon nitride, silicon oxynitride or other suitable dielectric materials, and
Can have simple layer structure or multilayered structure.Dielectric material or conductive material can be formed in an appropriate manner, including physical vapor
Deposition, chemical vapor deposition etc..Etching or removing step may include wet etching or dry etching etc..
Although however, it is not to limit the invention in conclusion the present invention is disclosed as above with embodiment.Institute of the present invention
Belong in technical field and have usually intellectual, without departing from the spirit and scope of the present invention, when various change and profit can be made
Decorations.Therefore, subject to protection scope of the present invention ought be defined depending on appended claims range.
Claims (9)
1. a kind of semiconductor structure, comprising:
One conductive layer has one first conductive material；
One conductive stripe is located at identical stratum with the conductive layer, and has one second conductive material, wherein second conduction material
Material is to be adjacent to first conductive material, which has different conduction properties from second conductive material；
One dielectric layer；
One conducting element, interconnected with the conductive stripe, wherein the conducting element is by the dielectric layer and the conductive stripe
It separates；And
The memory array region and a connection pad area not overlapped, wherein the conductive stripe is located in the memory array region, should
Conductive layer is located in the connection pad area；
Wherein, which formed by second conductive material being filled in hole, is filled in being somebody's turn to do in hole
Second conductive material is that the dielectric layer and conductive plunger in dielectric film and first through hole by the upper and lower side of hole are supported, and
The dielectric layer is located on the side wall of the conductive plunger.
2. semiconductor structure according to claim 1, the lamination including more conductive stratum, wherein these conductive stratum respectively wrap
The conductive layer and the conductive stripe are included, these conductive layers of different estate are to expose respectively through the opening of different depth.
3. semiconductor structure according to claim 1, wherein the conducting element includes the conductive plunger, which is located at
In the one side wall of the conductive plunger and a bottom surface.
4. semiconductor structure according to claim 1, wherein the conducting element have be different from first conductive material with
One third conductive material of second conductive material.
5. semiconductor structure according to claim 1, wherein the conducting element includes adjacent conductive plunger and one
It is conductively connected, which is located in the two lateral walls of the conductive stripe, which is located at the upper of the conductive stripe
Surface.
6. semiconductor structure according to claim 1 further includes a dielectric plugs, wherein the conductive stripe is by adjacent
The dielectric layer defined with the dielectric plugs.
7. a kind of manufacturing method of semiconductor structure, comprising:
A first through hole is formed in a laminated construction, it is conductive to expose the laminated construction one with one first conductive material
Film；
A dielectric layer is formed in the first through hole；
The first through hole is filled with a conductive plunger；
One second through-hole for exposing the dielectric layer and the conductive film is formed in the laminated construction；
Part conductive film of second through-hole exposing is removed, to be formed by the outwardly extending hole of second through-hole；
The hole is filled with one second conductive material；And
Second through-hole is filled with a dielectric plugs.
8. the manufacturing method of semiconductor structure according to claim 7, wherein second through-hole be expose the conductive film with
The dielectric layer and the conductive plunger in the first through hole, the partially electronically conductive film which exposes are by an etching step
Suddenly it is removed, which is higher than the etch rate of the conductive film etching for the dielectric layer and the conductive plunger
Rate.
9. the manufacturing method of semiconductor structure according to claim 7, further include to form a conductive connection and insert in the conduction
Beyond the Great Wall, wherein second conductive material being filled in the hole is to form a conductive stripe, the profile of the conductive stripe is logical
It crosses the first through hole and the side wall of second through-hole defines.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410332407.4A CN105280590B (en) | 2014-07-14 | 2014-07-14 | Semiconductor structure and its manufacturing method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410332407.4A CN105280590B (en) | 2014-07-14 | 2014-07-14 | Semiconductor structure and its manufacturing method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN105280590A CN105280590A (en) | 2016-01-27 |
| CN105280590B true CN105280590B (en) | 2019-06-14 |
Family
ID=55149362
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201410332407.4A Active CN105280590B (en) | 2014-07-14 | 2014-07-14 | Semiconductor structure and its manufacturing method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN105280590B (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107731846B (en) | 2017-08-31 | 2019-01-01 | 长江存储科技有限责任公司 | Improve the three-dimensional storage forming method of channel through-hole homogeneity |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101826545A (en) * | 2009-03-03 | 2010-09-08 | 旺宏电子股份有限公司 | Integrated circuit self aligned 3d memory array and manufacturing method |
| CN103633108A (en) * | 2012-08-23 | 2014-03-12 | 爱思开海力士有限公司 | 3-dimensional stack memory device |
Family Cites Families (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW548860B (en) * | 2001-06-20 | 2003-08-21 | Semiconductor Energy Lab | Light emitting device and method of manufacturing the same |
| JP5091491B2 (en) * | 2007-01-23 | 2012-12-05 | 株式会社東芝 | Nonvolatile semiconductor memory device |
| US7781825B2 (en) * | 2007-10-18 | 2010-08-24 | Macronix International Co., Ltd. | Semiconductor device and method for manufacturing the same |
| US7981742B2 (en) * | 2008-07-02 | 2011-07-19 | Macronic International Co., Ltd. | Semiconductor device, data element thereof and method of fabricating the same |
| US8541831B2 (en) * | 2008-12-03 | 2013-09-24 | Samsung Electronics Co., Ltd. | Nonvolatile memory device and method for fabricating the same |
| KR101186038B1 (en) * | 2010-11-26 | 2012-09-26 | 에스케이하이닉스 주식회사 | Method of fabricating semiconductor device |
| KR101169176B1 (en) * | 2010-12-15 | 2012-07-30 | 에스케이하이닉스 주식회사 | Semiconductor device and method for manufacturing the same |
-
2014
- 2014-07-14 CN CN201410332407.4A patent/CN105280590B/en active Active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101826545A (en) * | 2009-03-03 | 2010-09-08 | 旺宏电子股份有限公司 | Integrated circuit self aligned 3d memory array and manufacturing method |
| CN103633108A (en) * | 2012-08-23 | 2014-03-12 | 爱思开海力士有限公司 | 3-dimensional stack memory device |
Also Published As
| Publication number | Publication date |
|---|---|
| CN105280590A (en) | 2016-01-27 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| TWI478310B (en) | Fin anti-fuse with reduced programming voltage | |
| TWI520275B (en) | Memory device and method of manufacturing the same | |
| CN106876397A (en) | Three-dimensional storage and forming method thereof | |
| CN108269805B (en) | Semiconductor memory device and method of manufacturing the same | |
| US10439048B2 (en) | Photomask layout, methods of forming fine patterns and method of manufacturing semiconductor devices | |
| CN103367317A (en) | Semiconductor device, method for fabricating the same and system comprising the same | |
| US10269823B2 (en) | Flash memory semiconductor device | |
| TWI582841B (en) | Method for fabricating transistor gate and semiconductor device comprising transistor gate | |
| US9455155B2 (en) | Semiconductor structure and manufacturing method for the same | |
| TW202018953A (en) | Finfet having insulating layers between gate and source/drain contacts | |
| US9530786B2 (en) | Memory device and method for fabricating the same | |
| KR20150007520A (en) | Phase-change random access memory device and method of manufacturing the same | |
| TWI575714B (en) | Three-dimensional memory | |
| US9508732B2 (en) | Semiconductor devices including a gate electrode and methods of manufacturing the same | |
| US9337208B2 (en) | Semiconductor memory array with air gaps between adjacent gate structures and method of manufacturing the same | |
| US9142454B1 (en) | Semiconductor structure and method for manufacturing the same | |
| CN104051331A (en) | Damascene conductor for 3D array | |
| TWI793433B (en) | Staircase structure in three-dimensional memory device and method for forming the same | |
| CN108122840B (en) | Semiconductor device, preparation method and electronic device | |
| CN103456787B (en) | Transistor unit and manufacture method thereof | |
| CN105097516B (en) | A kind of FinFET and its manufacturing method, electronic device | |
| CN105280590B (en) | Semiconductor structure and its manufacturing method | |
| CN108735711A (en) | A kind of semiconductor devices and preparation method thereof, electronic device | |
| TW201624622A (en) | Non-volatile memory cell, NAND-type non-volatile memory and method of manufacturing thereof | |
| KR20110128468A (en) | Methods of forming a pattern, methods of forming a gate structure and methods of manufacturing a semiconductor device using the same |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |