CN105280590A - Semiconductor structure and manufacturing method thereof - Google Patents
Semiconductor structure and manufacturing method thereof Download PDFInfo
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- CN105280590A CN105280590A CN201410332407.4A CN201410332407A CN105280590A CN 105280590 A CN105280590 A CN 105280590A CN 201410332407 A CN201410332407 A CN 201410332407A CN 105280590 A CN105280590 A CN 105280590A
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- conductive
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Abstract
The invention discloses a semiconductor structure and a manufacturing method thereof. The semiconductor structure comprises a first conductive layer, a conductive strip, a dielectric layer and a conductive element. The conductive layer is provided with a first conductive material. The conductive strip and the conductive layer are positioned on the same layer, and the conductive strip is provided with a second conductive material. The second conductive material is adjacent to the first conductive material and has conductive properties different from the first conductive material. The conductive element intersects with the conductive strip, and also is separated from the conductive strip through the dielectric layer.
Description
Technical field
The invention relates to a kind of semiconductor structure and manufacture method thereof, and relate to a kind of memory and manufacture method thereof especially.
Background technology
The structure of semiconductor element constantly changes in recent years, and the memory storage capacity of element also constantly increases.Storage device is used in many products, such as, in the storage unit of MP3 player, digital camera, computer archives etc.Along with the increase of application, the demand for storage device also tends to less size, larger memory capacity.In response to this demand, be need manufacture high component density and there is undersized storage device.
Therefore, designers are devoted to develop a kind of three-dimensional memory devices invariably, not only have many lamination planes and reach higher memory storage capacity, having more small size, possess good characteristic and stability simultaneously.
Summary of the invention
According to an embodiment, a kind of semiconductor structure is disclosed, it comprise a conductive layer, a conductive stripe, a dielectric layer, with a conducting element.Conductive layer has one first electric conducting material.Conductive stripe and conductive layer are positioned at identical stratum, and have one second electric conducting material.Second electric conducting material is different the first electric conducting material of adjacent conduction property.Conducting element and conductive stripe interconnected, and be divided in conductive stripe by dielectric layer.
According to another embodiment, disclose a kind of manufacture method of semiconductor structure, it comprises the following steps.One first through hole is formed, to expose the conducting film that laminated construction has one first electric conducting material in a laminated construction.Form a dielectric layer in the first through hole.The first through hole is filled with a conductive plunger.One second through hole exposing dielectric layer and conducting film is formed in laminated construction.Remove the partially conductive film that the second through hole exposes, to be formed by the outward extending hole of the second through hole.With one second filled with conductive material hole.The second through hole is filled with a dielectric plugs.
Accompanying drawing explanation
Figure 1A to Fig. 9 illustrates the manufacture method of the semiconductor structure according to embodiment.
[symbol description]
102: laminated construction
104: conducting film
106: dielectric film
108: memory array region
110: the first through holes
112: dielectric layer
114: conductive plunger
116: upper surface
118: sidewall
120: basal surface
122: mask layer
124: opening
126: the second through holes
128: sidewall
130: sidewall
132: conductive stripe profile
134: hole
136: connection pad district
138: conductive layer
140: conductive stripe
142: dielectric plugs
144: conduction connects
146: conducting element
148: sidewall
150: sidewall
152: opening
Embodiment
Figure 1A to Fig. 9 illustrates the manufacture method of the semiconductor structure according to embodiment.
Please refer to top view and the profile of Figure 1A and Figure 1B, laminated construction 102 comprises and is stacked in conducting film in substrate (not illustrating) 104 and dielectric film 106 alternately.Wherein for the sake of clarity, the diagram that the present invention is denoted as " A " only illustrates the structure of conducting film 104 wherein in a stratum.Substrate can comprise Silicon Wafer, be formed in epitaxial loayer on silicon materials or the suitable semi-conducting material such as doped layer, silicon-on-insulator (SOI).Conducting film 104 is formed with the first electric conducting material.Dielectric film 106 is formed with oxide.
Please refer to Fig. 2 A and Fig. 2 B, photoetching technique can be utilized to carry out etch step, in the laminated construction 102 of memory array region 108, form the first through hole 110 (being wherein denoted as the structure be illustrated as near the first through hole 110 of " B ").The first through hole 110 can be controlled according to etch period to stop on the dielectric film 106 of the bottom.
Please refer to Fig. 3 A and Fig. 3 B, form conducting film 104 that dielectric layer 112 exposes in the first through hole 110 with on dielectric film 106.With filled with conductive material first through hole 110 to form conductive plunger 114.In some embodiments, cmp (CMP) can be utilized to remove the electric conducting material (not shown) be formed on the upper surface 116 of laminated construction 102.As shown in Figure 3 B, dielectric layer 112 is positioned at the sidewall 118 of conductive plunger 114 with on basal surface 120.Dielectric layer 112 can be ONO structure, ONONO structure, ONONONO structure or the sandwich construction that is made up of tunneling material (tunnelingmaterial)/capture material (trappingmaterial)/barrier material (blockingmaterial), is applied to the storage material of NAND gate (NAND).Wherein, be tunneling material from the interior ground floor oxide that counts outward and the oxide (O1N1O2) of nitride and the second layer, second layer nitride (N2) is capture material, and third layer oxide (O3) or third layer oxide/nitride or the 4th layer of oxide (O3/N3/O4) are barrier material.
Please refer to Fig. 4 A to Fig. 4 C, form the mask layer 122 of patterning (for the sake of clarity, be not shown in Fig. 4 A) on laminated construction 102, and the pattern openings 124 mask layer 122 being arranged in memory array region 108 is transferred to laminated construction 102 downwards, to form the second through hole 126 (being wherein denoted as the structure be illustrated as near the second through hole 126 of " C ").Mask layer 122 can comprise photoresist or other suitable material, such as silicon nitride, and it can utilize photoetching technique to carry out etch step to carry out patterning.
Please refer to Fig. 4 A, between adjacent first through hole 110 in z-direction of the second through hole 126 of formation, and at least expose the dielectric layer 112 in the first through hole 110.In some embodiments, the second through hole 126 more can expose the conductive plunger 114 in the first through hole 110.So far step, defines the conductive stripe profile 132 extended toward Z-direction between the sidewall that the first through hole 110 and the second through hole 126 are connected in z-direction 128,130 groups.
Please refer to Fig. 5 A to Fig. 5 C, remove conducting film 104 by the part that the second through hole 126 exposes in memory array region 108, stretch out and hole 134 between dielectric film 106 from the sidewall 130 (that is sidewall 130 of dielectric film 106) of the second through hole 126 to be formed; And stay and the conducting film 104 in the connection pad district 136 of memory array region 108 non-overlapping copies, to form conductive layer 138.In embodiment, remove conducting film 104 by an etch step, this etch step higher than the etch rate for dielectric layer 112, conductive plunger 114, dielectric film 106 and/or mask layer 122, or does not remove in fact dielectric layer 112, conductive plunger 114, dielectric film 106 and/or mask layer 122 for the etch rate of conducting film 104 (or first electric conducting material).Etch step to can be etc. to etching technics, comprises wet etching or dry etching method etc.For example, at the first electric conducting material be polysilicon example in the middle of, removing method can comprise CF
4/ O
2/ N
2the dry etching of mist, or use tetramethyl ammonium hydroxide (tetramethylammoniumhydroxide; Or the wet etching of hot ammoniacal liquor (hotammonia) TMAH).The external periphery outline of hole 134 is not limited to rectangle as shown in the figure, and can become other profiles according to etching situation, such as annular or irregular shape etc.
In some embodiments, formed although hole 134 is large area, but because with conductive plunger 114, the dielectric layer 112 in the first through hole 110 can support that the dielectric film 106 of the upper and lower side of hole 134 is separated from each other, and the effect that other regions (such as connection pad district 136) not forming hole 134 of laminated construction 102 also provide support, therefore in memory array region 108, the dielectric film 106 of different estate can maintain the disconnected position expected, that is hole 134 can have the spatial shape of expectation.
Please refer to Fig. 6 A to Fig. 6 C, with the second filled with conductive material hole 134, extend and conductive stripe 140 separated from each other toward Z axis to be formed.In embodiment, simultaneously the conductive stripe 140 of different estate utilizes identical depositing operation to be formed, and therefore has material character homogeneous in fact.In some embodiments, also annealing process can be carried out, such as laser annealing technique, to promote the character of the second electric conducting material.
As shown in Figure 6A, the second electric conducting material be filled in hole 134 is the part (or conductive layer 138) that adjacent conducting film 104 stays, and the conductive stripe 140 therefore in memory array region 108 is electrically connected to the conductive layer 138 in connection pad district 136.Each conduction stratum comprises conductive layer 138 and conductive stripe 140.In some embodiments, mask layer 122 is also utilized to carry out etching technics such as tropism such as grade, with remove mask layer 122 expose the second electric conducting material (not shown) be deposited in the second through hole 126 or on the sidewall 130 of dielectric film 106, to avoid the second electric conducting material short circuit be each other filled in different estate hole 134.
Please refer to Fig. 7 A to Fig. 7 C, utilize dielectric material to fill the second through hole 126, to form dielectric plugs 142.As shown in Figure 7 A, conductive stripe 140 is defined with dielectric plugs 142 by adjacent dielectric layer 112.In one embodiment, dielectric plugs 142 is oxide.
Please refer to Fig. 8 A to Fig. 8 C, can cmp be carried out, the dielectric material (not shown) above the upper surface 116 of laminated construction 102 and mask layer 122 (Fig. 7 B and Fig. 7 C) are removed.In other embodiments, mask layer 122 also can retain, or removes in other suitable steps.
Please refer to Fig. 8 A and Fig. 8 B, formation is toward X-direction extension and conduction separated from each other connects 144 on conductive plunger 114, and strides across the conductive stripe 140 between conductive plunger 114.Adjacent conduction connects 144 and forms conducting element 146 with conductive plunger 114, and itself and conductive stripe 140 are interconnected, and are divided in conductive stripe 140 by dielectric layer 112.Conduction connection 144 can be formed by the 3rd electric conducting material with conductive plunger 114.The formation method of conduction connection 144 can comprise deposition the 3rd electric conducting material on laminated construction 102, then utilizes photoetching technique to carry out etch step and is formed with patterning the 3rd electric conducting material.
The semiconductor structure of embodiment is three-dimensional perpendicular grid nand flash memory lamination, and wherein in memory array region 108, the conductive stripe 140 extended toward Z-direction is used as bit line, and the conducting element 146 extended toward X-direction is used as wordline.
In some comparative examples, the formation of bit line is the laminated construction by pattern conductive film and dielectric film, forms the opening of strip once and defines.In other words, the situation that whole sidewall exposes opening can be there is in bit line forming process.But, comprise the striped lamination of the high-aspect-ratio (aspectratio) of bit line, it is when both sides are all opening and do not support by other elements, easily be subject to other stress (in such as immersion liquid cleaning step, be full of liquid in the opening, or leaching, pull the stress caused in work) impact and bend (bending), make structural damage even form less desirable short circuit, reduce product yield.
In an embodiment of the present invention, the profile of each stratum conductive stripe 140 is that the through hole (comprising the first through hole 110 and the second through hole 126) utilizing different step to be formed defines, and the second electric conducting material in order to form conductive stripe 140 in process is supported.For example, in step described in Fig. 6 A to Fig. 6 C, be filled in the second electric conducting material in hole 134, it is that the dielectric layer 112 be subject in dielectric film 106 and the first through hole 110 supported with conductive plunger 114.Therefore, compared to comparative example, embodiment has comparatively stable structure feature, the problem of deformation is less likely to occur, and product reliability is high.
In order in response to device electrically on demand, for the first electric conducting material of conductive layer 138 (or conducting film 104 stay part), conductive stripe 140 the second electric conducting material, different conduction properties can be had from the 3rd electric conducting material of conducting element 146.In some designs, its resistance of conductive layer 138 lifting region (pick-upregion) as bit line should be less than the resistance of the bit line being generally closed condition (normallyoff), and therefore the resistance of the first electric conducting material need be less than the second electric conducting material.In one embodiment, the first electric conducting material is the material of doping, such as heavily doped N-type polycrystalline silicon (N+poly).Second electric conducting material is unadulterated material or essential silicon materials (intrinsicsilicon), such as unadulterated polysilicon.3rd electric conducting material is heavily doped P-type silicon germanium (P+SiGe).
Conducting element 146 (wordline) is positioned at the conductive plunger 114 in the opposing sidewalls 148,150 of conductive stripe 140, it is that filling first through hole 110 is formed self-aligned (as described in the content with reference to Fig. 3 A and Fig. 3 B), therefore accurate expected structure can be had, to improve product yield.
As described in the content with reference to Fig. 6 A to Fig. 6 C, second electric conducting material system of different estate utilizes identical depositing operation to be formed simultaneously, therefore the conductive stripe 140 formed has material character homogeneous in fact, the bit line passage capable of being of each memory cell in array is had identical in fact electrical, improve the usefulness of device by this.
Please refer to Fig. 9, in other embodiments, in the laminated construction 102 in connection pad district 136, form the opening 152 of different depth, to expose the conductive layer 138 of different estate respectively.
Also can carry out other techniques do not shown afterwards.Such as fill opening 152 with dielectric medium (not shown), and in dielectric medium, form the contact plunger being electrically connected to conductive layer 138.And above laminated construction 102, forming other conductive members being electrically connected to contact plunger or wordline, such as conductive contact or metal layer are as M1, M2 etc.In some embodiments, also can intert the forming step of other elements between above-mentioned steps, or suitably change the order of step.
The present invention is not limited to execution mode described above, also can according to the actual requirements or other design suitably modulation.In another embodiment, for example, first electric conducting material of conductive layer 138 uses heavily doped N-type SiGe (N+SiGe), second electric conducting material of conductive stripe 140 uses essence or unadulterated SiGe, and the 3rd electric conducting material of conducting element 146 uses heavily doped P type polysilicon.Wherein in the step removing SiGe (SiGe) first electric conducting material in memory array region 108, can such as use pure CF
4gas etches as the chemical plasma of etching gas; Use HCl etching; Or use HF/HNO
3/ CH
3the wet etching of COOH etching agent.Electric conducting material also can comprise metal, such as TiN, Ti, TaN, Ta, Au, W etc., or suitable metal silicide.Dielectric medium for dielectric film, dielectric layer, dielectric plugs or other insulation components can comprise oxide, nitride, nitrogen oxide respectively, such as silica, silicon nitride, silicon oxynitride or other suitable dielectric materials, and simple layer structure or sandwich construction can be had.Dielectric material or electric conducting material can be formed in an appropriate manner, comprise physical vapour deposition (PVD), chemical vapour deposition (CVD) etc.Etch or remove step and can comprise wet etching or dry etching etc.
In sum, although the present invention is with embodiment openly as above, so itself and be not used to limit the present invention.Persond having ordinary knowledge in the technical field of the present invention, without departing from the spirit and scope of the present invention, when being used for a variety of modifications and variations.Therefore, protection scope of the present invention is when being as the criterion of defining depending on the right of enclosing.
Claims (10)
1. a semiconductor structure, comprising:
One conductive layer, has one first electric conducting material;
One conductive stripe, is positioned at identical stratum with this conductive layer, and has one second electric conducting material, and wherein this second electric conducting material is different this first electric conducting material of adjacent conduction property;
One dielectric layer; And
One conducting element, interconnected with this conductive stripe, and be divided in this conductive stripe by this dielectric layer.
2. semiconductor structure according to claim 1, comprises the lamination of many conduction stratum, and wherein these conduction stratum respectively comprise this conductive layer and this conductive stripe, and these conductive layers of different estate expose through the opening of different depth respectively.
3. semiconductor structure according to claim 1, comprise a memory array region and a connection pad district of non-overlapping copies, wherein this conductive stripe is arranged in this memory array region, and this conductive layer is arranged in this connection pad district.
4. semiconductor structure according to claim 1, wherein this conducting element comprises a conductive plunger, on the sidewall that this dielectric layer is positioned at this conductive plunger and a basal surface.
5. semiconductor structure according to claim 1, wherein this conducting element has one the 3rd electric conducting material being different from this first electric conducting material and this second electric conducting material.
6. semiconductor structure according to claim 1, wherein this conducting element comprises an adjacent conductive plunger and and conducts electricity and be connected, and this conductive plunger is positioned in the two lateral walls of this conductive stripe, this conduction connect be positioned at this conductive stripe upper surface above.
7. semiconductor structure according to claim 1, more comprises a dielectric plugs, and wherein this conductive stripe is defined by this adjacent dielectric layer and this dielectric plugs.
8. a manufacture method for semiconductor structure, comprising:
One first through hole is formed, to expose the conducting film that this laminated construction has one first electric conducting material in a laminated construction;
Form a dielectric layer in this first through hole;
This first through hole is filled with a conductive plunger;
One second through hole exposing this dielectric layer and this conducting film is formed in this laminated construction;
Remove this conducting film of part that this second through hole exposes, to be formed by the outward extending hole of this second through hole;
With one second this hole of filled with conductive material; And
This second through hole is filled with a dielectric plugs.
9. the manufacture method of semiconductor structure according to claim 8, wherein this second through hole exposes this dielectric layer in this conducting film and this first through hole and this conductive plunger, this partially conductive film that this second through hole exposes is removed by an etch step, this etch step for the etch rate of this conducting film higher than the etch rate for this dielectric layer and this conductive plunger.
10. the manufacture method of semiconductor structure according to claim 8, more comprising formation one conduction is connected on this conductive plunger, this second electric conducting material be wherein filled in this hole is formation one conductive stripe, and the profile of this conductive stripe is defined by the sidewall of this first through hole and this second through hole.
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