CN102569035A - Method for reworking wafer after interruption of back metallization process - Google Patents
Method for reworking wafer after interruption of back metallization process Download PDFInfo
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- CN102569035A CN102569035A CN2012100445788A CN201210044578A CN102569035A CN 102569035 A CN102569035 A CN 102569035A CN 2012100445788 A CN2012100445788 A CN 2012100445788A CN 201210044578 A CN201210044578 A CN 201210044578A CN 102569035 A CN102569035 A CN 102569035A
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Abstract
The invention relates to a method for reworking a wafer after interruption of a back metallization process. The method comprises the following steps of: when the current back metallization process is interrupted because of failure of a cavity, measuring a thickness of the current metal layer on the surface of the wafer as a first thickness, keeping high vacuum in the cavity, and reducing temperature of the wafer; breaking the vacuum in the cavity, and taking the wafer out; returning to the high-vacuum cavity to bake the wafer; and continuing to perform back metallization on the current metal layer. According to the method, after the cavity fails, high-vacuum temperature reduction is adopted, the oxidizability of the taken wafer is reduced, the wafer is baked in the high-vacuum cavity, and deposition is performed on the current metal layer, so that stripping among back metal layers is prevented effectively; and therefore, the yield and the reliability of the wafer are improved.
Description
Technical field
The present invention relates to technical field of semiconductors, the reworking method of wafer after particularly a kind of back metal process disruption.
Background technology
In the making flow process of semiconductor device, to metallize at chip back surface usually, the chip back surface metallization claims that again back metal technology, its main purpose are to reduce contact resistance.The metal of chip back surface adopts evaporator to evaporate usually or adopts sputtering unit to carry out sputter and forms, and under the high vacuum process conditions, accomplishes chip back surface depositing Ti, Ni, Ag, metals such as Au.
In the back metal technology of wafer, when Metal Deposition has taken place wafer surface, the back metal technical process is interrupted, and at this moment, the benefit that the wafer after the process disruption need carry out the residual metallic layer is long.Mend growth process and can be divided into two kinds: a kind ofly continue technology, another kind ofly come back to high vacuum state board continuation technology again for must vacuum breaker carrying out maintenance of equipment for the technology board keeps vacuum state.For first kind of situation, generally peeling off of metal level can not taken place.Be left intact for second kind of situation and metal level to take place when continuing technology easily peel off.
How to the processing of doing over again of the wafer after the back metal process disruption of said second kind of situation, making that the chip back surface metal level after doing over again does not peel off, guarantee the yield and the reliability of wafer, is a difficult problem in the industry.
Summary of the invention
The reworking method that the purpose of this invention is to provide wafer after a kind of back metal process disruption is to prevent causing peeling off between the chip back surface metal level because of vacuum breaker.
Technical solution of the present invention is the reworking method of wafer after a kind of back metal process disruption, may further comprise the steps:
After the chamber fault causes current back metal process disruption, measure the current metal layer thickness of wafer surface and be designated as first thickness, keep the chamber high vacuum, said wafer is lowered the temperature;
The chamber vacuum breaker takes out said wafer;
Said wafer returns to high-vacuum chamber and toasts;
Said wafer continues the back metal technology of current metal level.
As preferably: continue in the step of back metal technology of current metal level at said wafer; When first thickness of the current metal level of said wafer surface during less than current metal level desired thickness; Said wafer surface is deposited the current metal level of second thickness, and said second thickness is the difference of the desired thickness and first thickness.
As preferably: when said difference during less than 100 dusts, said second thickness is 100 dusts.
As preferably: continue in the step of back metal technology of current metal level at said wafer; When first thickness of the current metal level of said wafer surface is identical with the current metal level desired thickness of wafer surface; Said wafer surface is deposited the current metal level of the 3rd thickness, then deposit lower metal layer.
As preferably: said the 3rd thickness is 100 dusts-500 dusts.
As preferably: the air pressure of said chamber high vacuum is less than 9E-7torr.
As preferably: return in the step that high-vacuum chamber toasts at said wafer, the temperature of said baking is greater than 100 ℃, and the time of baking was greater than 3 minutes.
As preferably: in the step that said wafer is lowered the temperature, the temperature after the said wafer cooling is less than 60 ℃.
Compared with prior art; The present invention adopts the high vacuum cooling after the chamber fault, reduce the oxidized property after wafer takes out; Returning high-vacuum chamber again toasts; Carry out the deposition of current metal level again, effectively prevented peeling off between the metal layer on back, thereby improve the yield and the reliability of wafer.
Description of drawings
Fig. 1 is the flow chart of the reworking method of wafer after the back metal process disruption of the present invention.
Embodiment
The present invention below will combine accompanying drawing to do further to detail:
A lot of details have been set forth in the following description so that make much of the present invention.But the present invention can implement much to be different from alternate manner described here, and those skilled in the art can do similar popularization under the situation of intension of the present invention, so the present invention does not receive the restriction of following disclosed practical implementation.
Secondly, the present invention utilizes sketch map to be described in detail, when the embodiment of the invention is detailed; For ease of explanation; The profile of expression device architecture can be disobeyed general ratio and done local the amplification, and said sketch map is instance, and it should not limit the scope of the present invention's protection at this.The three dimensions size that in actual fabrication, should comprise in addition, length, width and the degree of depth.
Fig. 1 shows the flow chart of the reworking method of wafer after the back metal process disruption of the present invention; This method is mainly used in by the chamber fault and causes the back metal process disruption, and need carry out the situation of the back metal technology that maintenance of equipment recovers to interrupt again through vacuum breaker.
See also shown in Figure 1, in the present embodiment,
In step 101, after the chamber fault causes current back metal process disruption, measure the current metal layer thickness of wafer surface and be designated as first thickness; Keep the chamber high vacuum, said wafer is lowered the temperature, because wafer is in the deposition process of metal level; Temperature is higher, and the temperature of toasting before the smithcraft overleaf is higher, so need lower the temperature to wafer; To prevent in atmosphere, causing the autoxidation layer growth too fast after wafer from going out chamber owing to excessive temperature; Temperature after the said wafer cooling is the best less than 60 ℃ to drop to normal temperature, and the air pressure of said chamber is less than 9E-7torr;
In step 102, the chamber vacuum breaker takes out said wafer; Carry out maintenance of equipment; The said wafer that takes out exposes in atmosphere, and not oxidized for wafer, said wafer is preferably in 1 hour and turns back in the high-vacuum chamber again; Said wafer after the taking-up also can be placed in the inert gas, in case oxidation;
In step 103; After maintenance of equipment finishes; Wafer returns to high-vacuum chamber and toasts, and the temperature of said baking is greater than 100 ℃, and the time of baking was greater than 3 minutes; The air pressure of said chamber is less than 9E-7torr, and the effect of said baking is to remove the steam and other volatilizable chemical substances that wafer surface possibly sticked;
In step 104, said wafer continues current back metal technology, and first thickness that records when step 101 is during less than current metal level desired thickness; Wafer surface is deposited the current metal level of second thickness; Said second thickness is the difference of the current metal level desired thickness and first thickness, and when said difference during less than 100 dusts, said second thickness is 100 dusts; Because when second thickness is too thin; The current metal level connecting of the current metal level of second thickness and first thickness is bad, thereby causes lower metal layer and current metal level adhesive force bad, is prone to cause metal interlevel to peel off; When first thickness that records when step 101 is identical with the current metal level desired thickness of wafer surface; Said wafer surface is deposited the current metal level of the 3rd thickness; Then deposit lower metal layer; Because the current metal level of first thickness is unavoidably understood some autoxidation after the chamber vacuum breaker takes out, the current metal level that deposits said the 3rd thickness well is connected the current metal level of said first thickness, thereby strengthens the adhesive force between current metal level and the lower metal layer; Avoid metal interlevel to peel off; The 3rd thickness of the current metal level of said wafer surface with different product as a reference for the technology tolerance of back metal thickness, electrical property under the situation of the chip back surface metal film thickness actual value value of departing from objectives, performances such as stability still can be accepted; This scope that allows to depart from is the technology tolerance of chip back surface metal film thickness, and the 3rd thickness of the current metal level of said wafer surface is 100 dusts-500 dusts.
The present invention adopts the high vacuum cooling after the chamber fault, reduce the oxidized property after wafer takes out; Returning high-vacuum chamber again toasts; Carry out the deposition of current metal level again, effectively prevented peeling off between the metal layer on back, thereby improve the yield and the reliability of wafer.
The above is merely preferred embodiment of the present invention, and all equalizations of being done according to claim scope of the present invention change and modify, and all should belong to the covering scope of claim of the present invention.
Claims (8)
1. the reworking method of wafer after the back metal process disruption is characterized in that, may further comprise the steps:
After the chamber fault causes current back metal process disruption, measure the current metal layer thickness of wafer surface and be designated as first thickness, keep the chamber high vacuum, said wafer is lowered the temperature;
The chamber vacuum breaker takes out said wafer;
Said wafer returns to high-vacuum chamber and toasts;
Said wafer continues the back metal technology of current metal level.
2. the reworking method of wafer after the back metal process disruption according to claim 1; It is characterized in that: continue in the step of back metal technology of current metal level at said wafer; When first thickness of the current metal level of said wafer surface during less than current metal level desired thickness; Wafer surface is deposited the current metal level of second thickness, and said second thickness is the difference of the desired thickness and first thickness.
3. the reworking method of wafer after the back metal process disruption according to claim 2 is characterized in that: when said difference during less than 100 dusts, second thickness is 100 dusts.
4. the reworking method of wafer after the back metal process disruption according to claim 1; It is characterized in that: continue in the step of back metal technology of current metal level at said wafer; When first thickness of the current metal level of said wafer surface is identical with the current metal level desired thickness of wafer surface; Wafer surface is deposited the current metal level of the 3rd thickness, then deposit lower metal layer.
5. the reworking method of wafer after the back metal process disruption according to claim 4 is characterized in that: said the 3rd thickness is 100 dusts-500 dusts.
6. the reworking method of wafer after the back metal process disruption according to claim 1, it is characterized in that: the air pressure of said chamber high vacuum is less than 9E-7torr.
7. the reworking method of wafer after the back metal process disruption according to claim 1 is characterized in that: return in the step that high-vacuum chamber toasts at said wafer, the temperature of said baking is greater than 100 ℃, and the time of baking was greater than 3 minutes.
8. the reworking method of wafer after the back metal process disruption according to claim 1 is characterized in that: in the step that said wafer is lowered the temperature, the temperature after the said wafer cooling is less than 60 ℃.
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| CN201210044578.8A CN102569035B (en) | 2012-02-27 | 2012-02-27 | The reworking method of wafer after back metal process disruption |
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| CN102569035B CN102569035B (en) | 2016-06-29 |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104576347A (en) * | 2014-08-18 | 2015-04-29 | 上海华虹宏力半导体制造有限公司 | Method for improving back metallization of IGBT (Insulated Gate Bipolar Transistor) |
| CN107623051A (en) * | 2017-08-30 | 2018-01-23 | 平煤隆基新能源科技有限公司 | The handling process of the inclined thin slice of plated film thickness in a kind of PECVD processes |
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| CN1233854A (en) * | 1998-04-30 | 1999-11-03 | 日本电气株式会社 | Method for forming interconnection structure |
| CN1428455A (en) * | 2001-12-25 | 2003-07-09 | 中国科学院金属研究所 | Gas-phase deposition coating and vacuum heat-treatment on-line combined composite coating equipment |
| CN101211773A (en) * | 2006-12-30 | 2008-07-02 | 上海先进半导体制造股份有限公司 | Method for preventing chip back metal peeling |
| CN101702408A (en) * | 2005-03-30 | 2010-05-05 | 富士通微电子株式会社 | Semiconductor device and manufacturing method thereof |
| CN102097288A (en) * | 2009-12-14 | 2011-06-15 | 北大方正集团有限公司 | Rework method for back-side metal process |
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2012
- 2012-02-27 CN CN201210044578.8A patent/CN102569035B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1233854A (en) * | 1998-04-30 | 1999-11-03 | 日本电气株式会社 | Method for forming interconnection structure |
| CN1428455A (en) * | 2001-12-25 | 2003-07-09 | 中国科学院金属研究所 | Gas-phase deposition coating and vacuum heat-treatment on-line combined composite coating equipment |
| CN101702408A (en) * | 2005-03-30 | 2010-05-05 | 富士通微电子株式会社 | Semiconductor device and manufacturing method thereof |
| CN101211773A (en) * | 2006-12-30 | 2008-07-02 | 上海先进半导体制造股份有限公司 | Method for preventing chip back metal peeling |
| CN102097288A (en) * | 2009-12-14 | 2011-06-15 | 北大方正集团有限公司 | Rework method for back-side metal process |
Non-Patent Citations (1)
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| 中华人民共和国国家军用标准半导体集成电路总规范GJB597A-96: "中华人民共和国国家军用标准半导体集成电路总规范GJB597A-96", 《中华人民共和国国家军用标准半导体集成电路总规范GJB597A-96》, 31 December 1996 (1996-12-31) * |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104576347A (en) * | 2014-08-18 | 2015-04-29 | 上海华虹宏力半导体制造有限公司 | Method for improving back metallization of IGBT (Insulated Gate Bipolar Transistor) |
| CN104576347B (en) * | 2014-08-18 | 2017-08-08 | 上海华虹宏力半导体制造有限公司 | The ameliorative way of IGBT back face metalizations |
| CN107623051A (en) * | 2017-08-30 | 2018-01-23 | 平煤隆基新能源科技有限公司 | The handling process of the inclined thin slice of plated film thickness in a kind of PECVD processes |
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| CN102569035B (en) | 2016-06-29 |
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