CN102548254A - Nuclear-free preparation method of chip carrier - Google Patents

Nuclear-free preparation method of chip carrier Download PDF

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Publication number
CN102548254A
CN102548254A CN2010106236518A CN201010623651A CN102548254A CN 102548254 A CN102548254 A CN 102548254A CN 2010106236518 A CN2010106236518 A CN 2010106236518A CN 201010623651 A CN201010623651 A CN 201010623651A CN 102548254 A CN102548254 A CN 102548254A
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China
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layer
fine
line
conductive pole
chip carrier
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CN2010106236518A
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Inventor
朱兴华
苏新虹
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Peking University Founder Group Co Ltd
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Peking University Founder Group Co Ltd
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Priority to CN2010106236518A priority Critical patent/CN102548254A/en
Publication of CN102548254A publication Critical patent/CN102548254A/en
Pending legal-status Critical Current

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Abstract

The invention provides a nuclear-free preparation method of a chip carrier. The method comprises the following steps: preparing at least two fine circuit layers, an inner conductive column layer and an inner insulating layer on a carrier plate so as to obtain an inner fine circuit board, wherein the inner conductive column layer and the inner insulating layer are positioned between the at least two fine circuit layers; and preparing at least one conductive column layer, at least one outer insulating layer and at least one outer fine circuit layer on at least one surface of the inner fine circuit board. According to the invention, the nuclear-free preparation method is adopted for preparing the chip carrier; an image transfer method is adopted for preparing the conductive column layers; since pure resin type insulating layers are laminated, the surfaces of the ground insulating layers are smoother and the insulating layers and the fine circuit layers can be bonded better so as to ensure the reliability and qualified rate of products; moreover, the process of grinding the laminated insulating layers is not limited by the layer number of the chip carrier. The nuclear-free preparation method can be used for preparing chip carriers with different odd numbers of fine circuit layers or different even numbers of fine circuit layers.

Description

The seedless manufacture method of chip carrier
Technical field
The present invention relates to make the circuit board technology field, particularly, relate to a kind of seedless manufacture method of chip carrier.
Background technology
The fast development of electronic technology makes that the integrated level of semiconductor device is increasingly high, and base plate for packaging is developed to multi-layer sheet by lamina gradually, for example high density PCB (printed circuit board (PCB)) base plate for packaging.In order to improve the integrated level of PCB base plate for packaging, adopt the interlayer interconnection technique that multilayer fine-line layer is connected, to obtain more available wiring area in limited space, the fine-line layer typically refers to live width and distance between centers of tracks is the line layer of 25um.
It directly has influence on the adhesion between follow-up fine-line and the insulating barrier because of the glass fiber after grinding exposes serious situation when making the fine-line product based on seedless manufacture craft, to use the insulating layer material that contains glass fiber at present to make appearance easily, causes the low problem of reliability of products difference and qualification rate.
Summary of the invention
For addressing the above problem, the present invention provides a kind of seedless manufacture method of chip carrier, is used for the problem that rate of finished products is low, cost is high of prior art chips carrier.
The present invention provides a kind of seedless manufacture method of chip carrier, wherein, comprising:
Preparing two layers of fine line layer at least, internal layer conductive pole layer and inner insulation layer between the said line layer of two layers of fine at least on the support plate, to obtain internal layer fine-line plate;
On the one side at least of said internal layer fine-line plate, prepare at least one deck conductive pole layer, one deck outer insulation and the outer fine-line layer of one deck at least at least.
Preferably, said primary insulation layer material and/or said outer layer insulation layer material are pure resin, and said pure resin comprises: epoxy resin, polyimide resin or the BMI three BT resin of tremnbling.
Preferably, said support plate is copper support plate.
Preferably, saidly preparing two layers of fine line layer at least, internal layer conductive pole layer and inner insulation layer between the said line layer of two layers of fine at least on the support plate, also comprising before the internal layer fine-line plate obtaining:
Said support plate is carried out polishing, and preferably, the roughness that makes said support plate is between 0.1-0.3 μ m.
Preferably, saidly preparing two layers of fine line layer at least, internal layer conductive pole layer and inner insulation layer between the said line layer of two layers of fine at least on the support plate, comprising to obtain internal layer fine-line plate:
On support plate, electroplate the first fine-line layer and internal layer conductive pole layer;
On said first fine-line layer and internal layer conductive pole layer, cover inner insulation layer, said inner insulation layer is carried out lamination and milled processed obtain the plane that said inner insulation layer and internal layer conductive pole layer are formed;
On the plane of said inner insulation layer and internal layer conductive pole layer composition, make one deck conductive seed layer, the preparation second fine-line layer on said conductive seed layer through the mode of Metal Deposition or metal splash.
Preferably, saidly on support plate, electroplate the first fine-line layer and internal layer conductive pole layer comprises:
The said first fine-line layer and internal layer conductive pole layer are carried out after brown handles the said inner insulation layer of covering one deck on the said first fine-line layer and internal layer conductive pole layer.
Preferably, the mode through heavy copper, metal splash or flash prepares said conductive seed layer on said plane.
Preferably, saidly making two layers of fine line layer at least, internal layer conductive pole layer and inner insulation layer between the said line layer of two layers of fine at least on the support plate, also comprising before the internal layer fine-line plate obtaining:
Through preparation one deck conductive seed layer on the said support plate of polishing, on said conductive seed layer, prepare said internal layer fine-line plate.
Preferably, said on the one side at least of said internal layer fine-line plate, prepare at least one deck conductive pole layer, at least one deck outer insulation and at least the outer fine-line layer of one deck comprise:
One side in said internal layer fine lines is circuit board double sided prepares the first conductive pole layer and first outer insulation, the another side in said internal layer fine lines is circuit board double sided and the preparation second conductive pole layer, second outer insulation;
Respectively said first outer insulation and second outer insulation are carried out lamination and milled processed and obtain the plane that plane that said first outer insulation and the said first conductive pole layer form and the said second conductive pole layer and said second outer insulation are formed;
The plane for preparing the 3rd conductive seed layer and said second conductive pole layer and said second outer insulation composition respectively on the plane of said first outer insulation and said first conductive pole layer composition prepares the 4th conductive seed layer;
Preparing the 3rd fine-line layer on said the 3rd conductive seed layer and preparation the 4th fine-line layer on said the 4th conductive seed layer respectively.
Preferably, said one side in said internal layer fine lines is circuit board double sided prepares the first conductive pole layer and first outer insulation, and the another side in said internal layer fine lines is circuit board double sided comprises with the preparation second conductive pole layer, second outer insulation:
The brown processing is carried out on the surface of the said first conductive pole layer and the surface of the second conductive pole layer.
The present invention also provides a kind of chip carrier, and wherein, said chip carrier adopts above-mentioned any seedless manufacture method to make and obtains.
Preferably, the live width and/or the distance between centers of tracks of said fine-line layer are less than or equal to 25um, preferably are less than or equal to 15um, for example are 10um.
The present invention has following beneficial effect:
Present embodiment prepares chip carrier through seedless manufacture method; Be coated with conductive pole layer fully through image transfer method incoming call; Through selecting the insulating barrier of the pure resinous type of lamination for use, can make the surface of the insulating barrier after the grinding more level and smooth, help between insulating barrier and the fine-line layer better adhesion being arranged; Guarantee reliability of products and qualification rate; Simultaneously, do not receive the restriction of the chip carrier number of plies when after each insulating barrier is carried out lamination treatment, grinding, help preparing chip carrier with different odd layer fine-line layer or different even level fine-line layers.
Description of drawings
Fig. 1 is the flow chart of seedless manufacture method first embodiment of chip carrier provided by the invention;
Fig. 2 is the flow chart of seedless manufacture method second embodiment of chip carrier provided by the invention;
Fig. 3 a-3j is the generalized section of product in the seedless manufacture method of chip carrier provided by the invention.
Embodiment
The present invention provides a kind of seedless manufacture method of chip carrier, it is characterized in that, comprising:
Preparing two layers of fine line layer at least, internal layer conductive pole layer and inner insulation layer between the said line layer of two layers of fine at least on the support plate, to obtain internal layer fine-line plate;
On the one side at least of said internal layer fine-line plate, prepare at least one deck conductive pole layer, one deck outer insulation and the outer fine-line layer of one deck at least at least.
Preferably, in various embodiments of the present invention, said primary insulation layer material and/or said outer layer insulation layer material are pure resin, and said pure resin comprises: epoxy resin, polyimide resin or the BMI three BT resin of tremnbling.
Preferably, in various embodiments of the present invention, said support plate is copper support plate.
Preferably, in various embodiments of the present invention, saidly preparing two layers of fine line layer at least, internal layer conductive pole layer and inner insulation layer between the said line layer of two layers of fine at least on the support plate, also comprising before the internal layer fine-line plate obtaining:
Said support plate is carried out polishing, and preferably, the roughness that makes said support plate is between 0.1-0.3 μ m.
Preferably, in various embodiments of the present invention, saidly preparing two layers of fine line layer at least, internal layer conductive pole layer and inner insulation layer between the said line layer of two layers of fine at least on the support plate, comprising to obtain internal layer fine-line plate:
On support plate, electroplate the first fine-line layer and internal layer conductive pole layer;
On said first fine-line layer and internal layer conductive pole layer, cover inner insulation layer, said inner insulation layer is carried out lamination and milled processed obtain the plane that said inner insulation layer and internal layer conductive pole layer are formed;
On the plane of said inner insulation layer and internal layer conductive pole layer composition, make one deck conductive seed layer, the preparation second fine-line layer on said conductive seed layer through the mode of Metal Deposition or metal splash.
Preferably, in various embodiments of the present invention, saidly on support plate, electroplate the first fine-line layer and internal layer conductive pole layer comprises:
The said first fine-line layer and internal layer conductive pole layer are carried out after brown handles the said inner insulation layer of covering one deck on the said first fine-line layer and internal layer conductive pole layer.
Preferably, in various embodiments of the present invention, the mode through heavy copper, metal splash or flash prepares said conductive seed layer on said plane.
Preferably, in various embodiments of the present invention, saidly making two layers of fine line layer at least, internal layer conductive pole layer and inner insulation layer between the said line layer of two layers of fine at least on the support plate, also comprising before the internal layer fine-line plate obtaining:
Through preparation one deck conductive seed layer on the said support plate of polishing, on said conductive seed layer, prepare said internal layer fine-line plate.
Preferably, in various embodiments of the present invention, said on the one side at least of said internal layer fine-line plate, prepare at least one deck conductive pole layer, at least one deck outer insulation and at least the outer fine-line layer of one deck comprise:
One side in said internal layer fine lines is circuit board double sided prepares the first conductive pole layer and first outer insulation, the another side in said internal layer fine lines is circuit board double sided and the preparation second conductive pole layer, second outer insulation;
Respectively said first outer insulation and second outer insulation are carried out lamination and milled processed and obtain the plane that plane that said first outer insulation and the said first conductive pole layer form and the said second conductive pole layer and said second outer insulation are formed;
The plane for preparing the 3rd conductive seed layer and said second conductive pole layer and said second outer insulation composition respectively on the plane of said first outer insulation and said first conductive pole layer composition prepares the 4th conductive seed layer;
Preparing the 3rd fine-line layer on said the 3rd conductive seed layer and preparation the 4th fine-line layer on said the 4th conductive seed layer respectively.
Preferably; In various embodiments of the present invention; Said one side in said internal layer fine lines is circuit board double sided prepares the first conductive pole layer and first outer insulation, and the another side in said internal layer fine lines is circuit board double sided comprises with the preparation second conductive pole layer, second outer insulation:
The brown processing is carried out on the surface of the said first conductive pole layer and the surface of the second conductive pole layer.
The present invention provides a kind of chip carrier, it is characterized in that, said chip carrier adopts foregoing seedless manufacture method to make and obtains.
Preferably, in various embodiments of the present invention, the live width and/or the distance between centers of tracks of said fine-line layer are less than or equal to 25um, preferably are less than or equal to 15um, for example are 10um.
Various embodiments of the present invention can be used for various chip carriers, for example printed circuit board (PCB).
In each used in the present invention conductive structure, can adopt copper or aluminum or its electrical conductivity alloy material.
For making those skilled in the art understand technical scheme of the present invention better, be described in detail below in conjunction with the seedless manufacture method of accompanying drawing to chip carrier provided by the invention.
Fig. 1 is the flow chart of seedless manufacture method first embodiment of chip carrier provided by the invention.As shown in Figure 1, the workflow of the seedless manufacture method of present embodiment chip carrier specifically comprises the steps:
Step 101, on support plate, make the first fine-line layer, internal layer conductive pole layer, inner insulation layer and the second fine-line layer successively.
In the present embodiment, be that example is introduced technical scheme with copper support plate, on support plate, electroplate the first fine-line layer and internal layer conductive pole layer through the image transfer method; On the first fine-line layer and conductive pole layer, cover inner insulation layer then, the height of inner insulation layer is higher than the conductive pole layer, and inner insulation layer can be pure resin; For example can tremnble for epoxy resin, polyimide resin or BMI three (Bismaleimide Triazine, BT) pure resin such as resin is when the insulating barrier of the pure resinous type of milled processed; The surface of insulating barrier is more level and smooth, and helping has better adhesion between insulating barrier and the fine-line layer, improves the reliability of chip carrier; In practical application; Can select the type of resin according to the dielectric constant of needed insulating barrier,, then insulating barrier carried out milled processed so that the conductive pole layer exposes to improve the performance of chip carrier; Obtain the common flat surface of forming of insulating barrier and conductive pole layer; On this flat surface, make the second fine-line layer through the image transfer method then, on flat surface, make line layer and can avoid line layer to break off, guarantee rate of finished products.
Etch away support plate then, obtain independently internal layer fine-line layer, get into step 102 then.
Step 102, on internal layer fine-line layer two-sided, make at least one deck conductive pole layer, one deck outer insulation and the outer fine-line layer of one deck at least at least respectively.
Plated conductive post layer simultaneously on internal layer fine-line layer two-sided respectively; Be distributed in then on the conductive pole layer on two surfaces and respectively cover one deck outer insulation; The height of outer insulation is higher than the conductive pole layer; Then each outer insulation is carried out milled processed so that the conductive pole layer exposes, obtain two flat surfaces of forming jointly by outer insulation and conductive pole layer respectively, on each flat surface, make the outer fine-line layer of one deck at least through the image transfer method then.Wherein, the outer layer insulation layer material can be selected pure resins such as epoxy resin, polyimide resin or BT resin for use.
Repeating step 102 can obtain the chip carrier of more fine-line layers.
Present embodiment prepares chip carrier through seedless manufacture method; Prepare the conductive pole layer through the image transfer method; Select for use the material of pure resinous type to make insulating barrier, insulating barrier comprises inner insulation layer and outer insulation, can make the surface of the insulating barrier after the grinding more level and smooth; Help between insulating barrier and the fine-line layer better adhesion being arranged; Improve the reliability of chip carrier, and the mode that can adopt dual side build-up layers or single face to increase layer prepares the chip carrier of odd-level fine-line layer or even level fine-line layer, dual side build-up layers is on carrier two-sided, to make the fine-line layer simultaneously; It is on a single face of carrier, to make fine-line that single face increases layer, thereby helps preparing the chip carrier of the fine-line layer with various different numbers of plies.
Fig. 2 is the flow chart of seedless manufacture method second embodiment of chip carrier provided by the invention.As shown in Figure 2, the preparation method of present embodiment chips carrier comprises:
Step 201, on copper support plate the preparation the first fine-line layer.
Fig. 3 a-3j is the generalized section of product in the seedless manufacture method of chip carrier provided by the invention.In embodiments of the present invention, be that example is introduced technical scheme with Fig. 3 a-3j.Consult Fig. 3 a, the material of support plate 101 is a copper, and support plate 101 is carried out polishing; The roughness that makes support plate 101 avoids dredging the line layer breach that the hole problem causes between 0.1-0.3 μ m, improve the rate of finished products of chip carrier; On support plate 101, electroplate first conductive seed layer 201; First conductive seed layer 201 can be copper conductive seed layer, prepares the first fine-line layer 102 through the image transfer method then, and image transfer method detailed process is included in and covers one deck dry film on the Seed Layer; Obtain having the dry film of the pattern of the first fine-line layer through overexposure, after developing; On this dry film, electroplate the first fine-line layer 102, again the dry film etching is removed, get into step 202 then.
Step 202, on the first fine-line layer preparation internal layer conductive pole layer.
Consult Fig. 3 b, on the first fine-line layer 102, prepare dry film, on the pattern of this dry film, electroplate then and obtain internal layer conductive pole layer 103, again the dry film etching is removed, get into step 203 then with conductive pole layer pattern through the image transfer method.
Step 203, at the surface coverage inner insulation layer of the first fine-line layer and internal layer conductive pole layer.
Consult Fig. 3 c; On the first fine-line layer 102 and internal layer conductive pole layer 103, cover one deck inner insulation layer 104; Inner insulation layer 104 is pure resin; For example can be epoxy resin, polyimide resin or BT resin etc., the height of inner insulation layer 104 is higher than internal layer conductive pole layer 103, then inner insulation layer 104 is carried out lamination treatment and grind internal layer conductive pole layer 103 is exposed; Obtain internal layer conductive pole layer 103 and form smooth plane with inner insulation layer 104; The first fine-line layer is prepared on the flat surface, avoids the first fine-line layer to fracture and guarantee that the first fine-line layer fully contacts with internal layer conductive pole layer 103, improves the rate of finished products of follow-up line layer.After obtaining the smooth plane of internal layer conductive pole layer 103 and inner insulation layer 104 compositions, get into step 204.
Step 204, on the plane that internal layer conductive pole layer and inner insulation layer are formed the preparation second fine-line layer.
Consult Fig. 3 d-3e; Form preparation second conductive seed layer 202 on the smooth plane at internal layer conductive pole layer 103 and inner insulation layer 104; On second conductive seed layer 202, prepare dry film through the image transfer method then with the second fine-line layer, 105 pattern; Obtain connecting through internal layer conductive pole layer 103 between the second fine-line layer, 105, the first fine-line layer 102 and the second fine-line layer 105 in plating on the pattern of this dry film again, after the dry film etching is removed; Obtain internal layer fine-line plate, get into step 205 then.
In practical application, repeat above-mentioned steps and can obtain to have the more internal layer fine-line plate of multilayer fine-line layer.
Step 205, on the first fine-line layer preparation the first conductive pole layer and on the second fine-line layer preparation the second conductive pole layer.
Consult Fig. 3 f-3g; Adopt the mode of dual side build-up layers; Through the image transfer method respectively on the surface of the first fine-line layer 102 of internal layer fine-line plate and the second fine-line layer 105 preparation simultaneously have the dry film of conductive pole layer pattern, then on the dry film pattern on two surfaces, electroplate and obtain the first conductive pole layer 106 and the second conductive pole layer 107, present embodiment is through while plated conductive post layer on the surface of the first fine-line layer 102 and the second fine-line layer 105; Help improving production efficiency of products; Then the dry film etching is removed, again first conductive seed layer 201 and second conductive seed layer, 202 etchings are removed, get into step 206 then.
Step 206, covering first outer insulation on the surface of the first fine-line layer and conductive pole layer and on the surface of the second fine-line layer and conductive pole layer, covering second outer insulation.
Consult Fig. 3 h; Cover first outer insulation 108 on the surface of the first fine-line layer 102 and the first conductive pole layer, 106 composition and on the surface of the second fine-line layer 105 and the second conductive pole layer, 107 composition, covering second outer insulation 109; Then first outer insulation 108 and second outer insulation 109 are carried out lamination treatment and milled processed simultaneously, obtain the flat surface of the first conductive pole layer 106 and first outer insulation, 108 compositions and the flat surface of the second conductive pole layer 107 and second outer insulation, 109 compositions respectively.Get into step 207 then.
Step 207, on the flat surface that preparation the 3rd fine-line layer and the second conductive pole layer and second outer insulation on the flat surface that the first conductive pole layer and first outer insulation are formed are formed preparation the 4th fine-line layer.
Consult Fig. 3 i-3j; Preparing the 3rd conductive seed layer 203 on the flat surface of the first conductive pole layer 106 and first outer insulation, 108 compositions and preparation the 4th conductive seed layer 204 on the flat surface of the second conductive pole layer 107 and second outer insulation, 109 compositions respectively; Then preparing the 3rd fine-line layer 110 on the 3rd conductive seed layer 203 and preparation the 4th fine-line layer 111 on the 4th conductive seed layer 204; The 3rd fine-line layer 110 and the 4th fine-line layer 111 are outer fine-line layer; After etching is removed the 3rd conductive seed layer 203 and the 4th conductive seed layer 204, can obtain having the chip carrier of 4 layers of line layer.
Repeat above-mentioned steps, can obtain having the chip carrier of the fine-line layer more than at least 4 layers.
In practical application, also can prepare some the fine-line layer in the chip carrier, during especially for the chip carrier of preparation odd number fine-line layer through the mode that single face increases layer.The live width of fine-line can be set at 20um in the present embodiment, and the spacing between each layer fine-line can be set at 20um.
Present embodiment prepares chip carrier through seedless manufacture method; Be coated with conductive pole layer fully through image transfer method incoming call; Select the insulating barrier of pure resinous type during lamination treatment for use; Can make the surface of the insulating barrier after the grinding more level and smooth; Help between insulating barrier and the fine-line layer better adhesion being arranged, improve the reliability of chip carrier, and the mode that adopts single face to increase layer or dual side build-up layers also helps preparing the chip carrier with different odd layer fine-line layer or different even level fine-line layers.
The present invention also provides a kind of chip carrier through method for preparing, and the rate of finished products of this chip carrier is high, reliability is high.
It is understandable that above execution mode only is the illustrative embodiments that adopts for principle of the present invention is described, yet the present invention is not limited thereto.For the one of ordinary skilled in the art, under the situation that does not break away from spirit of the present invention and essence, can make various modification and improvement, these modification also are regarded as protection scope of the present invention with improving.

Claims (12)

1. the seedless manufacture method of a chip carrier is characterized in that, comprising:
Preparing two layers of fine line layer at least, internal layer conductive pole layer and inner insulation layer between the said line layer of two layers of fine at least on the support plate, to obtain internal layer fine-line plate;
On the one side at least of said internal layer fine-line plate, prepare at least one deck conductive pole layer, one deck outer insulation and the outer fine-line layer of one deck at least at least.
2. the seedless manufacture method of chip carrier according to claim 1; It is characterized in that; Said primary insulation layer material and/or said outer layer insulation layer material are pure resin, and said pure resin comprises: epoxy resin, polyimide resin or the BMI three BT resin of tremnbling.
3. the seedless manufacture method of chip carrier according to claim 1 and 2 is characterized in that, said support plate is copper support plate.
4. according to the seedless manufacture method of arbitrary described chip carrier in the aforementioned claim; It is characterized in that; Saidly preparing two layers of fine line layer at least, internal layer conductive pole layer and inner insulation layer between the said line layer of two layers of fine at least on the support plate, also comprising before the internal layer fine-line plate obtaining:
Said support plate is carried out polishing, and preferably, the roughness that makes said support plate is between 0.1-0.3 μ m.
5. according to the seedless manufacture method of arbitrary described chip carrier in the aforementioned claim; It is characterized in that; Saidly preparing two layers of fine line layer at least, internal layer conductive pole layer and inner insulation layer between the said line layer of two layers of fine at least on the support plate, comprising to obtain internal layer fine-line plate:
On support plate, electroplate the first fine-line layer and internal layer conductive pole layer;
On said first fine-line layer and internal layer conductive pole layer, cover inner insulation layer, said inner insulation layer is carried out lamination and milled processed obtain the plane that said inner insulation layer and internal layer conductive pole layer are formed;
On the plane of said inner insulation layer and internal layer conductive pole layer composition, make one deck conductive seed layer, the preparation second fine-line layer on said conductive seed layer through the mode of Metal Deposition or metal splash.
6. the seedless manufacture method of chip carrier according to claim 5 is characterized in that, saidly on support plate, electroplates the first fine-line layer and internal layer conductive pole layer comprises:
The said first fine-line layer and internal layer conductive pole layer are carried out after brown handles the said inner insulation layer of covering one deck on the said first fine-line layer and internal layer conductive pole layer.
7. to go the seedless manufacture method of 5 or 6 described chip carriers according to right, it is characterized in that,
Mode through heavy copper, metal splash or flash prepares said conductive seed layer on said plane.
8. according to the seedless manufacture method of arbitrary described chip carrier in the aforementioned claim; It is characterized in that; Saidly making two layers of fine line layer at least, internal layer conductive pole layer and inner insulation layer between the said line layer of two layers of fine at least on the support plate, also comprising before the internal layer fine-line plate obtaining:
Through preparation one deck conductive seed layer on the said support plate of polishing, on said conductive seed layer, prepare said internal layer fine-line plate.
9. according to the seedless manufacture method of arbitrary described chip carrier in the aforementioned claim; It is characterized in that, said on the one side at least of said internal layer fine-line plate, prepare at least one deck conductive pole layer, at least one deck outer insulation and at least the outer fine-line layer of one deck comprise:
One side in said internal layer fine lines is circuit board double sided prepares the first conductive pole layer and first outer insulation, the another side in said internal layer fine lines is circuit board double sided and the preparation second conductive pole layer, second outer insulation;
Respectively said first outer insulation and second outer insulation are carried out lamination and milled processed and obtain the plane that plane that said first outer insulation and the said first conductive pole layer form and the said second conductive pole layer and said second outer insulation are formed;
The plane for preparing the 3rd conductive seed layer and said second conductive pole layer and said second outer insulation composition respectively on the plane of said first outer insulation and said first conductive pole layer composition prepares the 4th conductive seed layer;
Preparing the 3rd fine-line layer on said the 3rd conductive seed layer and preparation the 4th fine-line layer on said the 4th conductive seed layer respectively.
10. according to the seedless manufacture method of arbitrary described chip carrier in the aforementioned claim; It is characterized in that; Said one side in said internal layer fine lines is circuit board double sided prepares the first conductive pole layer and first outer insulation, and the another side in said internal layer fine lines is circuit board double sided comprises with the preparation second conductive pole layer, second outer insulation:
The brown processing is carried out on the surface of the said first conductive pole layer and the surface of the second conductive pole layer.
11. a chip carrier is characterized in that, any described seedless manufacture method is made and is obtained among the said chip carrier employing claim 1-10.
12. chip carrier according to claim 11 is characterized in that, the live width and/or the distance between centers of tracks of said fine-line layer are less than or equal to 25um, preferably are less than or equal to 15um, for example are 10um.
CN2010106236518A 2010-12-30 2010-12-30 Nuclear-free preparation method of chip carrier Pending CN102548254A (en)

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CN103826390A (en) * 2014-02-24 2014-05-28 广州兴森快捷电路科技有限公司 Thick copper printed circuit board and manufacturing method thereof
CN105552024A (en) * 2016-03-14 2016-05-04 京东方科技集团股份有限公司 Array substrate, manufacturing method thereof and display device
CN106028683A (en) * 2015-03-26 2016-10-12 住友电木株式会社 Manufacturing method of organic resin substrate, organic resin substrate and semiconductor device
CN111356309A (en) * 2020-04-15 2020-06-30 江苏普诺威电子股份有限公司 Manufacturing method of multilayer circuit board with high line alignment precision
CN112739020A (en) * 2020-12-15 2021-04-30 广德宝达精密电路有限公司 Method for manufacturing gold-plated circuit board

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Application publication date: 20120704