CN102931168A - Packaging substrate and manufacturing method thereof - Google Patents

Packaging substrate and manufacturing method thereof Download PDF

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Publication number
CN102931168A
CN102931168A CN2012104583594A CN201210458359A CN102931168A CN 102931168 A CN102931168 A CN 102931168A CN 2012104583594 A CN2012104583594 A CN 2012104583594A CN 201210458359 A CN201210458359 A CN 201210458359A CN 102931168 A CN102931168 A CN 102931168A
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CN
China
Prior art keywords
layer
conductive pole
packaging
dielectric layer
base plate
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Pending
Application number
CN2012104583594A
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Chinese (zh)
Inventor
王德峻
黄建华
罗光淋
方仁广
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Advanced Semiconductor Engineering Shanghai Inc
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Advanced Semiconductor Engineering Shanghai Inc
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Application filed by Advanced Semiconductor Engineering Shanghai Inc filed Critical Advanced Semiconductor Engineering Shanghai Inc
Priority to CN2012104583594A priority Critical patent/CN102931168A/en
Publication of CN102931168A publication Critical patent/CN102931168A/en
Pending legal-status Critical Current

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Abstract

The invention discloses a packaging substrate, and a manufacturing method of the packaging substrate, wherein the packaging substrate comprises a first dielectric layer; at least one first conductive pole which is formed in the first dielectric layer; a seed layer which is covered on an upper surface of the first dielectric layer and is provided with at least one opening corresponding to the first conductive pole; and a first circuit layer which is formed on the seed layer, electrically connected with the first conductive pole through an opening and is arranged corresponding to the seed layer.

Description

Base plate for packaging and manufacture method thereof
Technical field
The invention relates to a kind of base plate for packaging and manufacture method thereof, particularly relevant for a kind of interlayer conduction hole that increases in conjunction with base plate for packaging and the manufacture method thereof of reliability.
Background technology
Now, the semiconductor packages industry is in order to satisfy various high density and microminiaturized package requirements, for more how active, passive component and circuit carry and connect, semiconductor packages also develops multilayer circuit board (multi-layer circuit board) by odt circuit gradually, under the confined space, utilize interlayer interconnection technique (Interlayerconnection) can supply the circuit layout area of utilization to enlarge on the conductor package substrate (substrate), to reach the integrated circuit needs of high current densities, reduce the thickness of base plate for packaging, under the same substrate unit are, to hold more substantial circuit and electronic component.
General multilayer circuit base plate for packaging mainly by a plurality of circuit layers (circuit layer) and a plurality of dielectric layer (dielectric layer) alternately coincide consist of.Usually circuit layer is made by the technique of copper foil layer plating collocation patterning photoresist; And dielectric layer is formed between the circuit layer, in order to protection and separate each circuit layer; And each circuit layer can be electrically connected to each other by the conductive pole in the dielectric layer.In an available circuit layer manufacture craft, in order to electroplate upper Copper Foil as circuit layer, usually (conducting particles by sub-micron grade is formed to form first the Seed Layer of a thinner thickness on dielectric layer, generally formed by metallic), it can utilize the modes such as electroless plating (chemical plating), physical deposition or sputter to form.Afterwards, the recycling mode of electroplating and patterning photoresist layer on described Seed Layer to form electro-coppering as circuit layer; Then, recycle equally plating mode and conductive pole pattern photoresist layer, on circuit layer to form at least one conductive pole.
In above-mentioned circuit substrate, although the material of Seed Layer and circuit layer and conductive pole can be copper, but with the angle of micro-structural, Seed Layer is comprised of the conducting particles of sub-micron grade, and its micro-structural may be acted upon by temperature changes and change and then intensity can change.Therefore when the use state of circuit substrate at follow-up packaging technology and final products, the part that the thermal effect that produces can cause Seed Layer to contact with circuit layer and conductive pole is subject to the destruction of thermal stress (thermal stress) and easy generation is peeled off or the crack.And above-mentioned peel off or crack phenomenon can cause conductive pole and circuit layer Contact bad causes to be electrically connected deterioratedly between the two easily, and then reduces the structural reliability (reliability) of circuit substrate.
So, be necessary to provide a kind of base plate for packaging and manufacture method thereof, to solve the existing problem of prior art.
Summary of the invention
In view of this, the invention provides a kind of base plate for packaging and manufacture method thereof, to solve the problem of the existing circuit board structure reliability of prior art.
Main purpose of the present invention is to provide a kind of base plate for packaging and manufacture method thereof, it utilizes Seed Layer to form an opening in the position that is connected with conductive pole, and then so that the electric connection structure between circuit layer and the conductive pole is more reliable, and can guarantee the signal transmission effect of follow-up chip.
For reaching aforementioned purpose of the present invention, one embodiment of the invention provides a kind of base plate for packaging, and wherein said base plate for packaging comprises: one first dielectric layer, at least one the first conductive pole, a Seed Layer and one first circuit layer.Described the first conductive stud is formed in described the first dielectric layer.Described Seed Layer is covered in a upper surface of described the first dielectric layer, and corresponding described the first conductive pole forms at least one opening.Described the first circuit layer is formed on the described Seed Layer, and is electrically connected by described opening and described the first conductive pole, and described the first circuit layer and the corresponding spread configuration of described Seed Layer.
Moreover another embodiment of the present invention provides the manufacture method of another kind of base plate for packaging, and wherein said manufacture method comprises following steps: one first dielectric layer (a) is provided, has at least one the first conductive pole in described the first dielectric layer; (b) on described the first dielectric layer, form a Seed Layer; (c) by Ear Mucosa Treated by He Ne Laser Irradiation, make corresponding described the first conductive pole in described the first sublayer form at least one opening; (d) electroplate formation one first circuit layer in described Seed Layer, described the first circuit layer is electrically connected by described opening and described the first conductive pole; And (e) remove not the described Seed Layer that is covered by described the first circuit layer, so that described Seed Layer and the corresponding spread configuration of described the first circuit layer.
Compared with prior art, packaging structure of the present invention so not only can make the electric connection structure between circuit layer and the conductive pole more reliable, can also guarantee the signal transmission effect of chip.
For foregoing of the present invention can be become apparent, preferred embodiment cited below particularly, and cooperate appended graphicly, be described in detail below:
Description of drawings
Fig. 1 is the generalized section of one embodiment of the invention base plate for packaging.
Fig. 2 is the generalized section of another embodiment of the present invention base plate for packaging.
Fig. 3 A-3G is the step that represents one embodiment of the invention manufacture method in the mode of generalized section.
Embodiment
Below the explanation of each embodiment be with reference to additional graphic, can be in order to the specific embodiment of implementing in order to illustration the present invention.Moreover, the direction term that the present invention mentions, such as " on ", D score, " top ", " end ", 'fornt', 'back', " left side ", " right side ", " interior ", " outward ", " side ", " on every side ", " central authorities ", " level ", " laterally ", " vertically ", " vertically ", " axially ", " radially ", " the superiors " or " orlop " etc., only be the direction with reference to annexed drawings.Therefore, the direction term of use is in order to explanation and understands the present invention, but not in order to limit the present invention.
Please refer to shown in Figure 1ly, the base plate for packaging 1 of one embodiment of the invention mainly comprises: one first dielectric layer 10a, at least one the first conductive pole 11a, a second circuit layer 12, a Seed Layer 13 ', one first circuit layer 14, one second dielectric layer 10b and at least one the second conductive pole 11b.Described the first conductive pole 11a is formed in described the first dielectric layer 10a.Described second circuit layer 12 is formed at a lower surface of described the first dielectric layer 10a, and is electrically connected with described the first conductive pole 11a.Described Seed Layer 13 ' is covered in the upper surface of described the first dielectric layer 10a, and corresponding described the first conductive pole 11a forms at least one opening 130.Described the first circuit layer 14 is formed on the described Seed Layer 13 ', and is electrically connected with described the first conductive pole 11a by described opening 130, and described the first circuit layer 14 and described Seed Layer the 13 ' corresponding spread configuration.Described the second dielectric layer 10b is covered on described the first dielectric layer 10a and described the first circuit layer 14.Described the second conductive pole 11b is formed in the second dielectric layer 10b, and is electrically connected with described the first circuit layer 14.
Referring again to shown in Figure 1, the material of the first dielectric layer 10a of present embodiment can be dielectric resin material, for example glass layer is through containing epoxy resin dipping (epoxy) and the rear made B rank film (B-stage prepreg) of dry sclerosis, it utilizes its run gum and gummosis characteristic in HTHP, be pressed together on a loading plate or the workbench, then again be heating and curing and obtain described the first dielectric layer 10a, the height of described the first dielectric layer 10a but is not limited to this approximately between 30 to 150 microns.
In the present embodiment, described at least one the first conductive pole 11a forms with the technique of electroplating collocation patterning photoresist in advance, then just be embedded in described the first dielectric layer 10a, the shape of the cross section of described the first conductive pole 11a is optional from circular, triangle or polygon etc., its surface can be used as routing surface, plant ball surface or interlayer conduction; Moreover, second circuit layer 12 as described in the surface (such as lower surface) of described the first dielectric layer 10a can be selected to be pre-formed with similar technique.The material of described the first dielectric layer 10a and the first conductive pole 11a is such as being copper, nickel, gold, silver or aluminium etc., but is not limited to this.The height of described the first conductive pole 11a but is not limited to this approximately between 20 to 100 microns.The thickness of described second circuit layer 12 is significantly less than the height of described the first conductive pole 11a usually.Described second circuit layer 12 can be as an external circuit layer at this, and is electrically connected with described the first conductive pole 11a.
In the present embodiment, described Seed Layer 13 ' is comprised of the conducting particles of sub-micron grade, generally formed by metallic, and for example be copper, and the thickness of described Seed Layer 13 ' is equal to or less than 1 micron.Described Seed Layer 13 ' is to form in modes such as electroless plating (chemical plating), physical deposition or sputters to be covered on described the first dielectric layer 10a, and corresponding described the first conductive pole 11a forms at least one opening 130.The area of described opening 130 can be equal to or less than the cross-sectional area of described the first conductive pole 11a.
In the present embodiment, described the first circuit layer 14 is that the technique of electroplating collocation patterning photoresist is formed on the described Seed Layer 13 ', and is electrically connected with described the first conductive pole 11a by described opening 130.The material of described the first circuit layer 14 is such as being copper, nickel, gold, silver or aluminium etc., but is not limited to this.
In the present embodiment, similar, the material of described the second dielectric layer 10b can be dielectric resin material equally, for example glass layer is through containing made B rank film after epoxy resin dipping and the dry sclerosis, it utilizes its run gum and gummosis characteristic in HTHP, be pressed together on described the first circuit layer 14 and the first dielectric layer 10a, then again be heating and curing and obtain described the second dielectric layer 10b, the height of described the second dielectric layer 10b is approximately identical to described the first dielectric layer 10a, but is not limited to this.
In the present embodiment, described at least one the second conductive pole 11b is formed in described the second dielectric layer 10b, and is electrically connected with described the first circuit layer 14.Described the second conductive pole 11b is formed on described the first circuit layer 14 with the technique of electroplating collocation patterning photoresist in advance, covered by described the second dielectric layer 10b, but the end (top) of described the second conductive pole 11b expose outside described the second dielectric layer 10b.The height of described the second conductive pole 11b and diameter and described the first conductive pole 11a are roughly the same, but are not limited to this.The shape of the cross section of described the second conductive pole 11b is optional from circular, triangle or polygon etc., and its surface can be used as routing surface, plants ball surface or interlayer conduction;
Please refer to shown in Figure 2, it discloses the generalized section of another embodiment of the present invention base plate for packaging, the base plate for packaging 2 of Fig. 2 is basically similar in appearance to the base plate for packaging 1 of Fig. 1, but the base plate for packaging 2 of Fig. 2 is that the Seed Layer 13 ', the first circuit layer 14, the second conductive pole 11b and the second dielectric layer 10b that further form another group is on described the second dielectric layer 10b originally, increase a layer purpose in order to reach, for example can form base plate for packaging 2 structures with three layers or above circuit.
The base plate for packaging 1,2 of Fig. 1 of the present invention and Fig. 2 utilize described Seed Layer 13 ' be connected the position that conductive pole 11a connects and form an opening 130, and then so that the electric connection structure between described the first circuit layer 14 and the first conductive pole 11a is more reliable, and can guarantee the signal transmission effect of follow-up chip.
The present invention will be in hereinafter utilizing Fig. 3 A to 3G to describe in detail one by one, the manufacture method of one embodiment of the invention base plate for packaging 1, and it mainly comprises the following step:
At first, please refer to shown in Fig. 3 A, in a step (a), one first dielectric layer 10a is provided, has in advance at least one the first conductive pole 11a among described the first dielectric layer 10a, and the surface (such as lower surface) of described the first dielectric layer 10a is pre-formed a second circuit layer 12, herein, the formation method of described second circuit layer 12 and the first conductive pole 11a can be to form by the mode of a support plate with Copper Foil by Patternized technique and etching Copper Foil, certainly, also can directly form the first conductive pole 11a at described support plate with Copper Foil, remove afterwards support plate, namely form the structure that has in advance at least one the first conductive pole 11a among the described first dielectric layer 10a;
Then, please refer to shown in Fig. 3 B, in a step (b), in the upper Seed Layer 13 that forms of described the first dielectric layer 10a, then, in a step (c), I1 shines described Seed Layer 13 by laser (laser), makes described Seed Layer 13 corresponding described the first conductive pole 11a form at least one opening 130;
Afterwards, shown in Fig. 3 C, in a step (d), utilize the photoresist layer (photoresist) 15 of a patterning, electroplate formation one first circuit layer 14 in described Seed Layer 13, described the first circuit layer 14 is formed on Seed Layer 13 surfaces that described photoresist layer 15 exposes, and described the first circuit layer 14 is electrically connected with described the first conductive pole 11a by described opening 130;
Then, please refer to shown in Fig. 3 D, remove described photoresist layer 15;
Subsequently, shown in Fig. 3 E, in a step (d1), the photoresist layer 16 that recycles another patterning is electroplated on described the first circuit layer 14 and is formed to few one second conductive pole 11b;
Then, please refer to Fig. 3 F, remove described photoresist layer 16;
Afterwards, please refer to shown in Fig. 3 G, in a step (e), remove the described Seed Layer 13 that is not covered by described the first circuit layer 14 with suitable etching solution, with the Seed Layer 13 ' of formation patterning, that is only stay the Seed Layer 13 ' that is covered by described the first circuit layer 14; And
At last, please refer to shown in Figure 1ly, in a step (e1), form one second dielectric layer 10b and be covered on described the first dielectric layer 10a and described the first circuit layer 14, and coat described the second conductive pole 11b.So, the base plate for packaging 1 that can complete.Described step (e1) also can reach afterwards step (e) at described step (d1) and implement before.
Please refer to shown in Figure 2, the present invention also alternative step (b), (c) that repeats above-mentioned Fig. 3 B forms and anotherly has the Seed Layer 13 ' of opening 130 on described the second dielectric layer 10b, and the step (d)~(e1) that repeats ensuing Fig. 3 C to 3G and Fig. 1 is to reach the purpose that increases layer, so can form the base plate for packaging 2 with three layers or above circuit.
As mentioned above, the present invention utilizes base plate for packaging 1 and a manufacture method thereof, described Seed Layer 13 parts of removal between described the first circuit layer 14 and described the first conductive pole 11a, be subject to easily thermal expansion problem to avoid that the weak electrical structure of existing Seed Layer occurs, thereby destroy the reliability that is connected between circuit layer and the conductive pole, thereby the present invention can utilize the opening 130 of described Seed Layer 13 ' to solve smoothly the first circuit layer 14 of circuit substrate and the problem of the electric connection structure reliability between the first conductive pole 11a.
The present invention is described by above-mentioned related embodiment, yet above-described embodiment is only for implementing example of the present invention.Must be pointed out that published embodiment does not limit the scope of the invention.On the contrary, being contained in the spirit of claims and modification and impartial setting of scope is included in the scope of the present invention.

Claims (13)

1. base plate for packaging, it is characterized in that: described base plate for packaging comprises:
One first dielectric layer;
At least one the first conductive pole is formed in described the first dielectric layer;
One Seed Layer is covered in a upper surface of described the first dielectric layer, and corresponding described the first conductive pole forms at least one opening; And
One first circuit layer is formed on the described Seed Layer, and is electrically connected by described opening and described the first conductive pole, and described the first circuit layer and the corresponding spread configuration of described Seed Layer.
2. base plate for packaging as claimed in claim 1, it is characterized in that: the area of described opening is equal to or less than the cross-sectional area of described the first conductive pole.
3. base plate for packaging as claimed in claim 1, it is characterized in that: described opening is the laser burn opening.
4. base plate for packaging as claimed in claim 1, it is characterized in that: the thickness of described Seed Layer is equal to or less than 1 micron.
5. packaging structure as claimed in claim 1, it is characterized in that: described packaging structure comprises one second dielectric layer in addition, is covered on described the first dielectric layer and described the first circuit layer; And
At least one the second conductive pole is formed in the second dielectric layer, and is electrically connected with described the first circuit layer.
6. such as claim 1 or 5 described packaging structures, it is characterized in that: the height of described the first conductive pole and described the second conductive pole is between 20 to 100 microns.
7. such as claim 1 or 5 described base plate for packaging, the shape of the cross section of described the first conductive pole or described the second conductive pole is selected from circle, triangle or polygon.
8. packaging structure as claimed in claim 1, it is characterized in that: described packaging structure comprises a second circuit layer in addition, is formed at a lower surface of described the first dielectric layer, and is electrically connected with described the first conductive pole.
9. the manufacture method of a base plate for packaging, it is characterized in that: described manufacture method comprises following steps:
(a) provide one first dielectric layer, have at least one the first conductive pole in described the first dielectric layer;
(b) on described the first dielectric layer, form a Seed Layer;
(c) by Ear Mucosa Treated by He Ne Laser Irradiation, make corresponding described the first conductive pole in described the first sublayer form at least one opening;
(d) electroplate formation one first circuit layer in described Seed Layer, described the first circuit layer is electrically connected by described opening and described the first conductive pole; And
(e) remove the described Seed Layer that is not covered by described the first circuit layer, so that described Seed Layer and the corresponding spread configuration of described the first circuit layer.
10. the manufacture method of base plate for packaging as claimed in claim 9, it is characterized in that: in step (d) afterwards, other comprises:
(d1) on described the first circuit layer, form at least one the second conductive pole.
11. the manufacture method of base plate for packaging as claimed in claim 10 is characterized in that: in step (e) afterwards, other comprises:
(e1) form one second dielectric layer and be covered on the first dielectric layer and described the first circuit layer, and coat described the second conductive pole.
12. the manufacture method of base plate for packaging as claimed in claim 9 is characterized in that: the area of described opening is equal to or less than the cross-sectional area of described the first conductive pole.
13. the manufacture method of packaging structure as claimed in claim 9 is characterized in that: the thickness of described Seed Layer is equal to or less than 1 micron.
CN2012104583594A 2012-11-14 2012-11-14 Packaging substrate and manufacturing method thereof Pending CN102931168A (en)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105655303A (en) * 2014-12-03 2016-06-08 恒劲科技股份有限公司 Interposer substrate and manufacture method thereof
CN105720031A (en) * 2014-12-03 2016-06-29 恒劲科技股份有限公司 Interposer substrate and method of fabricating same

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101278396A (en) * 2005-10-07 2008-10-01 国际商业机器公司 Plating seed layer including an oxygen/nitrogen transition region for barrier enhancement
CN101702400A (en) * 2009-11-16 2010-05-05 威盛电子股份有限公司 Circuit substrate and technology thereof
US20100326709A1 (en) * 2009-06-30 2010-12-30 Ibiden Co., Ltd. Printed wiring board and method for manufacturing the same
CN102548254A (en) * 2010-12-30 2012-07-04 北大方正集团有限公司 Nuclear-free preparation method of chip carrier
CN202940225U (en) * 2012-11-14 2013-05-15 日月光半导体(上海)股份有限公司 Package substrate

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101278396A (en) * 2005-10-07 2008-10-01 国际商业机器公司 Plating seed layer including an oxygen/nitrogen transition region for barrier enhancement
US20100326709A1 (en) * 2009-06-30 2010-12-30 Ibiden Co., Ltd. Printed wiring board and method for manufacturing the same
CN101702400A (en) * 2009-11-16 2010-05-05 威盛电子股份有限公司 Circuit substrate and technology thereof
CN102548254A (en) * 2010-12-30 2012-07-04 北大方正集团有限公司 Nuclear-free preparation method of chip carrier
CN202940225U (en) * 2012-11-14 2013-05-15 日月光半导体(上海)股份有限公司 Package substrate

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105655303A (en) * 2014-12-03 2016-06-08 恒劲科技股份有限公司 Interposer substrate and manufacture method thereof
CN105720031A (en) * 2014-12-03 2016-06-29 恒劲科技股份有限公司 Interposer substrate and method of fabricating same

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