CN102543946B - 半导体器件封装及其制造方法 - Google Patents

半导体器件封装及其制造方法 Download PDF

Info

Publication number
CN102543946B
CN102543946B CN201110427046.8A CN201110427046A CN102543946B CN 102543946 B CN102543946 B CN 102543946B CN 201110427046 A CN201110427046 A CN 201110427046A CN 102543946 B CN102543946 B CN 102543946B
Authority
CN
China
Prior art keywords
semiconductor device
passivation layer
device package
dielectric
package
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201110427046.8A
Other languages
English (en)
Chinese (zh)
Other versions
CN102543946A (zh
Inventor
R·A·博普雷
P·A·麦康奈利
A·V·高达
T·B·戈尔茨卡
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
General Electric Co
Original Assignee
General Electric Co
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by General Electric Co filed Critical General Electric Co
Publication of CN102543946A publication Critical patent/CN102543946A/zh
Application granted granted Critical
Publication of CN102543946B publication Critical patent/CN102543946B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00Encapsulations, e.g. protective coatings
    • H10W74/10Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/131Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being only partially enclosed
    • H10W74/137Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being only partially enclosed the encapsulations being directly on the semiconductor body
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/117Shapes of semiconductor bodies
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/01Manufacture or treatment
    • H10W70/05Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers
    • H10W70/08Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers by depositing layers on the chip or wafer, e.g. "chip-first" RDLs
    • H10W70/09Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers by depositing layers on the chip or wafer, e.g. "chip-first" RDLs extending onto an encapsulation that laterally surrounds the chip or wafer, e.g. fan-out wafer level package [FOWLP] RDLs
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60Insulating or insulated package substrates; Interposers; Redistribution layers
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00Encapsulations, e.g. protective coatings
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00Encapsulations, e.g. protective coatings
    • H10W74/01Manufacture or treatment
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00Encapsulations, e.g. protective coatings
    • H10W74/10Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/131Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being only partially enclosed
    • H10W74/144Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being only partially enclosed the encapsulations comprising foils
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00Encapsulations, e.g. protective coatings
    • H10W74/10Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/131Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being only partially enclosed
    • H10W74/147Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being only partially enclosed the encapsulations being multilayered
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/01Manufacture or treatment
    • H10W70/05Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers
    • H10W70/093Connecting or disconnecting other interconnections thereto or therefrom, e.g. connecting bond wires or bumps
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/071Connecting or disconnecting
    • H10W72/0711Apparatus therefor
    • H10W72/07131Means for applying material, e.g. for deposition or forming coatings
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/071Connecting or disconnecting
    • H10W72/073Connecting or disconnecting of die-attach connectors
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00Package configurations

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Light Receiving Elements (AREA)
  • Semiconductor Integrated Circuits (AREA)
CN201110427046.8A 2010-12-08 2011-12-08 半导体器件封装及其制造方法 Active CN102543946B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US12/962,761 US8310040B2 (en) 2010-12-08 2010-12-08 Semiconductor device package having high breakdown voltage and low parasitic inductance and method of manufacturing thereof
US12/962761 2010-12-08

Publications (2)

Publication Number Publication Date
CN102543946A CN102543946A (zh) 2012-07-04
CN102543946B true CN102543946B (zh) 2016-12-07

Family

ID=45002829

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201110427046.8A Active CN102543946B (zh) 2010-12-08 2011-12-08 半导体器件封装及其制造方法

Country Status (8)

Country Link
US (2) US8310040B2 (https=)
EP (1) EP2463901B1 (https=)
JP (1) JP5926547B2 (https=)
KR (1) KR101944477B1 (https=)
CN (1) CN102543946B (https=)
PH (1) PH12011000403A1 (https=)
SG (1) SG182076A1 (https=)
TW (1) TWI544590B (https=)

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8431438B2 (en) * 2010-04-06 2013-04-30 Intel Corporation Forming in-situ micro-feature structures with coreless packages
US9209151B2 (en) 2013-09-26 2015-12-08 General Electric Company Embedded semiconductor device package and method of manufacturing thereof
US9806051B2 (en) 2014-03-04 2017-10-31 General Electric Company Ultra-thin embedded semiconductor device package and method of manufacturing thereof
WO2015174993A1 (en) * 2014-05-15 2015-11-19 Intel Corporation Molded composite enclosure for integrated circuit assembly
WO2015182581A1 (ja) * 2014-05-29 2015-12-03 アーゼット・エレクトロニック・マテリアルズ(ルクセンブルグ) ソシエテ・ア・レスポンサビリテ・リミテ 空隙形成用組成物、その組成物を用いて形成された空隙を具備した半導体装置、およびその組成物を用いた半導体装置の製造方法
EP3065164A1 (en) * 2015-03-04 2016-09-07 ABB Technology AG Power semiconductor arrangement and method of generating a power semiconductor arrangement
WO2020014499A1 (en) * 2018-07-13 2020-01-16 Array Photonics, Inc. Dual-depth via device and process for large back contact solar cells
DE102020135088A1 (de) * 2020-03-27 2021-09-30 Samsung Electronics Co., Ltd. Halbleitervorrichtung
US11699663B2 (en) 2020-04-27 2023-07-11 Taiwan Semiconductor Manufacturing Company, Ltd. Passivation scheme design for wafer singulation
CN113517205A (zh) * 2020-04-27 2021-10-19 台湾积体电路制造股份有限公司 半导体器件及其形成方法
CN115939222B (zh) * 2022-11-24 2025-10-17 湖南三安半导体有限责任公司 半导体器件及其制备方法
CN116936592A (zh) * 2023-07-24 2023-10-24 华天科技(昆山)电子有限公司 一种高可靠性的cis芯片封装结构及方法

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4198444A (en) * 1975-08-04 1980-04-15 General Electric Company Method for providing substantially hermetic sealing means for electronic components
US6329708B1 (en) * 1999-04-26 2001-12-11 Oki Electric Industry Co. Ltd. Micro ball grid array semiconductor device and semiconductor module

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4249299A (en) * 1979-03-05 1981-02-10 Hughes Aircraft Company Edge-around leads for backside connections to silicon circuit die
US5161093A (en) 1990-07-02 1992-11-03 General Electric Company Multiple lamination high density interconnect process and structure employing a variable crosslinking adhesive
DE69738783D1 (de) * 1996-10-08 2008-07-31 Hitachi Chemical Co Ltd Halbleiteranordnung, halbleiterchipträgersubstrat, herstellungsverfahren für anordnung und substrat, klebstoff und doppelseitiges haftklebeband
EP0926729A3 (en) * 1997-12-10 1999-12-08 Mitsubishi Gas Chemical Company, Inc. Semiconductor plastic package and process for the production thereof
US6239980B1 (en) 1998-08-31 2001-05-29 General Electric Company Multimodule interconnect structure and process
US6306680B1 (en) 1999-02-22 2001-10-23 General Electric Company Power overlay chip scale packages for discrete power devices
US6232151B1 (en) 1999-11-01 2001-05-15 General Electric Company Power electronic module packaging
JP4454814B2 (ja) * 2000-08-29 2010-04-21 Necエレクトロニクス株式会社 樹脂封止型半導体装置及びその製造方法
US7633765B1 (en) * 2004-03-23 2009-12-15 Amkor Technology, Inc. Semiconductor package including a top-surface metal layer for implementing circuit features
US7262444B2 (en) 2005-08-17 2007-08-28 General Electric Company Power semiconductor packaging method and structure
JP5033682B2 (ja) * 2008-03-12 2012-09-26 株式会社テラミクロス 半導体素子およびその製造方法並びに半導体装置およびその製造方法
CN102077341B (zh) * 2008-06-26 2014-04-23 Nxp股份有限公司 封装半导体产品及其制造方法
TW201101547A (en) * 2009-06-23 2011-01-01 Univ Kun Shan Packaging structure of light emitting diode

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4198444A (en) * 1975-08-04 1980-04-15 General Electric Company Method for providing substantially hermetic sealing means for electronic components
US6329708B1 (en) * 1999-04-26 2001-12-11 Oki Electric Industry Co. Ltd. Micro ball grid array semiconductor device and semiconductor module

Also Published As

Publication number Publication date
EP2463901B1 (en) 2018-06-13
TW201246475A (en) 2012-11-16
JP2012124486A (ja) 2012-06-28
US20120329207A1 (en) 2012-12-27
US8586421B2 (en) 2013-11-19
SG182076A1 (en) 2012-07-30
EP2463901A2 (en) 2012-06-13
US20120146234A1 (en) 2012-06-14
KR20120089993A (ko) 2012-08-16
CN102543946A (zh) 2012-07-04
US8310040B2 (en) 2012-11-13
PH12011000403A1 (en) 2014-07-23
TWI544590B (zh) 2016-08-01
JP5926547B2 (ja) 2016-05-25
EP2463901A3 (en) 2012-08-29
KR101944477B1 (ko) 2019-01-31

Similar Documents

Publication Publication Date Title
CN102543946B (zh) 半导体器件封装及其制造方法
JP6956234B2 (ja) ポリマー基板を有する半導体素子を備えるプリント回路モジュール、及びその製造方法
US10497648B2 (en) Embedded electronics package with multi-thickness interconnect structure and method of making same
TWI907971B (zh) 電子結構以及製造電子結構的方法
KR101173075B1 (ko) 집적 회로 디바이스를 패키징하는 방법 및 장치
JP7277056B2 (ja) 一体化された電磁干渉シールドを備えるエレクトロニクスパッケージおよびその製造方法
US12218098B2 (en) Chip assembling on adhesion layer or dielectric layer, extending beyond chip, on substrate
US10607929B2 (en) Electronics package having a self-aligning interconnect assembly and method of making same
US10312194B2 (en) Stacked electronics package and method of manufacturing thereof
US10804115B2 (en) Electronics package with integrated interconnect structure and method of manufacturing thereof
US7723213B2 (en) Manufacturing method of semiconductor chips and semiconductor device having the semiconductor chips
KR20110101068A (ko) 반도체 장치의 제조 방법 및 반도체 장치
US10700035B2 (en) Stacked electronics package and method of manufacturing thereof
KR20090029660A (ko) 반도체 장치의 제조 방법
US9966371B1 (en) Electronics package having a multi-thickness conductor layer and method of manufacturing thereof
US7906833B2 (en) Semiconductor device and manufacturing method thereof
CN103280438B (zh) 具有准确芯片附着层的大功率介电载体
CN111883480B (zh) 一种芯片互连方法

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant