CN102496666A - Semiconductor device and manufacturing method for gallium nitride epitaxial layer of semiconductor device - Google Patents
Semiconductor device and manufacturing method for gallium nitride epitaxial layer of semiconductor device Download PDFInfo
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Abstract
An embodiment of the invention discloses a manufacturing method for a gallium nitride epitaxial layer. The method includes that firstly, a base is provided and comprises a silicon substrate of a (100) system crystal face and an etching barrier layer on the surface of the silicon substrate; secondly, a groove pattern window is formed on the surface of the etching barrier layer, and the edge of the groove pattern window is parallel to the (100) system crystal orientation of the silicon substrate; thirdly, a groove is formed on the surface of the silicon surface with the etching barrier layer having the groove pattern window as a cover film, the lateral sides of the groove are (111) crystal faces of the silicon substrate, and two opposite (111) crystal faces of the groove are interested to form a groove bottom; and fourthly, a GaN epitaxial layer is formed on the surface of the silicon substrate with the groove. Dislocation density of the gallium nitride (GaN) epitaxial layer growing on the silicon (Si) substrate can be reduced by one to two orders of magnitude, and quality of the gallium nitride (GaN) epitaxial layer obtained on the silicon (Si) substrate can be improved.
Description
Technical field
The present invention relates to semi-conducting material technology and technical field of semiconductor illumination, relate in particular to a kind of semiconductor device and epitaxy of gallium nitride layer manufacturing method thereof thereof.
Background technology
Along with the rise of energy-conserving and environment-protective notion in the world wide, the nitride LED epitaxy technology that is applied to white light LEDs obtained fast development in recent years, made the luminous efficiency of nitride semiconductor LED chip improve very fast.Wherein, reached more than 130 lumens/watt,, indicated that the LED technology has begun to get into general illumination market comprehensively considerably beyond the light efficiency of common energy-saving lamp with the white light LEDs list lamp source efficient of gallium nitride based LED chip as lasing light emitter.
But with sapphire, carborundum (SiC) is that the cost of the gallium nitride based LED made of substrate is high, and this mainly is the reason from two aspects: be because the costing an arm and a leg of sapphire, carborundum (SiC) substrate itself on the one hand; Be owing to make comparatively difficulty of large scale, high-quality sapphire, carborundum (SiC) substrate on the other hand.At present, 4 " Sapphire Substrate has just begun to get into commercial, and is not only of a high price but also performance is very unstable.And silicon (Si) substrate has cost commercialization substrate and silicon-based devices low, that be prone to cleavage, the large-area high-quality that is easy to get and is easy to advantages such as integrated; Therefore, People more and more turns to technology maturation, with low cost, the simple and good silicon substrate of heat dissipation characteristics of processing with attentiveness.
Yet; There are the bigger lattice mismatch and the problem of thermal mismatching between silicon (Si) substrate and the gallium nitride (GaN); Wherein, the lattice mismatch degree between silicon (Si) substrate and the gallium nitride (GaN) is up to 20.4%, and the thermal mismatching degree is especially up to 56%; Make that the dislocation density of gallium nitride (GaN) the material epitaxy layer of on silicon (Si) substrate, growing is higher, obtain high-quality gallium nitride (GaN) material epitaxy layer on the silicon (Si) thereby cause being difficult in.
Summary of the invention
For solving the problems of the technologies described above; The embodiment of the invention provides a kind of semiconductor device and epitaxy of gallium nitride layer manufacturing method thereof thereof; Can be reduced in the dislocation density of gallium nitride (GaN) the material epitaxy layer of growing on silicon (Si) substrate; The quality of gallium nitride (GaN) the material epitaxy layer that raising obtains on silicon (Si) makes that the Grown GaN material devices obtains higher performance on the Si substrate.
For addressing the above problem, the embodiment of the invention provides following technical scheme:
A kind of epitaxy of gallium nitride layer manufacturing method thereof, this method comprises: substrate is provided, and said substrate comprises that (100) are the silicon substrate of crystal face and are positioned at the etching barrier layer on the said surface of silicon; In said etching barrier layer surface, form the groove figure window, < 110>that said groove figure window edge is parallel to said silicon substrate are the crystal orientation; With the etching barrier layer with groove figure window is mask, in said surface of silicon, forms groove, and said groove side surface is that (111) of said silicon substrate are crystal face, and two (111) that said groove is relative are that crystal face intersects, and form trench bottom surfaces; Has formation GaN epitaxial loayer on the surface of silicon of said groove.
Preferably; The concrete mode that in said surface of silicon, forms groove is: with the etching barrier layer with groove figure window is mask; The employing wet corrosion technique is removed the silicon substrate material that the barrier layer that is not etched covers; In surface of silicon, forming said groove, the corrosive liquid that said wet corrosion technique adopts is that (111) of the silicon substrate of crystal face are that the corrosion rate of crystal face is less than the corrosion rate that is crystal face to said silicon substrate non-(111) to (100).
Preferably, said corrosive liquid is LiOH solution, NaOH solution or KOH solution.
Preferably, the mass fraction of said LiOH solution is in 5%～30% scope; The mass fraction of said NaOH solution is in 20%～40% scope; The mass fraction of said KOH solution is in 10%～60% scope.
Preferably, the temperature of said wet corrosion technique is in 80 ℃～350 ℃ scopes.
Preferably, the degree of depth of said groove is in the scope of 200nm～1200nm.
Preferably, said groove figure window is shaped as bar shaped or square; The width of said groove figure window is in the scope of 400nm～2400nm; Distance between said groove figure window is in 5 μ m～20 mu m ranges.
Preferably, the thickness of said etching barrier layer is in 50nm～300nm scope.
Preferably, the generation type of said GaN epitaxial loayer is specially: on the surface of silicon of said groove, form the AlN resilient coating; On the surface of said AlN resilient coating, form low temperature GaN layer, said low temperature GaN layer upper surface flushes with said etching barrier layer surface basically; On said low temperature GaN laminar surface, form high temperature GaN layer, said high temperature GaN layer covers said etching barrier layer upper surface fully.
Temperature when preferably, said AlN resilient coating forms is controlled in 800 ℃～900 ℃ scopes; The thickness of said AlN resilient coating is in 20nm～80nm scope.
Temperature when preferably, said low temperature GaN layer forms is controlled at the lower temperature between 980 ℃～1150 ℃; Temperature when said high temperature GaN layer forms is controlled at the higher temperature between 980 ℃～1150 ℃.
Chamber when preferably, said AlN resilient coating, said low temperature GaN layer and said high temperature GaN layer form is pressed and all is controlled in 100torr～600torr scope.
The present invention also provides a kind of semiconductor device, and this semiconductor device comprises: (100) are the silicon substrate of crystal face; Be positioned at the etching barrier layer on the said surface of silicon, said etching barrier layer has the groove figure window in the surface, and < 110>that said groove figure window edge is parallel to said silicon substrate are the crystal orientation; Do not had groove in the surface of silicon that is covered by said etching barrier layer, said groove side surface is that (111) of said silicon substrate are crystal face, and said trench bottom surfaces is that crystal face intersects and forms by relative two (111); Has the GaN epitaxial loayer on the surface of silicon of said groove having.
Compared with prior art, technique scheme has the following advantages:
The epitaxy of gallium nitride layer manufacturing method thereof that the embodiment of the invention provided; < 110>that are parallel to said silicon substrate through formation edge in said etching barrier layer surface are the groove figure window in crystal orientation; Be beneficial in said surface of silicon, form and have the groove that (111) are crystal face; Be mask with etching barrier layer again with groove figure window; Two sides of formation are said silicon substrate in said surface of silicon (111) are the groove of crystal face, have formation GaN epitaxial loayer on the surface of silicon of said groove then.
Distribute the most alike because (111) of the Si substrate that exposes to the open air out in the said groove are the lattice of crystal face and GaN; Therefore; The GaN epitaxial loayer that the method that utilizing among the present invention is provided is made; Can weaken the adverse effect because of existing higher lattice mismatch and thermal mismatching to bring between silicon (Si) substrate and the gallium nitride (GaN); Thereby the dislocation density of gallium nitride (GaN) the material epitaxy layer that will on silicon (Si) substrate, grow reduces by 1～2 one magnitude; The quality of gallium nitride (GaN) epitaxial loayer that raising obtains on silicon (Si), and then make that the Grown GaN device obtains higher performance on the Si substrate, further promoted with silicon (Si) to be the practicability and the commercialization of the GaN material of substrate.
Description of drawings
In order to be illustrated more clearly in the embodiment of the invention or technical scheme of the prior art; To do to introduce simply to the accompanying drawing of required use in embodiment or the description of the Prior Art below; Obviously, the accompanying drawing in describing below only is some embodiments of the present invention, for those of ordinary skills; Under the prerequisite of not paying creative work, can also obtain other accompanying drawing according to these accompanying drawings.
Fig. 1 is the flow chart of epitaxy of gallium nitride layer manufacturing method thereof provided by the present invention;
Fig. 2 is the structural representation after on (100) are the Si substrate of crystal face, forming etching barrier layer in the method provided by the present invention;
Fig. 3 is the structural representation after forming groove on the Si substrate in the method provided by the present invention;
Fig. 4 is the structural representation that in groove, forms in the method provided by the present invention behind the AlN resilient coating;
Fig. 5 is the structural representation after forming low temperature GaN layer on the AlN resilient coating in the method provided by the present invention;
Fig. 6 is the structural representation after forming high temperature GaN layer on the low temperature GaN layer in the method provided by the present invention.
Fig. 1～Fig. 6 shows: 1--(100) is a crystal face Si substrate; The 2--etching barrier layer; 3--groove figure window; The 4--groove; (111) of 5--Si substrate are crystal face; The 6--AlN resilient coating; 7--low temperature GaN layer; 8--high temperature GaN layer.
Embodiment
To combine the accompanying drawing in the embodiment of the invention below, the technical scheme in the embodiment of the invention is carried out clear, intactly description, obviously, described embodiment only is the present invention's part embodiment, rather than whole embodiment.Based on the embodiment among the present invention, those of ordinary skills are not making the every other embodiment that is obtained under the creative work prerequisite, all belong to the scope of the present invention's protection.
A lot of details have been set forth in the following description so that make much of the present invention; But the present invention can also adopt other to be different from alternate manner described here and implement; Those skilled in the art can do similar popularization under the situation of intension of the present invention, so the present invention does not receive the restriction of following disclosed specific embodiment.
Secondly, the present invention combines sketch map to be described in detail, when the embodiment of the invention is detailed; For ease of explanation; The profile of expression device architecture can be disobeyed general ratio and done local the amplification, and said sketch map is example, and it should not limit the scope of the present invention's protection at this.The three dimensions size that in actual fabrication, should comprise in addition, length, width and the degree of depth.
Said as the background technology part; Owing to have bigger lattice mismatch and thermal mismatch problem between silicon (Si) substrate and the gallium nitride (GaN); Thereby make that the dislocation density of gallium nitride (GaN) the material epitaxy layer of on silicon (Si) substrate, growing is higher, cause being difficult in and obtain high-quality gallium nitride (GaN) material epitaxy layer on the silicon (Si).
In view of this, the embodiment of the invention provides a kind of epitaxy of gallium nitride layer manufacturing method thereof, below in conjunction with accompanying drawing this method is specifically described.
Embodiment one:
As shown in Figure 1, provide the epitaxy of gallium nitride layer manufacturing method thereof may further comprise the steps in the embodiment of the invention:
Step S101: substrate is provided, and said substrate comprises that (100) are the silicon substrate 1 of crystal face and are positioned at the etching barrier layer 2 on the said surface of silicon.
Can adopt technologies such as thermal oxidation or deposit in the embodiment of the invention; Formation etching barrier layer 2 is gone up on silicon substrate 1 surface in that said (100) are crystal face; Usually the temperature of thermal oxidation is between 750 ℃～1100 ℃; The etching barrier layer 2 of heat growth can tightly be attached on the said silicon substrate, and has good dielectric property.In embodiments of the present invention, the material of said etching barrier layer 2 is for being SiO
2, as shown in Figure 2, Fig. 2 shows in the method provided by the present invention structural representation after on (100) are the Si substrate of crystal face, forming etching barrier layer, and the thickness of wherein said etching barrier layer 2 is in 50nm～300nm scope.
In addition; Because the structure of crystal is the zincblende lattce structure of cube phase; Therefore; (100) described in the present invention are that crystal face comprises the crystal face of crystal orientation along < 001>< 00-1>< 010>< 0-10>< 100>crystal orientation such as < 100 >, and corresponding crystal face is crystal face Si substrate as the Si substrate of substrate surface for (100), and corresponding crystal orientation is the crystal orientation for < 100 >.
Step S102: in said etching barrier layer 2 surfaces, form the groove figure window, < 110>that said groove figure window edge is parallel to said silicon substrate are the crystal orientation.
After said etching barrier layer 2 formed, spin coating photoresist layer on said etching barrier layer 2 in order to guarantee exposure accuracy, also can form the anti-reflecting layer (not shown), to reduce unnecessary reflection between photoresist layer and said etching barrier layer 2; Adopt mask that photoresist layer is made public afterwards with groove figure; On said photoresist layer surface, form channel patterns; Be mask with photoresist layer afterwards with channel patterns; Adopt technologies such as reactive ion etching, said etching barrier layer 2 in, forming < 110>that the edge is parallel to said silicon substrate is crystal orientation groove figure window 3, adopts method removal photoresist layer and anti-reflecting layers such as chemical cleaning afterwards.
Can adopt BOE, HF wet etching or RIE CF in the embodiment of the invention
4Technologies such as dry plasma etching are carried out etching to said etching barrier layer 2; Thereby the groove figure window 3 that in said etching barrier layer 2, obtains expecting; The shape of said groove figure window 3 can be bar shaped or square; The present invention does not limit this, as long as the edge direction of said groove figure window 3 is parallel to said Si substrate<110>Be that the crystal orientation gets final product; The width a of the etching barrier layer 2 of said groove figure window 3 hollow heart eating aways is in the scope of 400nm～2400nm, and the distance b of the etching barrier layer that is not corroded between adjacent trenches graphical window is in 5 μ m～20 mu m ranges.
In like manner; < 110>in this step are that the crystal orientation comprises < 110>< 1-10>< 1-10>< 110>< 0-11>< 01-1>< 101>< 10-1>< 011>< 0-1-1>< 101>crystal orientation such as < 10-1 >; The pairing crystal face in these crystal orientation is a crystal face for (110), and corresponding crystal face is crystal face Si substrate as the Si substrate of substrate surface for (110).
Step S103: the etching barrier layer 2 to have groove figure window 3 is a mask; In said surface of silicon, form groove 4; Said groove 4 sides are that (111) of said silicon substrate are crystal face 5, and said groove 4 two relative (111) are that crystal face intersects, and form trench bottom surfaces.
The concrete mode that in said surface of silicon, forms groove 4 is: the etching barrier layer 2 to have groove figure window 3 is a mask; Adopt wet corrosion technique to remove the silicon substrate material that is not covered by said etching barrier layer 2; In surface of silicon, to form said groove 4; Wherein, said groove 4 two relative (111) are that crystal face intersects, and form trench bottom surfaces.Because among the present invention will be that crystal face 5 exposes to the open air out with (111) in the said silicon substrate; Therefore; Selected corrosive liquid is LiOH solution, NaOH solution or KOH solution in the embodiment of the invention, be preferably KOH solution, and the concentration proportioning of different corrosive liquids is different; Wherein, the mass fraction of said LiOH solution is in 5%～30% scope; The mass fraction of said NaOH solution is in 20%～40% scope; The mass fraction of said KOH solution is in 10%～60% scope.
In addition, said corrosive liquid can also be selected CsOH solution, NH
4OH solution, TMAH solution, EDP solution, N (CH
3)
4OH solution, (CH
3)
3N (CH
2CH
2OH) OH solution, the mixed solution of KOH and isopropyl alcohol, the mixed solution of NaOH and isopropyl alcohol, H
2O and NH
2(CH
2)
2NH
2Mixed solution, N
2H
4, H
2The mixed solution of O and iso-2-propyl alcohol, N
2H
4With H
2The O mixed solution, N
2H
4, H
2O and C
6H
4(OH)
2Corrosive liquids such as mixed solution, the present invention does not do qualification to this, as long as the corrosion rate that said corrosive liquid is the corrosion rate of crystal face 5 to said silicon substrate (111) is crystal face less than said corrosive liquid to said silicon substrate non-(111).
The silicon substrate (111) that in to said groove figure window 3, exposes to the open air out is that crystal face 5 corrodes, and until in said (100) are crystal face Si substrate 1, forming in the process of groove 4, the temperature of said wet corrosion technique is in 80 ℃～350 ℃ scopes.And because the crystal orientation of said groove 4 interior silicon substrate crystal faces is definite; Can confirm the degree of depth of said groove 4 according to the width a of groove figure window 3 described in the step S102; As shown in Figure 3, the degree of depth of utilizing the said groove 4 that the method in the embodiment of the invention obtains is in 200nm～1200nm scope.
With identical in above-mentioned two steps; (111) described in this step are that crystal face comprises the crystal face of crystal orientation along < 111>< 11-1>< 11-1>< 111>< 1-11>< 1-1-1>< 1-1-1>crystal orientation such as < 1-11 >; Its corresponding crystal face is crystal face Si substrate as the Si substrate of substrate surface for (111), and corresponding crystal orientation is the crystal orientation for < 111 >.And the crystal face that other non-< 111>are the crystal orientation is referred to as to non-(111) is crystal face; Corresponding crystal face is that non-(111) are crystal face Si substrate as the Si substrate of substrate surface, comprising (100) described in the step S101 be crystal face the Si substrate and step S102 described in (110) be brilliant Si substrate.
Step S104: on surface of silicon, form the GaN epitaxial loayer with said groove 4.
Because it is the most alike with the lattice distribution of GaN that (111) of the Si substrate in the said groove 4 are crystal face 5; Therefore can be on the surface of silicon in the said groove 4 selective growth GaN epitaxial loayer; Promptly in said groove 4, has nucleating growth on the Si substrate surface 5 that (111) are the crystal orientation, nucleating growth not on said etching barrier layer 2.This selectivity is that temperature and the chamber during through control GaN outer layer growth pressed and realized.Therefore, the generation type of the epitaxial loayer of GaN described in the present invention specifically is divided into following three steps again:
Step S104a: on the surface of silicon of said groove 4, form AlN resilient coating 6.
The Si substrate (111) that method through selective epitaxy can expose to the open air out in said groove 4 is a selective growth AlN resilient coating 6 on the surface of crystal face 5.This selectivity can be through AlN resilient coating 6 growth temperature and growth the time factors such as chamber pressure control; The growth temperature of the resilient coating of AlN described in the embodiment of the invention 6 is controlled in 800 degree～900 degree scopes, and the chamber pressure-controlled during growth is in 100torr～600torr scope.With reference to figure 4, Fig. 4 is the structural representation that in groove, forms in the method provided by the present invention behind the AlN resilient coating, and the thickness of said AlN resilient coating 6 is in 20nm～80nm scope.
Said AlN resilient coating in the embodiment of the invention not only can be alleviated lattice mismatch and the thermal mismatching degree between silicon (Si) substrate and the gallium nitride (GaN); Thereby the dislocation density when reducing said gallium nitride (GaN) outer layer growth; When high temperature, react with gallium nitride (GaN) but also can completely cut off silicon substrate (Si), avoid silicon substrate (Si) and gallium nitride (GaN) epitaxial loayer to be corroded.
Step S104b: on the surface of said AlN resilient coating 6, form low temperature GaN layer 7, said low temperature GaN layer 7 upper surface flush with said etching barrier layer 2 surfaces basically.
After said AlN resilient coating 6 growths are accomplished, selective growth low temperature GaN layer 7 on said AlN resilient coating 6 surfaces.Temperature during 7 growth of the GaN of low temperature described in embodiment of the invention layer is controlled at the lower temperature between 980 ℃～1150 ℃, and the chamber pressure-controlled during growth is in 100torr～600torr scope.
As shown in Figure 5, Fig. 5 is the structural representation after forming low temperature GaN layer on the AlN buffer-layer surface in the method provided by the present invention, as can be seen from the figure, flushes basically with said etching barrier layer 2 surfaces after said low temperature GaN layer 7 growth are accomplished.When said low temperature GaN layer 7 is specifically grown; Can control the filling extent of said low temperature GaN layer 7 through the time dependent curve of reflectivity on the said low temperature GaN of real-time monitoring layer 7 surface; When the time dependent curve of said reflectivity reaches a stage high position and begins to even up slightly, stop the growth of said low temperature GaN layer 7.The growth time of the GaN of low temperature described in embodiment of the invention layer 7 is in 7min～35min scope, and the concrete time is different because of the degree of depth of said groove 4.
Step S104c: on said low temperature GaN layer 7 surface, form high temperature GaN layer 8, said high temperature GaN layer 8 covers said etching barrier layer 2 surfaces fully.
After 7 growth of said low temperature GaN layer are accomplished, on said low temperature GaN layer 7 through the method for transversal epitaxial growth, the high temperature GaN layer 8 of growing continuously.Temperature during 8 growth of the GaN of high temperature described in embodiment of the invention layer is controlled at the higher temperature between 980 ℃～1150 ℃; Chamber during growth is pressed and still is controlled in 100torr～600torr scope, and the growth of said high temperature GaN layer 8 is up to accomplishing at ordinary times in said SiO2 mask 2 surface aggregates length.As shown in Figure 6, Fig. 6 is the structural representation after forming high temperature GaN layer on the low temperature GaN layer in the method provided by the present invention, and as can be seen from Figure 6, said high temperature GaN layer 8 covers said etching barrier layer 2 surfaces fully.
The epitaxy of gallium nitride layer manufacturing method thereof that the embodiment of the invention provided; According to (111) of Si substrate is that the lattice of crystal face and GaN distributes the most alike; The Si substrate and the surperficial etching barrier layer thereof that are crystal face to said (100) carry out etching; Formation has the groove that (111) are crystal face, thereby is that crystal face exposes to the open air out with (111) on the said Si substrate, and (111) at the Si substrate that exposes to the open air out are that order forms AlN resilient coating, low temperature GaN layer and high temperature GaN layer on the crystal face then; Thereby weakened to a certain extent between silicon (Si) substrate and the gallium nitride (GaN); Because of the adverse effect that exists higher lattice mismatch and thermal mismatching degree to bring, thereby the dislocation density of gallium nitride (GaN) the material epitaxy layer that will on silicon (Si) substrate, grow has reduced by 1～2 one magnitude, has improved the quality of gallium nitride (GaN) the material epitaxy layer that on silicon (Si), obtains; Make that finally the Grown GaN material devices obtains higher performance on the Si substrate; Reduced the cost of GaN material, promoted the reliability of GaN material devices simultaneously, further promoted with silicon (Si) to be the practicability and the commercialization of gallium nitride (GaN) material of substrate.
Embodiment two:
With a specific embodiment method provided by the present invention is described below.
Step 201: substrate is provided, goes up Using P ECVD on Si substrate 1 surface of (100) crystal face and under 350 degree, form continuous SiO
2 Etching barrier layer 2, as shown in Figure 2, said SiO
2The thickness of etching barrier layer 2 is 200nm.
Step 202: be etched in said SiO through photoetching and BOE
2Forming the edge in the etching barrier layer 2 is parallel on the said Si substrate<011>The strip groove graphical window 3 in crystal orientation, wherein, the width a of said groove figure window 3 is 1200nm, the distance b between adjacent trenches graphical window is 10 μ m.
Step 203: to have the SiO of groove figure window 3
2 Etching barrier layer 2 is a mask, uses KOH corrosive liquid Si substrate in the said groove figure window 3 of corrosion under 115 degree, in said Si substrate, forms to have the groove 4 that (111) are crystal face; With (111) in the said silicon substrate is that crystal face 5 exposes to the open air out, and wherein, said groove 4 sides are that (111) of said silicon substrate are crystal face; Said groove 4 two relative (111) are that crystal face intersects; Form trench bottom surfaces, as shown in Figure 3, the degree of depth of groove described in the present embodiment 4 is 600nm.
Step 204: on surface of silicon, form the GaN epitaxial loayer with said groove 4.
The generation type of said GaN epitaxial loayer is specially:
Step S204a: on the surface of silicon of said groove 4, form AlN resilient coating 6.
(111) of the Si substrate that the method through selective epitaxy can expose to the open air out in said groove figure window 3 are selective growth AlN resilient coating 6 on the crystal face 5; During concrete the growth; The growth temperature of said AlN resilient coating 6 is 850 ℃, and the chamber is pressed and is 500torr, and the AlN resilient coating 6 after growth is accomplished is as shown in Figure 4; The resilient coating of AlN described in the embodiment of the invention 6 growth times are 3min, and thickness is 50nm.
Step 204b: on the surface of said AlN resilient coating, form low temperature GaN layer, said low temperature GaN layer upper surface flushes with said etching barrier layer surface basically.
The growth temperature of the GaN of low temperature described in embodiment of the invention layer 7 is 1000 degree; The chamber is pressed and is 500torr; And control the filling extent of said low temperature GaN layer 7 through the time dependent curves of reflectivity on the said low temperature GaN of real-time monitoring layer 7 surface, to reach the stage high-order and when beginning to even up slightly when the time dependent curve of said reflectivity, stops the growth of said low temperature GaN layer 7; The growth time of said low temperature GaN layer 7 is 15min; As shown in Figure 5, after growth was accomplished, said low temperature GaN layer upper surface flushed with said etching barrier layer surface basically.
Step 204c: on said low temperature GaN laminar surface 7, form high temperature GaN layer 8, said high temperature GaN layer 8 covers said etching barrier layer upper surface fully.
On said low temperature GaN layer 7 through transversal epitaxial growth method at the continuous growth high temperature GaN layer 8 of 1060 degree, it still is 500torr that growth chamber is pressed, the growth of said high temperature GaN layer 8 is up at said SiO
2 Etching barrier layer 2 surface aggregates are long to be accomplished at ordinary times, and as shown in Figure 6, said high temperature GaN layer 8 covers said etching barrier layer upper surface fully.
Utilizing the dislocation density of method Grown GaN epitaxial loayer on the Si substrate that the embodiment of the invention provides is 10
8Magnitude.And method provided by the present invention is through in (100) being erosion grooves on the Si substrate of crystal face; Thereby in said groove, be that crystal face exposes to the open air out with (111) on the Si substrate; Be the GaN epitaxial loayer that the method for order growing AIN resilient coating, low temperature GaN layer and high temperature GaN layer on the crystal face obtains in (111) of the Si substrate that exposes to the open air out then; Because the growth pattern of low temperature GaN layer and high temperature GaN layer is to be set out by trench region; To around grow; Be that the direction of growth has been included groove top and the etching barrier layer zone that is positioned at around the groove, so the inner stress of epitaxial loayer can be to more multi-direction release, and be order growing AIN resilient coating, low temperature GaN layer and high temperature GaN layer on the Si substrate of crystal face directly in (111); Because in growth course; The inner Stress Release direction of epitaxial loayer is limited, so the Stress Release effect of the GaN epitaxial loayer that obtains of the method in the present embodiment is the Stress Release better effects if of the Si substrate Grown GaN epitaxial loayer of crystal face in (111) more directly, and the GaN material property of acquisition is also better.
Embodiment three:
Method provided by the present invention can be widely used in epitaxial growth and the making that gallium nitride (GaN) semiconductor device comprises gallium nitride light-emitting diode (GaN LED) and gallium nitride (GaN) semi-conductor electricity device, promptly can also continued growth make semiconductor device structures such as high quality GaN LED, laser, detector and power diode on the high temperature GaN layer described in the embodiment of the invention.Therefore, the embodiment of the invention also provides a kind of semiconductor device, and this semiconductor device comprises:
(100) be the silicon substrate of crystal face;
Be positioned at the etching barrier layer on the said surface of silicon, said etching barrier layer has the groove figure window in the surface, and < 110>that said groove figure window edge is parallel to said silicon substrate are the crystal orientation;
Do not had groove in the surface of silicon that is covered by said etching barrier layer, said groove side surface is that (111) of said silicon substrate are crystal face, and said trench bottom surfaces is that crystal face intersects and forms by relative two (111);
Has the GaN epitaxial loayer on the surface of silicon of said groove having.
In addition, to different semiconductor device type, on the GaN of above-mentioned formation epitaxial loayer, can also comprise corresponding semiconductor device structure.
The semiconductor device that the embodiment of the invention provided has higher performance, and lower cost has promoted the reliability of this semiconductor device simultaneously, has further promoted with silicon (Si) to be the development of gallium nitride (GaN) material semiconductor device of substrate.
Above-described " in the substrate surface " is meant that this zone belongs to the part of substrate by the zone of substrate surface to the certain depth that extends below; Said " on the substrate surface " is meant the zone that is made progress by substrate surface, and this zone does not belong to substrate itself.
Various piece adopts the mode of going forward one by one to describe in this specification, and what each part stressed all is and the difference of other parts that identical similar part is mutually referring to getting final product between the various piece.
To the above-mentioned explanation of the disclosed embodiments, make this area professional and technical personnel can realize or use the present invention.Multiple modification to these embodiment will be conspicuous concerning those skilled in the art, and defined General Principle can realize under the situation that does not break away from the spirit or scope of the present invention in other embodiments among this paper.Therefore, the present invention will can not be restricted to embodiment illustrated herein, but will meet and principle disclosed herein and features of novelty the wideest corresponding to scope.
Claims (13)
1. an epitaxy of gallium nitride layer manufacturing method thereof is characterized in that, this method comprises:
Substrate is provided, and said substrate comprises that (100) are the silicon substrate of crystal face and are positioned at the etching barrier layer on the said surface of silicon;
In said etching barrier layer surface, form the groove figure window, < 110>that said groove figure window edge is parallel to said silicon substrate are the crystal orientation;
With the etching barrier layer with groove figure window is mask, in said surface of silicon, forms groove, and said groove side surface is that (111) of said silicon substrate are crystal face, and two (111) that said groove is relative are that crystal face intersects, and form trench bottom surfaces;
Has formation GaN epitaxial loayer on the surface of silicon of said groove.
2. method according to claim 1 is characterized in that, the concrete mode that in said surface of silicon, forms groove is:
With the etching barrier layer with groove figure window is mask; The employing wet corrosion technique is removed the silicon substrate material that the barrier layer that is not etched covers; In surface of silicon, forming said groove, the corrosive liquid that said wet corrosion technique adopts is that (111) of the silicon substrate of crystal face are that the corrosion rate of crystal face is less than the corrosion rate that is crystal face to said silicon substrate non-(111) to (100).
3. method according to claim 2 is characterized in that, said corrosive liquid is LiOH solution, NaOH solution or KOH solution.
4. method according to claim 3 is characterized in that the mass fraction of said LiOH solution is in 5%～30% scope; The mass fraction of said NaOH solution is in 20%～40% scope; The mass fraction of said KOH solution is in 10%～60% scope.
5. method according to claim 2 is characterized in that, the temperature of said wet corrosion technique is in 80 ℃～350 ℃ scopes.
6. method according to claim 2 is characterized in that the degree of depth of said groove is in the scope of 200nm～1200nm.
7. method according to claim 1 is characterized in that, said groove figure window be shaped as bar shaped or square; The width of said groove figure window is in the scope of 400nm～2400nm; Distance between said groove figure window is in 5 μ m～20 mu m ranges.
8. method according to claim 1 is characterized in that, the thickness of said etching barrier layer is in 50nm～300nm scope.
9. method according to claim 1 is characterized in that, the generation type of said GaN epitaxial loayer is specially:
On the surface of silicon of said groove, form the AlN resilient coating;
On the surface of said AlN resilient coating, form low temperature GaN layer, said low temperature GaN layer upper surface flushes with said etching barrier layer surface basically;
On said low temperature GaN laminar surface, form high temperature GaN layer, said high temperature GaN layer covers said etching barrier layer upper surface fully.
10. method according to claim 9 is characterized in that, the temperature when said AlN resilient coating forms is controlled in 800 ℃～900 ℃ scopes; The thickness of said AlN resilient coating is in 20nm～80nm scope.
11. method according to claim 9 is characterized in that, the temperature when said low temperature GaN layer forms is controlled at the lower temperature between 980 ℃～1150 ℃; Temperature when said high temperature GaN layer forms is controlled at the higher temperature between 980 ℃～1150 ℃.
12. method according to claim 9 is characterized in that, the chamber when said AlN resilient coating, said low temperature GaN layer and said high temperature GaN layer form is pressed and all is controlled in 100torr～600torr scope.
13. a semiconductor device is characterized in that, this semiconductor device comprises:
(100) be the silicon substrate of crystal face;
Be positioned at the etching barrier layer on the said surface of silicon, said etching barrier layer has the groove figure window in the surface, and < 110>that said groove figure window edge is parallel to said silicon substrate are the crystal orientation;
Do not had groove in the surface of silicon that is covered by said etching barrier layer, said groove side surface is that (111) of said silicon substrate are crystal face, and said trench bottom surfaces is that crystal face intersects and forms by relative two (111);
Has the GaN epitaxial loayer on the surface of silicon of said groove having.
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