CN102496618A - Pixel structure and manufacturing method thereof - Google Patents
Pixel structure and manufacturing method thereof Download PDFInfo
- Publication number
- CN102496618A CN102496618A CN2011103998302A CN201110399830A CN102496618A CN 102496618 A CN102496618 A CN 102496618A CN 2011103998302 A CN2011103998302 A CN 2011103998302A CN 201110399830 A CN201110399830 A CN 201110399830A CN 102496618 A CN102496618 A CN 102496618A
- Authority
- CN
- China
- Prior art keywords
- layer
- patterning photoresist
- photoresist layer
- data wire
- electrode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Landscapes
- Thin Film Transistor (AREA)
- Liquid Crystal (AREA)
Abstract
The invention discloses a pixel structure and a manufacturing method thereof. The pixel structure comprises a substrate, a scanning line, a grid, an insulating layer, a semiconductor channel, a data line, a source, a drain, a protecting layer, a pixel electrode and a connecting electrode, wherein the insulating layer is arranged on the scanning line, the grid and the substrate; the semiconductor channel and the data line corresponding to the grid are arranged on the insulating layer; and the data line and the scanning line are not overlapped. The source and the drain are arranged on the semiconductor channel. The protecting layer arranged on the source, the drain and the data line is provided with a first contact hole partially exposing the drain and a plurality of second contact holes partially exposing the data line or the scanning line. The pixel electrode arranged on the protecting layer is electrically connected with the drain by the first contact hole, and the connecting electrode arranged on the protecting layer is electrically connected with the data line or the scanning line by the second contact holes.
Description
Technical field
The invention relates to a kind of dot structure and preparation method thereof, refer to a kind of method and dot structure of saving the making dot structure of light shield number especially.
Background technology
(thin film transistor TFT) has been widely used in the active array-type two-d display panel as driving component, in order to drive devices such as active display panels, active organic electroluminescent display panel thin-film transistor.Known thin-film transistor comprises a grid, one source pole, a drain electrode and as the semi-conductor layer of transistor channel; When making thin-film transistor, need the above micro-photographing process in five roads to define the pattern of each assembly of thin-film transistor usually with existing manufacturing technology.With five road light shield processing procedures is example, and wherein the first road light shield processing procedure is in order to define a first metal layer, to form the members such as grid of scan line and thin-film transistor; The second road light shield processing procedure is in order to define the semiconductor layer of thin-film transistor; The 3rd road light shield processing procedure is in order to defining one second metal level, with members such as the source electrode that forms data wire and thin-film transistor and drain electrodes; The 4th road light shield processing procedure is to be used for patterning one insulating protective layer, to form contact hole; The 5th road light shield processing procedure then is to be used for patterning one transparency conducting layer, to form pixel electrode.
Use number to simplify processing procedure in order to reduce light shield; Common use gray-level mask (half-tone mask) is used as the second road light shield for preparing thin-film transistor when definition thin-film transistor component pattern at present; Gray-level mask comprises a transparency carrier and is located at one on the transparency carrier and covers pattern and the half the zone (half-tone region) of passing through; Wherein covering pattern is the pattern that is used to define thin-film transistor drain electrode and source electrode; And partly pass through the zone is to be used to define the pattern that is positioned at the source electrode and the semiconductor layer of drain electrode below, to replace the second road light shield and the 3rd road light shield in the five road light shield processing procedures, that is to say; When making thin-film transistor, only four micro-photographing process of need can be accomplished the making of thin-film transistor.Yet the general light shield of the price of gray-level mask is expensive, is unfavorable for reducing production costs.Therefore, how in the thin-film transistor processing procedure, reducing light shield simultaneously uses number and saves that production cost is real to be the improved problem of correlation technique person institute desire.
Summary of the invention
One of the object of the invention is to provide a kind of dot structure and preparation method thereof, to save the production cost of thin-film transistor in the dot structure, wherein uses general light shield to replace the assembly pattern of gray-level mask with the definition thin-film transistor.
A preferred embodiment of the present invention provides a kind of method of making dot structure, and its step is following.One substrate is provided, and in substrate, forms an one scan line and a grid.On substrate, scan line and grid, form an insulating barrier and semi-conductor layer in regular turn, then, on semiconductor layer, form a metal level.On metal level, form one first patterning photoresist layer, wherein the first patterning photoresist layer has a smooth end face.The metal level that etching is not covered by the first patterning photoresist layer is to form an electrode pattern and a data wire.The semiconductor layer that etching is not covered by the first patterning photoresist layer, to form the semiconductor channel, wherein data wire and scan line do not overlap.The first patterning photoresist layer is carried out an ashing (ashing) processing procedure; Form one second patterning photoresist layer with the thickness that reduces the first patterning photoresist layer; Wherein the second patterning photoresist layer partly exposes electrode pattern, and an end face of an end face of the second patterning photoresist layer and electrode pattern is copline (coplanar).Etching is not drained to form one source pole and by the electrode pattern that the second patterning photoresist layer covers, and afterwards, removes the second patterning photoresist layer.On source electrode, drain electrode and data wire, form at least one protective layer, wherein protective layer has one first contact cavity portion and exposes drain electrode, and a plurality of second contact cavity portion exposes data wire or scan line.On protective layer, form a patterned transparent conductive layer, wherein patterned transparent conductive layer comprises that a pixel electrode electrically connects via the first contact hole and drain electrode, and a connection electrode is via the second contact hole and data wire or scan line electric connection.
A preferred embodiment of the present invention provides a kind of dot structure, comprises a substrate, one scan line, a grid, an insulating barrier, semiconductor channel, a data wire, one source pole, a drain electrode, a protective layer, a pixel electrode and a connection electrode.Scan line and grid are arranged on the substrate, and insulating barrier is arranged on scan line, grid and the substrate.The semiconductor channel is arranged on the insulating barrier and corresponding grid.Data wire is arranged on the insulating barrier, and wherein data wire and scan line do not overlap.Source electrode and drain electrode are arranged on the semiconductor channel.Protective layer is arranged on source electrode, drain electrode and the data wire, wherein protective layer have one first the contact cavity portion expose drain electrode, and a plurality of second the contact cavity portion expose data wire or scan line.The pixel electrode that is arranged on the protective layer is to electrically connect via the first contact hole and drain electrode, and the connection electrode that is arranged on the protective layer then is via the second contact hole and data wire or scan line electric connection.
The present invention proposes a kind of dot structure and preparation method thereof, and it uses a non-gray-level mask to replace gray-level mask, and utilizes four road light shield processing procedures to accomplish thin-film transistor in the dot structure, can significantly save production cost.In addition; The data wire of dot structure and scan line do not overlap mutually; Be positioned at scan line both sides and data wire separated from one another and use connection electrode instead with electric connection; Or electrically connect and to be positioned at data wire both sides and scan line separated from one another, can avoid because of scan line and data wire overlap (cross-line) cause the broken string of the data wire that is positioned at the top, help extremely corresponding dot structure of the sustainable normal delivery signal of data wire.
Description of drawings
Fig. 1 to Figure 14 has illustrated the production method of pixel structure sketch map of first preferred embodiment of the present invention.
Figure 15 to Figure 16 has illustrated the production method of pixel structure sketch map of second preferred embodiment of the present invention.
Embodiment
Have the knack of under the present invention the general art of technical field and can further understand the present invention for making, the hereinafter spy enumerates preferred embodiment of the present invention, and cooperate appended graphic, specify constitution content of the present invention and the effect desiring to reach.
Please refer to Fig. 1 to Figure 14.Fig. 1 to Figure 14 has illustrated the production method of pixel structure sketch map of first preferred embodiment of the present invention; Wherein Fig. 1, Fig. 5, Fig. 9, Figure 11 and Figure 13 are that the above pattern of looking illustrates, and Fig. 2 to Fig. 4, Fig. 6 to Fig. 8, Figure 10, Figure 12 and Figure 14 illustrate with the section pattern.
Fig. 2 has illustrated the generalized section of the dot structure of a preferred embodiment of the present invention along Figure 1A-A ' line segment and B-B ' line segment.Like Fig. 1 and shown in Figure 2, a substrate 10 is provided, substrate 10 can be for example glass substrate, quartz base plate, a plastic base etc. of hard substrate, also can be the soft substrate plate of other bendable material.Then; Form an one scan line 12 and a grid 14 on substrate 10; The method that wherein forms scan line 12 and grid 14 can comprise by physical vapour deposition (PVD) for example sputter (sputtering), vapor deposition (evaporation), or the long-pending technology of chemical vapour deposition (CVD) or other film Shen forms a conductive layer (figure does not show) comprehensively on substrate 10.Afterwards, carry out a for example micro image etching procedure of a patterning process, to form scan line 12 and grid 14.Scan line 12 electrically connects with grid 14, and forms a continuous line segment jointly.
As shown in Figure 3, on substrate 10, scan line 12 and grid 14, form an insulating barrier 16 and semi-conductor layer 18 in regular turn, and on semiconductor layer 18, form a metal level 22.The material of insulating barrier 16 can comprise for example silica, silicon nitride, silicon oxynitride or other dielectric material, but not as limit; Semiconductor layer 18 can be an amorphous silicon (amorphous silicon) layer or other semi-conducting material; The material of metal level 22 can comprise the combination of aluminium, molybdenum, chromium, tungsten, copper or above-mentioned metal, but not as limit.In addition, for reducing the resistance value between metal level 22 and the semiconductor layer 18, before forming metal level 22, also alternative prior to forming an ohmic contact layer 20 (ohmic contact layer) on the semiconductor layer 18.
As shown in Figure 4, on metal level 22, form one first patterning photoresist layer 24, wherein the first patterning photoresist layer 24 has a smooth end face S1, and grid 14 is covered by the first patterning photoresist layer 24 fully.In addition, the first patterning photoresist layer 24 is not preferably with scan line 12 and overlaps, but not as limit, also can be part and overlap.The method that forms the first patterning photoresist layer 24 is for example prior to forming a photoresist layer (figure does not show) on the metal level 22, because the planarization character voluntarily of photoresist layer, this moment, photoresist layer had smooth end face; Utilize a non-gray-level mask to carry out micro image etching procedure then and form the first patterning photoresist layer 24.Because the exposure that can pass through of non-gray-level mask Zhong Ge district is identical, so the first patterning photoresist layer 24 still has a smooth end face.As shown in Figure 4; The thickness of the first patterning photoresist layer 24 changes with the surface undulation of metal level 22; In more detail; The relation of established thickness of structure is an inverse ratio on the thickness of the first patterning photoresist layer 24 and the substrate 10, and for example the first patterning photoresist layer 24 is less than the thickness h 2 of the first patterning photoresist layer 24 above grid 14 both sides in the thickness h above the grid 14 1.In addition, the first patterning photoresist layer 24 is positioned at the both sides of the part metals layer 22 of scan line 12 tops, and the end face of the first patterning photoresist layer 24 is preferably the end face that is higher than metal level 22.Present embodiment is preferably the first patterning photoresist layer 24 that uses same light shield definition grid 14 tops and scan line 12 tops, but not as limit.
Fig. 6 has illustrated the generalized section of the dot structure of a preferred embodiment of the present invention along Fig. 5 A-A ' line segment and B-B ' line segment.Like Fig. 5 and shown in Figure 6, then remove the metal level 22 that is not covered by the first patterning photoresist layer 24, forming an electrode pattern 26 and a data wire 28, and expose part ohmic contact layer 20.The method of removing part metals layer 22 can comprise carries out a wet etching processing procedure.Electrode pattern 26 is corresponding to grid 14, that is electrode pattern 26 overlaps with grid 14.Data wire 28 comprises that one first data line segment 32 and one second data line segment 34 are separated from one another and lays respectively at the both sides of scan line 12.Afterwards, as shown in Figure 7, remove the ohmic contact layer 20 that is not covered, and remove the semiconductor layer 18 that is not covered by the first patterning photoresist layer 24 by the first patterning photoresist layer 24, with formation semiconductor channel 30, and expose partial insulative layer 16.The method of removing part ohmic contact layer 20 and part semiconductor layer 18 can comprise carries out a dry ecthing procedure.Wherein data wire 28 does not overlap with scan line 12.
As shown in Figure 8; After removing part metals layer 22, part ohmic contact layer 20 and the part semiconductor layer 18 that is not covered by the first patterning photoresist layer 24; The first patterning photoresist layer 24 is carried out an ashing (ashing) processing procedure, form one second patterning photoresist layer 36 with the thickness that reduces the first patterning photoresist layer 24.In more detail; Because the thickness h 1 of the first patterning photoresist layer 24 that is positioned at grid 14 tops is less than the thickness h 2 of the first patterning photoresist layer 24 that is positioned at grid 14 both sides tops; Therefore after carrying out the ashing processing procedure; The first patterning photoresist layer 24 of grid 14 tops can be removed earlier fully, and only stays the first patterning photoresist layer 24 above grid 14 both sides, to form the second patterning photoresist layer 36.And the first patterning photoresist layer 24 that is positioned at scan line 12 tops is also partly removed through ashing processing procedure thus; Forming the second less patterning photoresist layer 36 of thickness, the second patterning photoresist layer 36 of scan line 12 tops is preferably discontinuous the data wire 28 for example first data line segment 32 and the second data line segment 34 that does not expose its below.At this moment; The second patterning photoresist layer, 36 parts of grid 14 tops expose electrode pattern 26; And an end face S3 of this second patterning photoresist layer 36 and an end face S4 of electrode pattern 26 are copline (coplanar), and it is adjacent and contact that the end face S3 that is to say the second patterning photoresist layer 36 is preferably end face S4 with electrode pattern 26.
Figure 10 has illustrated the generalized section of the dot structure of a preferred embodiment of the present invention along Fig. 9 A-A ' line segment and B-B ' line segment.Like Fig. 9 and shown in Figure 10; Next remove the electrode pattern 26 that covered by the second patterning photoresist layer 36 of grid 14 tops forming an one source pole 38 and a drain electrode 40, and remove and do not covered and be positioned at the middle ohmic contact layer 20 of source electrode 38 and drain electrode 40 by this second patterning photoresist layer 36.Its method can comprise that carrying out a wet etching processing procedure removes partial electrode pattern 36 to exposing ohmic contact layer 20; Then carry out a dry ecthing procedure and remove part ohmic contact layer 20 to exposing semiconductor channel 30; The semiconductor channel 30 that wherein exposes can be used as the electronics channel of the thin-film transistor of follow-up completion, and the length-width ratio of semiconductor channel 30 can be adjusted by the width of grid 14.On the other hand; The second patterning photoresist layer 36 that is positioned at scan line 12 tops covers the first data line segment 32 and the second data line segment 34 fully; Therefore in the time of can avoiding removing the ohmic contact layer 20 of partial electrode pattern 26 and source electrode 38 and drain electrode 40 centres, the established first data line segment 32 and the second data line segment 34 are caused damage.
Figure 12 has illustrated the generalized section of the dot structure of a preferred embodiment of the present invention along Figure 11 A-A ' line segment and B-B ' line segment.Like Figure 11 and shown in Figure 12; Remove the second patterning photoresist layer 36; And on source electrode 38, drain electrode 40 and data wire 28, form at least one protective layer 42; Wherein protective layer 42 has one first contact hole, 44 parts and exposes drain electrode 40, and a plurality of second contact holes 46 parts expose data wire 28, and wherein the second contact hole 46 of protective layer 42 is that part exposes the first data line segment 32 and the second data line segment 34 respectively.Figure 14 has illustrated the generalized section of the dot structure of a preferred embodiment of the present invention along Figure 13 A-A ' line segment and B-B ' line segment.At last, like Figure 13 and shown in Figure 14, on protective layer 42, form a patterned transparent conductive layer, wherein patterned transparent conductive layer comprises a pixel electrode 48 and a connection electrode 50.Pixel electrode 48 electrically connects via the first contact hole 44 and drain electrode 40; And connection electrode 50 electrically connects via the second contact hole 46 and data wire 28; In more detail, connection electrode 50 is via the second contact hole 46 and the first data line segment 32 and 34 electric connections of the second data line segment.So far, accomplish four road light shield processing procedures of the thin-film transistor in the dot structure 52.
Please again with reference to Figure 13 and Figure 14.Like Figure 13 and shown in Figure 14; A kind of dot structure 52 of present embodiment comprises a substrate 10, one scan line 12, a grid 14, an insulating barrier 16, semiconductor channel 30, a data wire 28, one source pole 38, a drain electrode 40, one protective layer 42, a pixel electrode 48 and a connection electrode 50.Scan line 12 and grid 14 are arranged on the substrate 10, and insulating barrier 16 is arranged on scan line 12, grid 14 and the substrate 10.Semiconductor channel 30 is arranged on the insulating barrier 16 and corresponding grid 14.Data wire 28 is arranged on the insulating barrier 16, and wherein data wire 28 does not overlap with scan line 12.In the present embodiment, data wire 28 comprises that one first data line segment 32 and one second data line segment 34 are separated from one another and lays respectively at the both sides of scan line 12.Source electrode 38 is arranged on the semiconductor channel 30 with drain electrode 40.For reducing the resistance value between source electrode 38/ drain electrode 40 and the semiconductor channel 30, dot structure 52 can also comprise an ohmic contact layer 20, between source electrode 38 and semiconductor channel 30, and between drain electrode 40 and semiconductor channel 30.Protective layer 42 is arranged on source electrode 38, drain electrode 40 and the data wire 28; And protective layer 42 has one first contact hole, 44 parts and exposes drain electrode 40; And a plurality of second contact holes 46 parts expose data wire 28; Wherein, the second contact hole 46 of protective layer 42 is that part exposes the first data line segment 32 and the second data line segment 34 respectively.In addition; The pixel electrode 48 that is arranged on the protective layer 42 is to electrically connect via the first contact hole 44 and drain electrode 40; The connection electrode 50 that is arranged on the protective layer 42 then is to electrically connect via the second contact hole 46 and data wire 28; In more detail, connection electrode 50 is connected with the first data line segment 32 and the second data line segment 34 respectively via the second contact hole 46, makes the first data line segment 32 and the second data line segment 34 see through connection electrode 50 and electrically connects.It should be noted that; Data wire 28 does not overlap mutually with scan line 12 in the dot structure 52 of the present invention; Electrically connect the data line segment that is positioned at scan line 12 both sides and change with connection electrode 50; In the time of can avoiding data wire 28 to overlap mutually with scan line 12, data wire 28 meetings that are positioned at the top are broken at the cross-line place because of the gross thickness of other structure of its below is blocked up, help keeping the normal function of data wire 28.
Dot structure of the present invention does not exceed with the foregoing description.Hereinafter will be introduced the pixel structure preparation method of other preferred embodiment of the present invention in regular turn; And for the ease of comparing different place and the simplified illustration of each embodiment; Use the identical identical assembly of symbol mark among each embodiment hereinafter; And the different place that is primarily aimed at each embodiment describes, and no longer repeating part is given unnecessary details.
Please refer to Figure 15 to Figure 16; Figure 15 to Figure 16 has illustrated the production method of pixel structure sketch map of second preferred embodiment of the present invention; Wherein Figure 15 has illustrated the top view of the dot structure of present embodiment, and the generalized section of Figure 16 for illustrating along Figure 15 A-A ' line segment and B-B ' line segment.To shown in Figure 16, in a second embodiment, the method that forms dot structure 54 comprises like Figure 15: a substrate 10 is provided, and forms one scan line 56 and grid 14 on substrate 10.Be that with the first embodiment difference scan line 56 is a discontinuous line segment, comprise one first scan lines 62 separated from one another and one second scan lines 64, and the grid 14 and first scan lines 62 electrically connect and form a continuous line segment jointly.Then, on substrate 10, scan line 56 and grid 14, form an insulating barrier 66 and semi-conductor layer 18 in regular turn, and on semiconductor layer, form a metal level (figure does not show).Before forming metal level, the also alternative ohmic contact layer 20 that on semiconductor layer 18, forms.Then, form one first patterning photoresist layer (figure does not show) on metal level, and the first patterning photoresist layer is to utilize non-gray-level mask to form.Therefore, the first patterning photoresist layer has a smooth end face.The first patterning photoresist layer grid 14 that overlaps fully, and the first patterning photoresist layer and scan line 56 be preferably fully and do not overlap, but not as limit, also can be part and overlap.With the first patterning photoresist layer is shielding; Remove the metal level that is not covered by the first patterning photoresist layer; To form an electrode pattern (figure does not show) and a data wire 58; Wherein data wire 58 does not overlap with scan line 56, and scan line 56 comprises that first scan lines 62 and second scan lines 64 are separated from one another and lays respectively at the both sides of the data wire 58 that is a continuous line segment.
Form the semiconductor channel afterwards, source electrode is similar with first embodiment with the mode of drain electrode; Please in the lump with reference to aforementioned related description, Fig. 7, Fig. 8 and Figure 10; Remove the semiconductor layer 18 and ohmic contact layer 20 that are not covered by the first patterning photoresist layer; Be positioned at the semiconductor channel 30 of grid 14 tops with formation, and expose partial insulative layer 66.Then; The first patterning photoresist layer is carried out an ashing processing procedure; Form one second patterning photoresist layer (figure does not show) with the thickness that reduces the first patterning photoresist layer; Wherein the second patterning photoresist layer partly exposes electrode pattern, and an end face of an end face of the second patterning photoresist layer and electrode pattern is a copline.Remove not the electrode pattern that covered by the second patterning photoresist layer again to form source electrode 38 and drain electrode 40, remove the second patterning photoresist layer subsequently.
On source electrode 38, drain electrode 40 and data wire 58, form at least one protective layer 70, wherein protective layer 70 has the first contact hole, 44 parts and exposes drain electrode 40, and a plurality of second contact holes 72 parts expose scan line 56.On protective layer 70, form a patterned transparent conductive layer, wherein patterned transparent conductive layer comprises that pixel electrode 48 electrically connects via the first contact hole 44 and drain electrode 40, and a connection electrode 60 electrically connects via the second contact hole 72 and scan line 56.Be with the first embodiment difference; Insulating barrier 66 has a plurality of the 3rd contact holes 74; The 3rd contact hole 74 corresponding with the second contact hole 72 of protective layer 70 respectively and respectively part expose first scan lines 62 and second scan lines 64; In the present embodiment, connection electrode 60 is via the second contact hole 72 and the 3rd contact hole 74 and first scan lines 62 and 64 electric connections of second scan lines.So far, accomplish four road light shield processing procedures of the thin-film transistor in the dot structure 54.The present invention uses non-gray-level mask to replace the processing procedure that gray-level mask is accomplished thin-film transistor in the dot structure 54, to save the light shield cost.
Like Figure 15 and shown in Figure 16, the dot structure 54 of second embodiment comprises substrate 10, scan line 56, grid 14, insulating barrier 66, semiconductor channel 30, data wire 58, source electrode 38, drain electrode 40, protective layer 70, pixel electrode 48 and connection electrode 60.Be that with dot structure 52 differences of first embodiment scan line 56 comprises that first scan lines 62 and second scan lines 64 are separated from one another and lays respectively at the both sides of data wire 58.Protective layer 70 is arranged on source electrode 38, drain electrode 40 and the data wire 58; And protective layer 70 has the first contact hole, 44 parts and exposes drain electrode 40; And a plurality of second contact holes 72 parts expose scan line 56, it should be noted that insulating barrier 66 is arranged between scan line 56 and the protective layer 70; Therefore for making the second contact hole 72 expose scan line 56; It is corresponding with the second contact hole 72 of protective layer 70 respectively that insulating barrier 66 need have a plurality of the 3rd contact holes 74 in addition, and the 3rd contact hole 74 of insulating barrier 66 is connected with the second contact hole 72 of corresponding protective layer 70 respectively, partly to expose first scan lines 62 and second scan lines 64 respectively.The pixel electrode 48 that is arranged on the protective layer 70 electrically connects via the first contact hole 44 and drain electrode 40; The connection electrode 60 that is arranged on the protective layer 70 then electrically connects with scan line 56 via the second contact hole 72 and the 3rd contact hole 74; In more detail; Connection electrode 60 is to be connected with first scan lines 62 and second scan lines 64 respectively via the second contact hole 72 and the 3rd contact hole 74, makes first scan lines 62 and second scan lines 64 see through connection electrode 60 and electrically connects.Same theory; Data wire 58 does not overlap mutually with scan line 56 in the dot structure 54 of the present invention; Electrically connect the scan lines that is positioned at data wire 58 both sides and change with connection electrode 60; Can avoid in the known technology cross-line place that overlaps mutually at data wire and scan line, the data wire that is positioned at the top breaks, and helps keeping the normal function of data wire.
In sum, the present invention proposes a kind of dot structure and preparation method thereof, and it uses a non-gray-level mask to replace the four road light shield processing procedures that gray-level mask is accomplished thin-film transistor in the dot structure, to save production cost.In addition; The data wire of dot structure and scan line do not overlap mutually; Be positioned at scan line/data wire both sides and data wire/scan line separated from one another and use connection electrode instead with electric connection; Can avoid because of scan line and data wire overlap (cross-line) cause the broken string of the data wire that is positioned at the top, help the sustainable normal delivery signal of data wire to corresponding dot structure.
The above is merely preferred embodiment of the present invention, and all equalizations of doing according to claim of the present invention change and modify, and all should belong to covering scope of the present invention.
Claims (9)
1. a method of making dot structure is characterized in that, comprising:
One substrate is provided;
On this substrate, form an one scan line and a grid;
On this substrate, this scan line and this grid, form an insulating barrier and semi-conductor layer in regular turn;
On this semiconductor layer, form a metal level;
On this metal level, form one first patterning photoresist layer, wherein this first patterning photoresist layer has a smooth end face;
Remove this metal level that is not covered by this first patterning photoresist layer; To form an electrode pattern and a data wire; And remove this semiconductor layer that is not covered by this first patterning photoresist layer, to form the semiconductor channel, wherein this data wire and this scan line do not overlap;
This first patterning photoresist layer is carried out an ashing processing procedure; Form one second patterning photoresist layer with the thickness that reduces this first patterning photoresist layer; Wherein this second patterning photoresist layer partly exposes this electrode pattern, and an end face of an end face of this second patterning photoresist layer and this electrode pattern is a copline;
Removing this electrode pattern that is not covered by this second patterning photoresist layer drains to form one source pole and;
Remove this second patterning photoresist layer;
On this source electrode, this drain electrode and this data wire, form at least one protective layer, wherein this protective layer has one first contact cavity portion and exposes this drain electrode, and a plurality of second contact cavity portion exposes this data wire or this scan line; And
On this protective layer, form a patterned transparent conductive layer; Wherein this patterned transparent conductive layer comprises that a pixel electrode electrically connects via this first contact hole and this drain electrode, and a connection electrode is via those second contact holes and this data wire or the electric connection of this scan line.
2. the method for making dot structure as claimed in claim 1 is characterized in that, this first patterning photoresist layer is to utilize a non-gray-level mask to form.
3. the method for making dot structure as claimed in claim 1; It is characterized in that; This data wire comprises that one first data line segment and one second data line segment are separated from one another and lays respectively at the both sides of this scan line; Those of this protective layer second contact hole is that part exposes this first data line segment and this second data line segment respectively, and this connection electrode is via those second contact holes and this first data line segment and the electric connection of this second data line segment.
4. the method for making dot structure as claimed in claim 1; It is characterized in that; This scan line comprises that one first scan lines and one second scan lines are separated from one another and lays respectively at the both sides of this data wire; This insulating barrier have a plurality of the 3rd contact holes corresponding with those second contact holes of this protective layer respectively and respectively part expose this first scan lines and this second scan lines, and this connection electrode is via those second contact holes and those the 3rd contact holes and this first scan lines and the electric connection of this second scan lines.
5. the method for making dot structure as claimed in claim 1 is characterized in that, also comprises:
Form before this metal level, prior to forming an ohmic contact layer on this semiconductor layer;
Remove this ohmic contact layer that is not covered by this first patterning photoresist layer; And
Remove this ohmic contact layer that is not covered by this second patterning photoresist layer.
6. a dot structure is characterized in that, also comprises:
One substrate;
An one scan line and a grid are arranged on this substrate;
One insulating barrier is arranged on this scan line, this grid and this substrate;
The semiconductor channel is arranged on this insulating barrier and to should grid;
One data wire is arranged on this insulating barrier, and wherein this data wire and this scan line do not overlap;
An one source pole and a drain electrode are arranged on this semiconductor channel;
One protective layer is arranged on this source electrode, this drain electrode and this data wire, wherein this protective layer have one first the contact cavity portion expose this drain electrode, and a plurality of second the contact cavity portion expose this data wire or this scan line;
One pixel electrode is arranged on this protective layer and electrically connects via this first contact hole and this drain electrode; And
One connection electrode is arranged on this protective layer and electrically connects via those second contact holes and this data wire or this scan line.
7. dot structure as claimed in claim 6; It is characterized in that; This data wire comprises that one first data line segment and one second data line segment are separated from one another and lays respectively at the both sides of this scan line; Those of this protective layer second contact hole is that part exposes this first data line segment and this second data line segment respectively, and this connection electrode is via those second contact holes and this first data line segment and the electric connection of this second data line segment.
8. dot structure as claimed in claim 6; It is characterized in that; This scan line comprises that one first scan lines and one second scan lines are separated from one another and lays respectively at the both sides of this data wire; This insulating barrier have a plurality of the 3rd contact holes corresponding with those second contact holes of this protective layer respectively and respectively part expose this first scan lines and this second scan lines, and this connection electrode is via those second contact holes and those the 3rd contact holes and this first scan lines and the electric connection of this second scan lines.
9. dot structure as claimed in claim 6 is characterized in that, also comprises an ohmic contact layer, is positioned at this source electrode and this semiconductor interchannel, and is positioned at this drain electrode and this semiconductor interchannel.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201110399830 CN102496618B (en) | 2011-12-06 | 2011-12-06 | Pixel structure manufacturing method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201110399830 CN102496618B (en) | 2011-12-06 | 2011-12-06 | Pixel structure manufacturing method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN102496618A true CN102496618A (en) | 2012-06-13 |
| CN102496618B CN102496618B (en) | 2013-11-06 |
Family
ID=46188423
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 201110399830 Active CN102496618B (en) | 2011-12-06 | 2011-12-06 | Pixel structure manufacturing method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN102496618B (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2023130486A1 (en) * | 2022-01-07 | 2023-07-13 | 武汉华星光电技术有限公司 | Array substrate and liquid crystal display panel |
| US12001106B2 (en) | 2022-01-07 | 2024-06-04 | Wuhan China Star Optoelectronics Technology Co., Ltd. | Array substrate and liquid crystal display panel |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1845310A (en) * | 2006-03-22 | 2006-10-11 | 广辉电子股份有限公司 | Method for manufacturing pixel array substrate |
| US20080018850A1 (en) * | 2006-07-20 | 2008-01-24 | Au Optronics Corp. | Array substrate and method for fabricating thereof |
| CN101118881A (en) * | 2007-09-06 | 2008-02-06 | 友达光电股份有限公司 | Method for fabricating pixel structure |
-
2011
- 2011-12-06 CN CN 201110399830 patent/CN102496618B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1845310A (en) * | 2006-03-22 | 2006-10-11 | 广辉电子股份有限公司 | Method for manufacturing pixel array substrate |
| US20080018850A1 (en) * | 2006-07-20 | 2008-01-24 | Au Optronics Corp. | Array substrate and method for fabricating thereof |
| CN101118881A (en) * | 2007-09-06 | 2008-02-06 | 友达光电股份有限公司 | Method for fabricating pixel structure |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2023130486A1 (en) * | 2022-01-07 | 2023-07-13 | 武汉华星光电技术有限公司 | Array substrate and liquid crystal display panel |
| US12001106B2 (en) | 2022-01-07 | 2024-06-04 | Wuhan China Star Optoelectronics Technology Co., Ltd. | Array substrate and liquid crystal display panel |
Also Published As
| Publication number | Publication date |
|---|---|
| CN102496618B (en) | 2013-11-06 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN105161505B (en) | A kind of array substrate and preparation method thereof, display panel | |
| US6531392B2 (en) | Method of forming a thin film transistor array panel using photolithography techniques | |
| CN102270656B (en) | Organic light emitting diode display and manufacture method thereof | |
| CN102709238B (en) | Array substrate and manufacturing method thereof | |
| CN104217994B (en) | A kind of thin-film transistor array base-plate and preparation method thereof, display device | |
| US11114474B2 (en) | Thin film transistor, manufacturing method thereof, array substrate, and display panel | |
| JP5023465B2 (en) | Thin film transistor panel | |
| WO2013127200A1 (en) | Array substrate, manufacturing method and display device thereof | |
| CN104134671A (en) | Thin film transistor array substrate and manufacturing method thereof | |
| US10644037B2 (en) | Via-hole connection structure and method of manufacturing the same, and array substrate and method of manufacturing the same | |
| CN109300840A (en) | Display base plate and its manufacturing method, display device | |
| KR100264757B1 (en) | Active matrix lcd and method of producing the same | |
| KR20100005457A (en) | Thin film transistor substrate and method for fabricating the same | |
| JP2021502689A (en) | Manufacturing method of array board, display device and array board | |
| JP2008166669A (en) | Method of manufacturing array circuit board | |
| TW200527093A (en) | Thin film transistor array panel | |
| KR101262184B1 (en) | Display substrate and method for manufacturing the same | |
| CN101692439B (en) | Manufacturing method for a plurality of groups of substrates of thin-film transistor | |
| JP2003517641A (en) | Method for manufacturing active matrix device | |
| US8501552B2 (en) | Pixel structure and method of fabricating the same | |
| JP2002190598A (en) | Thin-film transistor array substrate and method of manufacturing the same | |
| TW573162B (en) | Active matrix liquid crystal device and method of making the same | |
| CN105575977B (en) | Display base plate, preparation method and display device | |
| CN102496618B (en) | Pixel structure manufacturing method | |
| TWI289360B (en) | Thin film transistor array substrate and manufacturing method thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| TR01 | Transfer of patent right | ||
| TR01 | Transfer of patent right |
Effective date of registration: 20230613 Address after: No. two, No. 1188 West Ring Road, Shengze Town, Wujiang District, Jiangsu, Suzhou Patentee after: Suzhou Shengze science and Technology Pioneer Park Development Co.,Ltd. Address before: 215217, No. 88, Tung Hing Road, Tongli District, Wujiang Economic Development Zone, Suzhou, Jiangsu Patentee before: CPTW (WUJIANG) Co.,Ltd. Patentee before: Chunghwa Picture Tubes, Ltd. |