KR101262184B1 - Display substrate and method for manufacturing the same - Google Patents

Abstract

A display substrate and a method of manufacturing the same are disclosed for reducing a resistance variation caused by a difference in length of fanout lines. The display substrate includes a base substrate, signal lines, signal pads, and a fanout line. The display area and the peripheral area are defined on the base substrate. The signal lines cross each other on the display area to define unit pixels. The signal pads are formed in the peripheral area and receive a driving signal from the outside. The fan out line is formed between the signal line and the signal pad corresponding to the signal line and includes at least one island portion spaced apart from each other and at least one first bridge portion formed in a different layer from the island portions to electrically connect the island portions.

In this case, the contact resistance value added to each fan out line may be adjusted by adjusting the number of formation of the first bridge part formed in each fan out line. Therefore, the resistance variation along the length of the fan outlines can be reduced.

Fan Out, Fan Out Line, Bridge, Contact Resistance, and Resistance Deviation

Description

DISPLAY SUBSTRATE AND METHOD FOR MANUFACTURING THE SAME}

1 is a partial plan view of a display substrate according to an exemplary embodiment of the present invention.

2 is an enlarged view of a region A of FIG. 1 according to an exemplary embodiment of the present invention.

3 is an enlarged view illustrating region B of FIG. 2 according to an exemplary embodiment of the present invention.

4 is an enlarged view illustrating an area C of FIG. 1 according to an embodiment of the present invention.

FIG. 5 is a cross-sectional view taken along line II ′ of FIG. 4.

FIG. 6 is an enlarged view of a region B of FIG. 2 according to another exemplary embodiment of the present invention.

FIG. 7 is an enlarged view of a region B of FIG. 2 according to another exemplary embodiment of the present invention.

8 to 12 are process diagrams illustrating a method of manufacturing the display substrate illustrated in FIG. 5.

<Description of the symbols for the main parts of the drawings>

100: display substrate 110: base substrate

PA: Display Area SA: Peripheral Area

DL: data line GL: gate line

DCL: Data connection line DGL: Gate connection line

DIE: Data Island Part GIE: Gate Island Part

120: first insulating layer 150: second insulating layer

B1, B2, B3, B4, B5, B6: First, second, third, fourth, fifth, and sixth bridge parts

P: unit pixel PE: pixel electrode

DFL: Data Fanout Line GFL: Gate Fanout Line

The present invention relates to a display substrate and a method of manufacturing the same, and more particularly, to a display substrate and a method of manufacturing the same having a fanout line structure for reducing the resistance difference caused by the length difference of the fanout lines.

In general, the display substrate includes a display area in which signal lines defining a plurality of unit pixels cross each other and a peripheral area surrounding the display area. A switching element connected to the signal lines and a pixel electrode receiving a pixel voltage from the switching element are formed in the unit pixel defined in the display area.

Pads contacting an external driving signal applying unit and fan-out lines connecting the signal lines to the pads are formed in the peripheral area.

In this case, since the spacing between the pads adjacent to each other is smaller than the spacing between the signal lines constituting the unit pixel, the pad fanout lines have different lengths according to the linear distance between the pads and the signal lines corresponding to each other.

Such a difference in length of the fanout line results in a difference in resistance between the fanout lines, resulting in difficulty in uniform driving of the display substrate.

Accordingly, the technical problem of the present invention is to solve such a conventional problem, and an object of the present invention is to provide a display substrate for reducing the resistance variation caused by the length difference of the fan out lines.

Another object of the present invention is to provide a method of manufacturing the display substrate.

In order to realize the above object of the present invention, the display substrate includes a base substrate, signal lines, signal pads, and a fanout line. A display area and a peripheral area are defined in the base substrate. The signal lines cross each other on the display area to define unit pixels. The signal pads are formed in the peripheral area and receive a driving signal from the outside. The fanout line is formed between the signal line and the signal pad corresponding to the signal line, and is formed of island parts spaced apart from each other and a layer different from the island parts to electrically connect the island parts. It includes 1 bridge part.

In accordance with another aspect of the present invention, there is provided a method of manufacturing a display substrate, including forming a first metal pattern including a gate line on a substrate, and forming the first metal pattern on the substrate. Forming a first insulating layer, forming a second metal pattern including a data line and a data pad on the first insulating layer, and forming at least one of the first metal pattern and the second metal pattern. Forming data island portions spaced apart from each other between the data line and the data pad, forming a second insulating layer on the substrate on which the second metal pattern is formed, and simultaneously forming the first and second insulating layers. Patterning to form first holes exposing both ends of the data island portions, forming a conductive material layer on the second insulating layer and the conductive material Patterning the layer, the pixel electrode and forming at least one first bridge unit for the data at the same time in contact with the island parts adjacent to each other via the first hole.

According to the display substrate and the manufacturing method thereof, the contact resistance value added to each fanout line can be adjusted by adjusting the number of formation of the first bridge portions formed in each fanout line. It is possible to reduce the resistance variation that occurs.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will now be described in more detail with reference to the accompanying drawings.

1 is a partial plan view of a display substrate according to an exemplary embodiment of the present invention.

Referring to FIG. 1, gate lines GL extending in a first direction x and data lines extending in a second direction y crossing the first direction x on the display substrate 100. The display area PA in which the plurality of unit pixels P are defined by the DLs, and the peripheral area SA surrounding the display area PA are defined.

In the peripheral area SA, a plurality of gate pads GP and data pads DP for receiving a driving signal from an external driving signal applying unit 10 are formed, and the plurality of gate pads GP Dense to each other to form a few gate pad groups (GPG).

Similarly, the plurality of data pads DP are dense with each other to form a small number of data pad groups DPG.

A gate fanout line GFL is formed between the gate pad group GPG and the gate lines GL to electrically connect the respective gate pads GP and each gate line GL.

In addition, a data fanout line DFL is formed between the data pad group DPG and the data lines DL to electrically connect each data pad DP and each data line DL.

Meanwhile, since the distance between the gate pads GP adjacent to each other in the gate pad group GPG is smaller than the distance between the gate lines GL constituting the unit pixel P, the gate pads GP corresponding to each other. ) And the longer the straight line distance between the gate line GL and the longer the length of the gate fanout line GFL. Accordingly, since the lengths of the gate fanout lines GFL are different from each other, the gate fanout lines GFL have variations in resistance values according to length differences. Similarly, the data fan-out lines DFL may have variations in resistance values according to length differences.

Accordingly, the gate and data fanout lines GFL and DFL are formed in the structure shown in FIG. 2.

2 is an enlarged view of a region A of FIG. 1 according to an exemplary embodiment of the present invention.

2, a portion of the data fanout line DFL is patterned by zigzag. In addition, the number of zig-zag repetitions of the data fanout lines DFL increases as the distance between the data lines DL and the data pads DP corresponding to each other becomes shorter.

Accordingly, the length between the data fanout line DFL connecting the data pad DP and the data line DL may be similarly adjusted. However, zigzag patterning alone cannot completely eliminate the difference in length between data fanout lines (DFLs), and there is also a resistance variation. Accordingly, in the present invention, in addition to zigzag patterning, a bridge part (not shown) for adjusting a contact resistance value applied to each data fanout line DFL is formed.

3 is an enlarged view illustrating region B of FIG. 2 according to an exemplary embodiment of the present invention.

2 and 3, a data fanout line DFL is disposed between the data connection line DCL extending from the data line DL and between the data connection line DCL and the data pad DP. The plurality of data island units DIE formed, at least one first bridge unit B1 formed on a layer different from the data island unit DIE, and a second layer formed on the same layer as the first bridge unit B1. The bridge part B2 and the 3rd bridge part B3 are included.

 In detail, at least one insulating layer is formed between the data island part DIE and the first bridge part B1, and a first portion exposing both ends of the data island part DIE in the insulating layer. A hole H1, a second hole H2 exposing an end of the data connection line DCL, a data pad hole DPH and a data pad hole DPH exposing the data pad DP; Separately, a third hole H3 exposing one end of the data pad DP is formed.

The first bridge part B1 contacts the data island units DIE adjacent to each other through the first hole H1. Accordingly, the data island units DIE spaced apart from each other are electrically connected to form one conductive line.

The second bridge part B2 is connected to the data connection line through a second hole H2 formed on the data connection line DCL and a first hole H1 formed on the data island part DIE. DCL) and the data island part DIE closest to the data connection line DCL are simultaneously in contact with each other. Accordingly, the data connection line DCL and the data island unit DIE closest to the data connection line DCL are electrically connected to each other.

The third bridge portion B3 is disposed on the data pad DP and the data pad DP through a third hole H3 and the first hole H1 formed on the data pad DP. Contact is simultaneously made with an adjacent data island portion (DIE). Accordingly, the data pad DP and the data island unit DIE closest to the data pad DP are electrically connected to each other.

Thus, a data fanout line DFL is formed to electrically connect the data line DL and the data pad DP.

  In this case, the number of data island units DIE and the first bridge units B1 constituting the data fanout line DFL are different, and the data line DL and the corresponding data pad DP are different. The shorter the straight line spacing, the greater the number of the first bridge portion B1 and the data island portion DIE.

Since the first bridge portion B1 and the data island portion DIE are in contact with each other through the first hole H1 as described above, as the number of first bridge portions B1 increases, the data fanout line DFL is increased. The contact resistance value applied to) increases.

Therefore, according to the present invention, the number of formation of the first bridge portion B1 is adjusted or the contact area between the first bridge portion B1 and the data island portion DIE is adjusted for each data fanout line DFL. The contact resistance value applied can be adjusted. Therefore, the variation of the resistance value caused by the difference in length between the data fanout lines DFL may be offset by the above-described addition or decrease of the contact resistance value.

2 and 3 illustrate the present invention using the data fanout line DFL as an example, but the gate fanout line GFL is also formed in a structure substantially similar to that of the data fanout line DFL.

Hereinafter, the present invention will be described in more detail with reference to FIGS. 4 to 5.

4 is an enlarged view illustrating an area C of FIG. 1 according to an embodiment of the present invention.

FIG. 5 is a cross-sectional view taken along line II ′ of FIG. 4.

1, 4, and 5, the display substrate 100 includes a base substrate 110. A first metal pattern including the gate line DL, the gate connection line DCL gate electrode D, the gate pad DP, and the gate island part DIE is formed on the base substrate 110.

The gate line GL is formed on the base substrate 110 to correspond to the display area PA. The gate connection line GCL extends from the gate line GL to the peripheral area SA.

The gate electrode G protrudes into the unit pixel P from the gate line GL. The gate pads GP are formed in the peripheral area SA in the same number as the gate lines GL.

The gate island parts GIE are disposed between one gate line GL and a gate pad GP corresponding to the one gate line GL. The gate island parts GIE are formed spaced apart from each other by a predetermined interval.

Each gate island portion GIE may be the same in length and shape or may be different. That is, the shorter the linear distance between the gate line GL and the gate pad GP corresponding to each other, the greater the number of gate island portions GIE constituting the gate fanout line GFL. In addition, as the linear distance between the gate line GL and the gate pad GP corresponding to each other increases, the length of the gate island part GIE constituting the gate fanout line GFL may increase.

The first insulating layer 120 is formed on the base substrate 110 on which the first metal pattern is formed. The first insulating layer 120 may be formed of, for example, silicon nitride (SiNx) or silicon oxide (SiOx).

The active layer A overlapping the gate electrode G is formed on the first insulating layer 120. For example, the active layer A is formed of a structure in which a semiconductor layer 131 made of amorphous silicon and an ohmic contact layer 132 made of ion-doped amorphous silicon are stacked.

The data line DL, the data connection line DCL, the source electrode S, the drain electrode D, the data pad DP, and the data island are formed on the first insulating layer 120 on which the active layer A is formed. A second metal pattern including a portion DIE is formed.

The source electrode S protrudes from the data line DL into the unit pixel P and partially overlaps the active layer A. The drain electrode D is formed to be spaced apart from the source electrode S by a predetermined distance, and partially overlaps the active layer A. In this case, the ohmic contact layer 132 is removed from the source electrode S and the drain electrode D to expose the semiconductor layer 131.

The data island units DIE are disposed between one data line DL and a data pad DP corresponding to the data line DL. The data island units DIE are formed spaced apart from each other by a predetermined interval. Each of the data island portions DIE may have the same length and shape or may be different. That is, the shorter the linear distance between the data line DL and the data pad DP corresponding to each other, the greater the number of data island units DIE. In addition, the longer the linear gap between the data line DL and the data pad DP corresponding to each other, the longer the length of the data island unit DIE constituting the data fanout line DFL may be.

The second insulating layer 150 is formed on the base substrate 110 on which the second metal pattern is formed. The second insulating layer 150 may be made of, for example, silicon nitride or silicon oxide.

In this case, a first hole H1 exposing both ends of the data island portions DIE and a contact hole CH exposing one end of the drain electrode are formed in the second insulating layer 150. In addition, the second hole H2 exposing an end of the data connection line DCL, the data pad hole DPH exposing the data pad DP, and the data pad hole DPH are separately provided. A third hole H3 exposing one end of the data pad DP may be formed. In addition, fourth holes H4 exposing both ends of the gate island parts GIE are exposed in the first and second insulating layers 120 and 150, and fifth holes H5 exposing end portions of the gate connection line. ), A sixth hole H6 exposing one end of the gate pad GP may be formed separately from the gate pad hole GPH exposing the gate pad and the gate pad hole GPH.

The pixel electrode PE, the first bridge portion B1, the second bridge portion B2, the third bridge portion B3, the fourth bridge portion B4, and the fifth bridge are disposed on the second insulating layer 150. An electrode pattern including the portion B5 and the sixth bridge portion B6 is formed.

The pixel electrode 150 is formed corresponding to each unit pixel P and is in electrical contact with the drain electrode D through the contact hole CH.

The first bridge portion B1 contacts the data island portions DIE adjacent to each other through the first hole H1 formed in the second insulating layer. Accordingly, the data island parts GIE are electrically connected to each other to form one conductive line.

The second bridge part B2 is connected to the data connection line through a second hole H2 formed on the data connection line DCL and a first hole H1 formed on the data island part DIE. DCL) and the data island part DIE closest to the data connection line DCL are simultaneously in contact with each other. Accordingly, the data connection line DCL and the data island unit DIE closest to the data connection line DCL are electrically connected to each other.

The third bridge portion B3 is disposed on the data pad DP and the data pad DP through a third hole H3 and the first hole H1 formed on the data pad DP. Contact is simultaneously made with an adjacent data island portion (DIE). Accordingly, the data pad DP and the data island unit DIE closest to the data pad DP are electrically connected to each other.

Thus, a data fanout line DFL is formed to electrically connect the data line DL and the data pad DP.

Similarly, the fourth bridge portion B4 is in contact with the gate island portions GIE adjacent to each other through the fourth holes H4 formed in the first and second insulating layers 120 and 150. Accordingly, the gate island parts GIE are electrically connected to each other to form one conductive line.

The fifth bridge part B5 is connected to the gate connection line through a fifth hole H5 formed on the gate connection line GCL and a fourth hole H4 formed on the gate island part GIE. GCL and the gate island part GIE closest to the gate connection line GCL are simultaneously in contact with each other. Accordingly, the gate connection line GCL and the gate island part GIE closest to the gate connection line GCL are electrically connected to each other.

The sixth bridge part B6 is most extended to the gate pad GP and the gate pad GP through the sixth hole H6 and the fourth hole H4 formed on the gate pad GP. It contacts simultaneously with the adjacent gate island part GIE. Accordingly, the gate pad GP and the gate island part GIE closest to the gate pad GP are electrically connected to each other.

Thus, a gate fanout line GFL is formed to electrically connect the gate line GL and the gate pad GP.

In the present invention, in addition to the zigzag patterning, by forming a bridge portion, the contact resistance applied to the fanout lines can be added or decreased. Accordingly, the resistance variation due to the difference in length between the fanout lines can be reduced.

Meanwhile, in the embodiment of the present invention, the island parts and the bridge parts are formed perpendicular to each other, but the present invention is not limited thereto, and the shape of the island parts and the bridge parts may be modified.

FIG. 6 is an enlarged view of a region B of FIG. 2 according to another exemplary embodiment of the present invention. In FIG. 6, the same reference numerals are given to the same components as in the embodiment of the present invention. Further, in the present invention, since the gate fan out line and the data fan out line are formed in substantially the same structure, both the data island part and the gate island part are referred to as "island parts".

3 and 6, the island portions DIE and the first, second, and third bridge portions B1, B2, and B3 are opposite to each other. Is formed in the direction.

FIG. 7 is an enlarged view of a region B of FIG. 2 according to another exemplary embodiment of the present invention. In FIG. 7, the same reference numerals are assigned to the same components as in the embodiment of the present invention. Further, in the present invention, since the gate fan out line and the data fan out line are formed in substantially the same structure, both the data island part and the gate island part are referred to as "island parts".

3 and 7, the island portions DIE and the shapes of the island portions DIE and the first, second and third bridge portions B1, B2, and B3 are arranged in a straight line. It is understood that the present invention is not limited thereto and may have two or more sides.

Although not shown, the island parts DIE and the first, second, and third bridge parts B1, B2, and B3 may be formed in a curved line.

Hereinafter, a method of manufacturing a display substrate according to an exemplary embodiment of the present invention will be described.

8 to 12 are process diagrams illustrating a method of manufacturing the display substrate illustrated in FIG. 5.

Referring to FIG. 8, a first metal layer (not shown) is formed on the base substrate 110. The first metal layer may be formed of, for example, a metal such as chromium, aluminum, tantalum, molybdenum, titanium, tungsten, copper, silver, or an alloy thereof, or may be formed of two or more layers having different physical properties. have.

 Subsequently, a first photoresist film (not shown) is coated on the first metal layer. In one example, the first photoresist film is made of a positive photoresist in which the exposed region is removed by a developer. Subsequently, the first photoresist film is patterned by a photolithography process to form a first photoresist pattern PR1.

Next, the first metal layer (not shown) is patterned by an etching process using the first photoresist pattern PR1 as an etching mask, so that the gate line DL and the gate connection line DCL gate electrode D are patterned. The first metal pattern including the gate pad DP and the gate island parts DIE is formed.

The etching process of forming the first metal pattern is, for example, a wet etching process. In addition, when the etching process for forming the first metal pattern is completed, the first photoresist pattern PR1 remaining on the first metal pattern is removed using a strip solution.

Referring to FIG. 9, the first insulating layer 120, the semiconductor layer 131, and the ohmic contact layer 132 are continuously formed on the base substrate 110 on which the first metal pattern is formed by using a chemical vapor deposition method. Form. For example, the first insulating layer 120 is made of silicon nitride or silicon oxide. The semiconductor layer 131 is made of amorphous silicon. The ohmic contact layer 132 is made of ion-doped amorphous silicon.

Subsequently, a second photoresist film (not shown) is coated on the ohmic contact layer 132, and the second photoresist film is patterned by a photolithography process to form a second photoresist pattern PR2. Next, the ohmic contact layer 132 and the semiconductor layer 131 are simultaneously patterned by an etching process using the second photoresist pattern PR2 as an etching mask to overlap the gate electrode G. Form A).

The etching process for forming the active layer A is preferably performed by dry etching. When the etching process for forming the active layer A is completed, the second photoresist pattern PR2 remaining on the active layer A is removed with a strip solution.

Referring to FIG. 10, a second metal layer (not shown) is formed on the base substrate 110 on which the active layer A is formed. The second metal layer may be formed of, for example, a metal such as chromium, aluminum, tantalum, molybdenum, titanium, tungsten, copper, silver, or an alloy thereof, or may be formed of two or more layers having different physical properties. have.

Subsequently, a third photoresist film (not shown) is coated on the second metal layer, and the third photoresist film is patterned by a photolithography process to form a third photoresist pattern PR3. Next, the second metal layer is patterned by an etching process using the third photoresist pattern PR3 as an etching mask to form a data line DL, a data connection line DCL, a source electrode S, and a drain electrode D. ), And a second metal pattern including the data pad DP and the data island part DIE.

Next, the ohmic contact layer 132 exposed at the spaced portion between the source electrode S and the drain electrode D is etched. The ohmic contact layer 132 may be etched by dry etching.

As a result, the switching element TFT including the gate electrode G, the active layer A, the source electrode S, and the drain electrode D is formed.

When the etching process of the ohmic contact layer 132 is finished, the third photoresist pattern PR3 remaining on the second metal pattern is removed with a strip solution.

Referring to FIG. 11, a second insulating layer 150 is formed on the base substrate 110 on which the switching element TFT is formed by using a chemical vapor deposition method. For example, the second insulating layer 150 may be formed of silicon nitride or silicon oxide.

Subsequently, a fourth photoresist film (not shown) is coated on the second insulating layer 150, and a fourth photoresist pattern PR4 is formed by a photolithography process.

Next, a first process of simultaneously etching both the first and second insulating layers 120 and 150 by using the fourth photoresist pattern PR4 as an etching mask to expose both ends of the data island units DIE. The hole H1, the second hole H2 exposing the end of the data connection line DCL, the contact hole CH exposing one end of the drain electrode, and the data pad DP are exposed. A third hole H3 exposing one end of the data pad DP is formed separately from the data pad hole DPH and the data pad hole DPH. In addition, a fourth hole H4 exposing both ends of the gate island parts GIE, a fifth hole H5 exposing the end of the gate connection line, and a gate pad hole exposing the gate pad. A sixth hole H6 exposing one end of the gate pad GP is formed separately from the GPH and the gate pad hole GPH.

Subsequently, the fourth photoresist pattern PR4 formed on the second insulating layer 10 is removed with a strip solution.

Referring to FIG. 12, a transparent conductive layer is formed on the second insulating layer 150 in which the first, second, third, fourth, and fifth sixth holes H1, H2, H3, H4, H5, and H6 are formed. A transparent electrode layer (not shown) made of a material is formed. The transparent electrode layer may be formed of, for example, indium tin oxide, indium zinc oxide, amorphous indium tin oxide, or the like, and may be deposited by a sputtering method.

Subsequently, a fifth photoresist film (not shown) is coated on the transparent electrode layer, and the fifth photoresist film is patterned by a photolithography process to form a fifth photoresist pattern PR5.

Next, the transparent electrode layer is etched by using the fifth photoresist pattern PR5 as an etching mask to etch the pixel electrode PE, the first bridge part B1, the second bridge part B2, and the third bridge. An electrode pattern including the bridge portion B3, the fourth bridge portion B4, the fifth bridge portion B5, and the sixth bridge portion B6 is formed.

The pixel electrode PE is formed corresponding to the unit pixel P, and contacts the drain electrode D through the contact hole CH to receive a pixel voltage from the switching element TFT.

The first bridge portion B1 contacts the data island portions DIE adjacent to each other through the first hole H1 formed in the second insulating layer. Accordingly, the data island parts GIE are electrically connected to each other to form one conductive line.

The second bridge part B2 is connected to the data connection line through a second hole H2 formed on the data connection line DCL and a first hole H1 formed on the data island part DIE. DCL) and the data island part DIE closest to the data connection line DCL are simultaneously contacted. Accordingly, the data connection line DCL and the data island unit DIE closest to the data connection line DCL are electrically connected to each other.

The third bridge portion B3 is disposed on the data pad DP and the data pad DP through a third hole H3 and the first hole H1 formed on the data pad DP. Contact is simultaneously made with an adjacent data island portion (DIE). Accordingly, the data pad DP and the data island unit DIE closest to the data pad DP are electrically connected to each other.

Thus, a data fanout line DFL is formed to electrically connect the data line DL and the data pad DP.

Similarly, the fourth bridge portion B4 is in contact with the gate island portions GIE adjacent to each other through the fourth holes H4 formed in the first and second insulating layers 120 and 150. Accordingly, the gate island parts GIE are electrically connected to each other to form one conductive line.

The fifth bridge part B5 is connected to the gate connection line through a fifth hole H5 formed on the gate connection line GCL and a fourth hole H4 formed on the gate island part GIE. GCL and the gate island part GIE closest to the gate connection line GCL are simultaneously in contact with each other. Accordingly, the gate connection line GCL and the gate island part GIE closest to the gate connection line GCL are electrically connected to each other.

The sixth bridge part B6 is most extended to the gate pad GP and the gate pad GP through the sixth hole H6 and the fourth hole H4 formed on the gate pad GP. It contacts simultaneously with the adjacent gate island part GIE. Accordingly, the gate pad GP and the gate island part GIE closest to the gate pad GP are electrically connected to each other.

Thus, a gate fanout line GFL is formed to electrically connect the gate line GL and the gate pad GP.

Subsequently, the fifth photoresist pattern PR5 remaining on the electrode pattern is removed with a strip solution. As a result, the display substrate 100 according to the exemplary embodiment of the present invention is completed.

As described above, according to the present invention, by forming a fanout line composed of island portions and at least one bridge portion electrically connecting the island portions, and controlling the number of bridge portions formed in each fanout line, The contact resistance value applied to the fan out line can be added or subtracted. Accordingly, the resistance variation due to the difference in length of the fanout lines can be compensated for.

Although described above with reference to the embodiments, those skilled in the art can be variously modified and changed within the scope of the invention without departing from the spirit and scope of the invention described in the claims below. I can understand.

Claims (21)

A base substrate having a display area and a peripheral area defined therein; Signal lines defining unit pixels crossing each other on the display area; Signal pads formed in the peripheral area and receiving a driving signal from the outside; And And at least one first bridge portion formed between the signal line and the signal pad corresponding to the signal line, the island portions spaced apart from each other, and at least one first bridge portion formed in a different layer from the island portions to electrically connect the island portions. A display substrate comprising a fanout line. The display substrate of claim 1, wherein the number of the first bridge parts included in the fanout line increases as the linear distance between the signal line and the signal pad connected by the fanout line increases. The display substrate of claim 1, wherein the fanout line is patterned by a zigzag pattern. 4. The display substrate of claim 3, wherein the number of zig-zag repetitions of the fan-out line patterned by the zig-zag increases as the linear distance between the signal line and the signal pad connected by the fan-out line increases. The apparatus of claim 4, wherein the fan out line comprises: a connection line extending from the signal line to the peripheral area; A second bridge portion electrically connected to the connection line and the island portion closest to the connection line and formed on the same layer as the first bridge portion; And And a third bridge portion electrically connected to the signal pad and the island portion closest to the signal pad, the third bridge portion being formed on the same layer as the first bridge portion. The method of claim 1, wherein the signal lines Gate wirings extending in a first direction and formed of a first metal pattern; And And data lines extending in a second direction crossing the first direction and formed of a second metal pattern. The display substrate of claim 6, wherein the island parts are formed of at least one of the first metal pattern and the second metal pattern. The method of claim 6, A first insulating layer formed between the first metal pattern and the second metal pattern; And And a second insulating layer formed on the second metal pattern. 9. The method of claim 8, A switching element formed in the unit pixel and connected to the signal lines; And And a pixel electrode formed on the second insulating layer to receive a pixel voltage from the switching element. The display substrate of claim 9, wherein the first bridge portion is formed of the same material as the pixel electrode. The display substrate of claim 8, wherein the first and second insulating layers include holes for connecting the island portion and the first bridge portion. Forming a first metal pattern including a gate line on the substrate; Forming a first insulating layer on the substrate on which the first metal pattern is formed; Forming a second metal pattern including a data line and a data pad on the first insulating layer; Forming data island portions spaced apart from each other between the data line and the data pad by at least one of the first metal pattern and the second metal pattern; Forming a second insulating layer on the substrate on which the second metal pattern is formed; Simultaneously patterning the first and second insulating layers to form first holes exposing both ends of the data island portions; Forming a conductive material layer on the second insulating layer; And Patterning the conductive material layer to form at least one first bridge portion which simultaneously contacts the data island portions adjacent to each other through a pixel electrode and the first hole. The method of claim 12, wherein the first bridge portion and the data island portions electrically connected by the first bridge portion form a data fanout line electrically connecting the data line and the data pad. The manufacturing method of the display substrate to carry out. The method of claim 13, wherein the number of formations increases as the linear distance between the data line and the data pad connected to the data fan-out line is shorter. The method of claim 13, wherein the data fanout line is patterned by a zigzag pattern. The method of claim 15, wherein the number of times the zig zag of the data fanout line is increased increases as the linear interval between the data line and the data pad connected by the data fanout line is shorter. The method of claim 12, wherein the forming of the first metal pattern comprises: And forming a gate pad spaced apart from the gate line. The method of claim 17, wherein forming the data island portions comprises: And forming gate island portions spaced apart from each other between the gate line and the gate pad using at least one of the first metal pattern and the second metal pattern. The method of claim 18, wherein the forming of the first hole further comprises forming a second hole exposing both ends of the gate island parts. 20. The display of claim 19, wherein forming a first bridge portion further comprises forming at least one second bridge portion in simultaneous contact with the gate island portions adjacent to each other via the second hole. Method of manufacturing a substrate. The method of claim 20, wherein the second bridge portion and the gate island portions electrically connected by the second bridge portion form a gate fanout line electrically connecting the gate line and the gate pad. The manufacturing method of the display substrate to carry out.

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