JP2001005031A - Thin film transistor array substrate and its production - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a thin film transistor array substrate on which a terminal pattern can be optically recognized and an external circuit for driving the liquid crystal can be mounted, by extending a gate lead line to a terminal part through a gate insulating film to form a terminal light-shielding layer and forming the light-shielding layer into an almost same shape as a transparent electrically conductive film. SOLUTION: A terminal light-shielding layer 41 in a terminal part is made almost same as the terminal and is extended to a contact hole 46, and then the terminal light-shielding layer 41 is electrically connected to a transparent electrically conductive film 43. Since the transparent electrically conductive film 43 and the terminal light-shielding layer 41 also acting as a gate lead line are formed through a gate insulating film 42, these layers are electrically connected in parallel in the circuit and most of the current flows through the contact hole 46 on the end of a gate terminal 21 to the gate lead line and terminal light-shielding layer 41. Thereby, when an external circuit for driving the liquid crystal is to be connected, the terminal can be recognized, and the external circuit for driving the liquid crystal can be mounted while optically checking a terminal pattern.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a thin film transistor array substrate and a method for manufacturing the same.

[0002]

2. Description of the Related Art In recent years, as the size and the contrast of liquid crystal display devices have increased, the resistance of wiring materials has been required to be reduced. Therefore, aluminum,
High melting point low resistance materials such as molybdenum, tungsten or alloys thereof have been widely used.

[0003] However, for example, as shown in FIG.
When aluminum or an aluminum alloy is used for the gate wiring 15, the gate electrode 12, the drain wiring 16, and the drain electrode 14 of the T array substrate, there is a problem that good contact cannot be made with the transparent conductive film or the semiconductor layer. Therefore, a technique of capping aluminum or an aluminum alloy with chromium, titanium, or the like has been developed, but in order not to increase the number of processes, a technique of etching the entire capping film at once is necessary. There is a problem that it is difficult to control the shape. Further, the resistance of an alkali cleaning solution or an amine-based resist stripping solution generally used for cleaning a TFT array glass substrate is poor, and it is necessary to apply a new chemical.

On the other hand, when molybdenum, tungsten, or an alloy thereof is similarly used, there is no problem such as aluminum or an aluminum alloy, but there is a problem that corrosion easily occurs at high temperature and high humidity. Even if a transparent conductive film is formed on these metals to a thickness of about several tens of nm, the corrosion cannot be suppressed, and the use of these metals for the terminal portion has a problem of reliability. As shown in FIG. A general terminal structure in which a wiring metal and a transparent conductive film are laminated cannot be adopted.

[0005] In order to prevent the above-mentioned disadvantages, for example, a technique described in Japanese Patent Application Laid-Open No. Hei 6-160905 is known. In the example shown in FIG. 10, when aluminum of a low resistance material is used for the wiring and aluminum is used for the terminal part, the aluminum is deteriorated, and the terminal part is formed of another metal to avoid the problem. Therefore, there is a problem that the number of steps is increased, and in order to solve those problems, a technique of changing the terminal structure to a transparent conductive film single-layer terminal structure is disclosed.

[0006]

However, in this manufacturing method, since the terminal is formed of a single layer of the transparent conductive film,
When an external circuit for driving a liquid crystal is automatically mounted on this terminal in a later step, a disadvantage arises in that the terminal pattern cannot be optically recognized.

When mounting an external circuit for driving a liquid crystal, it is a well-known technique to use an alignment mark formed near a terminal in a metal wiring forming step. For example, as disclosed in Japanese Patent Application Laid-Open No. Hei 5-21515, there is a technique in which dummy terminals and alignment marks are provided on both sides of a terminal group and an external circuit for driving a liquid crystal is mounted.

Further, in recent technical trends, a frame of an external circuit mounting area for driving a liquid crystal has to be narrowed in order to secure a large display area with respect to an outer dimension of a liquid crystal display device, and a display pixel has to be improved in order to improve display quality. And the terminal area is being reduced.

In the above-mentioned Japanese Patent Application Laid-Open No. Hei 5-21515,
An alignment mark for mounting an external circuit for driving a liquid crystal, which is formed in the vicinity of the terminal portion in the metal wiring step, and the terminal portion come closer to each other, which causes a short circuit due to electrostatic breakdown or foreign matter. In addition, since ITO is formed to a thickness of about 600 μm, it is difficult to process and the variation in pattern quality is increased, which causes a problem in alignment accuracy. Further, although a method of forming a dummy terminal and an alignment mark with aluminum to improve the alignment accuracy is disclosed, the number of manufacturing steps is increased by one, which causes a problem in productivity.

An object of the present invention is to provide a thin film transistor array substrate capable of optically confirming a terminal pattern and mounting an external circuit for driving a liquid crystal, and a method of manufacturing the same.

[0011]

Therefore, according to the present invention, a terminal light-shielding layer is provided by extending a gate lead-out line to a terminal portion via a gate insulating film 42, and has substantially the same shape as a transparent conductive film. Structure. As a result, the terminals themselves can be aligned, and there is no need to provide an alignment mark near the terminals, so that a short circuit can be prevented.

Further, since the light-shielding layer can be easily processed and the number of manufacturing steps does not increase, the above-mentioned problem can be solved.

Further, in the present invention, the terminal light shielding layer and the transparent conductive film are electrically connected outside the liquid crystal driving external circuit connection region. This makes it possible to make the terminal light-shielding layer and the transparent conductive film the same potential, thereby preventing electrostatic breakdown between both.

In addition, in a terminal having a single-layer structure of a transparent conductive film,
The positional accuracy when mounting the external circuit for driving the liquid crystal on the terminals is stricter than that of the terminal structure in which the transparent conductive film and the metal are directly laminated, and may exceed the process capability of the mounting apparatus.
Therefore, in the present invention, the terminal light-shielding layer and the transparent conductive film are electrically connected at both ends covered with the passivation film outside the mounting area of the liquid crystal driving external circuit, so that the mounting position accuracy can be reduced. .

[0015]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to the drawings.

FIG. 1 is a conceptual diagram of a TFT array substrate of a liquid crystal display device and connection terminal positions of a driving external circuit, and FIG. 2 is a conceptual diagram of a liquid crystal display device using the same.

First, the configuration of the TFT array substrate will be described with reference to FIG.

A gate line 13 and a drain line 14 are formed in a matrix on a glass substrate 11 with a gate insulating film or a semiconductor layer and a gate insulating film interposed therebetween, and a TFT 12 is formed near each intersection. And
The TFT 12 has a pixel electrode 15 for applying a voltage to the liquid crystal.
, And the gate line 13 and the drain line 14 are connected to a gate terminal 21 and a drain terminal 22, respectively.

Next, the structure and operation of a liquid crystal display device using the above-described TFT array substrate will be described with reference to FIG.

Rubbed TFT with printed alignment film
An array substrate 31 and a counter substrate 32 on which the same operation is performed are provided with a sealing material 35 and a spacer 3 via a liquid crystal 33.
6, the TFT array substrate 31, the opposing substrate 3
A polarizing plate 34 is attached to both 2. And
A liquid crystal driving external circuit 37 is mounted on a part of the TFT array substrate 31, and a signal substrate 39 is further connected to the external circuit 37, and a backlight 38 is installed near the TFT array substrate 31. The backlight 38 is turned on, and the signal sent from the signal substrate 39 is converted by the liquid crystal driving external circuit 37 on each of the gate terminal side and the drain terminal side, and the TFT
A signal is sent to the array substrate 31 to operate the TFT, a voltage is applied to the pixel electrode, a potential difference occurs between the TFT array substrate 31 and the opposing substrate 32, and the liquid crystal 33 operates to enable display.

Here, regarding the structure of the TFT array substrate and the method of manufacturing the same, an inverted staggered channel dug type TFT will be described.
Will be described as an example.

FIG. 3 is a plan view of one pixel portion including the above-described TFT. FIG. 4A is a plan view of the gate terminal, and FIG. 4B is a cross-sectional view taken along line AA ′ of FIG. 4A. FIG. 5A is a plan view of the drain terminal.
FIG. 5B is a cross-sectional view taken along line AA ′ of FIG. Also,
FIG. 6 is a sectional view taken along the line AA 'of FIG.

First, a high-melting-point low-resistance metal, for example, molybdenum that is susceptible to corrosion under high temperature and high humidity, is formed in a thickness of about 300 nm by sputtering, and is formed by photolithography and etching as shown in FIG.
The gate electrode 16 and the gate wiring 13 in (b) are formed. At the same time, the gate lead-out wiring / terminal light shielding layer 41 in FIGS. 4A and 4B and the terminal light shielding layer 47 in FIGS. 5A and 5B are formed. The shape of the terminal light-shielding layer in the terminal portion is substantially the same as the terminal shape, and the shape is extended to the contact hole 46, and the terminal light-shielding layer is electrically connected to the transparent conductive film 43 later.

Next, for example, by the plasma CVD method,
A gate insulating film made of silicon nitride or silicon oxide is formed to a thickness of about 500 nm. Furthermore, plasma CVD
The semiconductor film is formed to a thickness of about 300 nm and the n + semiconductor film is formed to a thickness of about 50 nm by the method. Subsequently, the semiconductor layer 19 and n + in FIG. 6 are formed by photolithography and etching.
The semiconductor layer 49 is formed in an island shape. At the same time, the semiconductor layer and the n + semiconductor layer formed on the terminals shown in FIGS. 4A and 4B and FIGS. 5A and 5B are all etched.

Next, a transparent conductive film, for example, indium tin oxide having a thickness of about 50 nm is formed by sputtering, and the pixel electrode 18 in FIGS. 3 and 6 is formed by photolithography and etching. At the same time, FIG.
A transparent conductive film 43 shown in FIGS. 5A and 5B and FIGS. 5A and 5B is formed.

Next, contact holes 46 in FIGS. 4A and 4B and FIGS. 5A and 5B are formed by photolithography and etching. At this time, FIG.
The pixel portion including the TFT shown in FIG. 6 is entirely covered with the photoresist and is not etched.

Next, the gate electrode 16 and the gate wiring 13
Similarly, the drain electrode 18, the source electrode 17, and the drain wiring 14 in FIGS. 3 and 6 are formed. At the same time, the gate lead-out wiring and the transparent conductive film connecting metal 44 shown in FIGS.
(B) The drain lead-out wiring 48 in FIG.

Next, the drain electrode 18 and the source electrode 17
Using the as a mask, the n + semiconductor film is etched to form the n + semiconductor layer 49 in FIG.

Finally, for example, silicon nitride is used as a passivation film for about 200 n
m, and a passivation film opening 20 in FIG. 3 is formed by photolithography and etching.
Complete the array substrate. At the same time, FIG.
(A), the gate terminal 21 in (b) and FIG.
The drain terminal 22 in (b) is exposed. Thus, a terminal light-shielding layer having substantially the same shape as the terminal is provided via the gate insulating film, and the terminal light-shielding layer is a single-layer transparent conductive film gate terminal electrically connected to the transparent conductive film at the contact hole portion. 21 and the drain terminal 22 are completed in the same number of steps as in the manufacture of the TFT array substrate.

FIG. 7A is a plan view of a gate terminal portion of the second example, and FIG. 7B is a cross-sectional view taken along the line AA 'of FIG. 7A. The difference from the first example is that the gate terminal 2
1 is also connected to the gate lead-out wiring / terminal light-shielding layer 41 at the end. Although the drain terminal is not shown, the difference from the first example is the same item as the gate terminal.

For the second example, FIGS. 2, 4 (a),
(B), FIGS. 7 (a), (b), FIGS. 8 and 9 (a),
This will be described with reference to FIG.

First, generally, as shown in FIG. 8, in one liquid crystal display device, a gate terminal side liquid crystal driving external circuit 51 and a drain terminal side liquid crystal driving external circuit 52 are provided on each of a gate side and a drain side. Are used several by one, and FIG.
It is implemented in the area of X1 in the middle. Further, since each of these is mounted on the TFT array substrate one by one, if the mounting position thereof is shifted in the direction of the double arrow in FIG.
The resistance between the T array and the external circuit for driving the liquid crystal also differs from one another, which may cause display unevenness at the boundary between the external circuits for driving the liquid crystal, and strict positional accuracy is required. Further, if the external circuit for driving the liquid crystal is simply mounted in the area X2 in FIG. 9, the positional accuracy is relaxed. At this time, the external circuit for driving the liquid crystal 37 in FIG. 2 moves to the left. At the time of mounting, there occurs a problem that the polarizing plate 34 on the counter substrate 32 side is scorched.

Next, as a terminal structure, as shown in FIGS. 9A and 9B, a case where a metal capable of forming a laminated structure of the transparent conductive film 43 and the gate lead-out line 61 can be used, and FIG. Compare with a) and (b). In the first example, the specific resistance value of the transparent conductive film 43 is larger than that of the transparent conductive film 43 laminated with the gate lead-out line 61 in FIG. External circuit 51
Alternatively, stricter positional accuracy is required for display unevenness due to a shift in the mounting position of the drain terminal side liquid crystal driving external circuit 52.

Therefore, in FIGS. 7A and 7B of the second example, a gate lead-out wiring / terminal light-shielding layer 41 and a transparent conductive film 43 formed of a high melting point and low resistance metal are connected to an external liquid crystal driving circuit. Are electrically connected at both ends covered with the passivation film outside the mounting region of the above, so that the gate lead-out wiring / terminal light-shielding layer 41 becomes the wiring of the terminal portion.
The thickness of the transparent conductive film 43 is set to 50 nm, and the specific resistance is set to 200 micro ohm centimeter. When the thickness of the gate lead-out / terminal light-shielding layer 41 is 300 nm and the specific resistance is 10 μOhm / cm, the wiring resistance of the transparent conductive film 43 is equal to that of the gate lead-out / terminal-light-shielding layer 41. Double. Since the transparent conductive film 43 and the gate lead line / terminal light-shielding layer 41 are provided via the gate insulating film 42, they are connected in parallel in an electric circuit, and the contact on the end side of the gate terminal 21 is formed. Most of the current flows through the gate lead line and light shielding layer 41 through the hole 46.

FIG. 11 shows this example in terms of an electric circuit. The current flows through the gate lead line / light shielding layer 41 at a ratio of about 1: 120.

As described above, the terminal light-shielding layer formed of a low-resistance metal and the transparent conductive film are electrically connected at both ends covered with the passivation film outside the mounting region of the liquid crystal driving external circuit. With this structure, it is possible to prevent display unevenness due to a shift in the mounting position of the gate terminal side liquid crystal driving external circuit or the drain terminal side liquid crystal driving external circuit. Further, it is possible to improve the quality with respect to the display unevenness as compared with a liquid crystal display device in which the transparent conductive film 43 and the lead wiring 61 are directly laminated as shown in FIG.

In the above-described first and second examples, a description has been given of a TFT array substrate in which a liquid crystal is operated by applying a voltage between the TFT array substrate and the counter substrate. The opposing electrode is formed in a comb shape, and a voltage is applied between these to operate the liquid crystal (IP
S: TFT of In Plane Switching)
It goes without saying that the present invention can be applied to an array substrate.

In the first and second examples, the transparent conductive film and the light-shielding layer of the terminal portion have substantially the same shape. However, the light-shielding layer only has to be a mark when mounting an external circuit for driving a liquid crystal. Different shapes may be used. For example, as shown in FIG. 12, the width of the terminal light shielding layer 41 may be smaller than the width of the transparent conductive film 43.

Further, as a modification of the present invention, as shown in FIG. 13, a structure in which a connection metal 44 extends on one or both sides of the transparent conductive film 43 of the terminal portion may be adopted.

[0040]

As described above, the present invention has a terminal structure of a single transparent conductive film having a terminal light-shielding layer having substantially the same shape as the terminal via the gate insulating film. When connecting an external circuit for driving a liquid crystal to transparent gate and drain terminals on a TFT array substrate using a high melting point low resistance metal that is susceptible to corrosion, such as molybdenum, tungsten, or an alloy thereof, as a gate wiring or a drain wiring. In addition, the terminal shape can be recognized, and an external circuit for driving a liquid crystal can be mounted by optically confirming the terminal pattern.

Further, according to the present invention, the terminal light-shielding layer is electrically connected to the transparent conductive film at the contact hole portion and has the same potential, so that electrostatic breakdown between the terminal light-shielding layer and the transparent conductive film is suppressed. Thus, when the drain electrode, the source electrode, and the drain wiring are formed by wet etching, it is possible to prevent an etchant from penetrating from the electrostatic breakdown mark and etching the terminal light-shielding layer.

Further, according to the present invention, since an alignment mark for mounting an external circuit for driving a liquid crystal is unnecessary, a short circuit between terminals due to an alignment mark induced at the time of high-density mounting can be prevented.

In addition, according to the present invention, an external circuit for driving a liquid crystal can be mounted by optically confirming the terminal pattern without increasing the number of manufacturing steps.

[Brief description of the drawings]

FIG. 1 is a diagram showing connection terminal positions of a TFT array substrate and a driving external circuit.

FIG. 2 is a diagram conceptually showing a liquid crystal display device.

FIG. 3 is a plan view showing a pixel portion on the thin film transistor array substrate.

4A and 4B are diagrams for explaining a gate wiring side terminal portion, wherein FIG. 4A is a plan view of a gate terminal, and FIG.
It is A 'line sectional drawing.

5A and 5B are diagrams for explaining a drain wiring side terminal portion, wherein FIG. 5A is a plan view of a drain terminal, and FIG.
It is A 'line sectional drawing.

FIG. 6 is a sectional view taken along line AA ′ of FIG. 3;

FIGS. 7A and 7B are diagrams for explaining a second example of the gate terminal portion, where FIG. 7A is a plan view and FIG. 7B is a cross-sectional view along the line AA ′.

FIG. 8 is a view schematically showing a position where an external circuit for driving liquid crystal is installed in the liquid crystal display device.

9A and 9B are diagrams for explaining a conventional one-gate-wiring-side terminal portion, where FIG. 9A is a plan view and FIG. 9B is a cross-sectional view taken along line AA ′.

FIG. 10 is a cross-sectional view illustrating a conventional two-gate-wire-side terminal portion.

FIG. 11 is a diagram showing an equivalent circuit of the example shown in FIG. 7;

FIG. 12 is a plan view showing a third example of the gate wiring side terminal portion.

FIG. 13 is a plan view showing a modification of the example shown in FIG.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 11 Transparent glass substrate 12 Thin film transistor (TFT) 13 Gate wiring 14 Drain wiring 15 Pixel electrode 16 Gate electrode 17 Source electrode 18 Drain electrode 19 Semiconductor layer 20 Passivation film opening 21 Gate terminal 22 Drain terminal 31 TFT array substrate 32 Counter substrate 33 Liquid crystal 34 Polarizing Plate 35 Sealing Material 36 Spacer 37 External Circuit for Driving Liquid Crystal 38 Backlight 39 Signal Substrate 40 n + Semiconductor Layer 41 Gate Lead-out Wiring / Terminal Shading Layer 42 Gate Insulating Film 43 Transparent Conductive Film 44 Gate Lead-Out Wiring and Transparent Conductive Film Connection metal 45 Passivation film 46 Contact hole 47 Terminal light shielding layer 48 Drain lead-out wiring 51 Gate terminal side liquid crystal driving external circuit 52 Drain terminal side liquid crystal driving external circuit 53 Liquid crystal display device Display region 61 a gate lead-out lines 62 gate lead wiring capping metal 63 electrode 64 of aluminum oxide

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 2H091 FA35Y FC26 GA07 GA13 LA04 LA07 LA30 2H092 GA29 HA28 JA26 JA34 JA37 JA41 JA46 JB52 JB57 KB24 MA05 MA13 MA17 MA14 NA14 PA03 PA06 PA11 PA13 5F110 AA22 CC07 DD02 EE04 EE06 EE36 EE37 FF FF30 GG24 GG45 HK04 HK06 HK08 HM18 HM19 NN02 NN04 NN24 NN35 NN44 NN46 QQ05

Claims (6)

[Claims] 1. A thin film transistor array substrate in which a terminal electrode portion for mounting an external circuit for driving a thin film transistor is formed of a single layer of a transparent conductive film by using a metal which is susceptible to corrosion under high temperature and high humidity for a gate wiring or a drain wiring. 2. The thin film transistor array substrate according to claim 1, wherein a terminal light-shielding layer is provided below the terminal electrode portion via an insulating film. 2. The thin film transistor array substrate according to claim 1, wherein the terminal light-shielding layer is electrically connected to a transparent conductive film of the terminal electrode portion. 3. The thin film transistor array substrate according to claim 1, wherein the metal which is susceptible to corrosion under high temperature and high humidity is molybdenum, tungsten, or molybdenum or a tungsten alloy. substrate. 4. A thin film transistor array substrate in which a terminal electrode portion for mounting an external circuit for driving a thin film transistor is formed of a single layer of a transparent conductive film, using a metal which is likely to cause corrosion under high temperature and high humidity for a gate wiring or a drain wiring. Wherein the terminal light-shielding layer is formed below the terminal electrode portion via an insulating film, and the terminal light-shielding layer is formed in the same step as the gate wiring. Substrate manufacturing method. 5. The thin film transistor array substrate according to claim 4, wherein the terminal light-shielding layer is electrically connected to a transparent conductive film of the terminal electrode portion. Manufacturing method. 6. The method of manufacturing a thin film transistor array substrate according to claim 4, wherein the metal which is susceptible to corrosion under high temperature and high humidity is molybdenum, tungsten, or molybdenum or a tungsten alloy. Of manufacturing a thin film transistor array substrate.