KR20020027731A - A method for fabricating array substrate for liquid crystal display device and the same - Google Patents

Abstract

PURPOSE: A method for fabricating an array panel for LCD(Liquid Crystal Display) devices is provided to interpose an oxide between a first and a second metal layers configuring a gate wire, to allow a developer removing photo-resist to cut off the first metal layer, thereby preventing galvanic corrosion of wires caused by the developer. CONSTITUTION: A substrate(111) is arranged. A first conductive metal layer made of aluminum having low resistance is formed on the substrate(111). An oxide is formed on a surface of the first conductive metal layer. A second conductive metal layer having high corrosion resistance is formed on the substrate(111), in which the oxide is formed. The second conductive metal layer and the first conductive metal layer are simultaneously patterned, to form a gate wire(113) and a gate electrode(126) in a structure of accumulating the first conductive metal layer, an insulating layer and the second conductive metal layer. A data wire(115), defining a pixel area by crossing the gate wire(113) centered on a gate insulating layer, a source electrode(159) and a drain electrode(161) are formed. An active layer is configured between the gate insulating layer and the source and drain electrodes(159,161). And a pixel electrode(171) contacting with the drain electrode(161) is formed.

Description

A method for fabricating array substrate for liquid crystal display device and the same}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device. More particularly, the present invention relates to a structure in which a galvanic phenomenon does not occur when a signal wiring formed in an array substrate is formed.

In general, a liquid crystal display device is an apparatus for expressing an image using optical anisotropy of a liquid crystal, and is mainly composed of an upper substrate, a lower substrate, and a liquid crystal positioned between two substrates.

A description with reference to FIG. 1 is as follows.

1 is an exploded perspective view schematically illustrating a general liquid crystal display device.

As shown in the drawing, a general liquid crystal display includes a color filter 7 including a black matrix 6 and a sub-color filter (red, green, blue) 8 and an upper portion on which a transparent common electrode 18 is formed on the color filter. And a lower substrate 22 having an array wiring including a substrate 5, a pixel region P and a pixel electrode 17 formed on the pixel region, and a switching element T. The upper substrate 5 and The liquid crystal 14 is filled between the lower substrates 22.

The lower substrate 22 is also referred to as an array substrate, and the thin film transistor T, which is a switching element, is positioned in a matrix type, and the gate wiring 13 and the data wiring 15 passing through the plurality of thin film transistors cross each other. Is formed.

The pixel area P is an area defined by the gate line 13 and the data line 15 intersecting each other. The pixel electrode 17 formed on the pixel region P uses a transparent conductive metal having relatively high light transmittance, such as indium-tin-oxide (ITO).

In the liquid crystal display device configured as described above, the liquid crystal layer 14 disposed on the pixel electrode 17 is oriented by a signal applied from the thin film transistor T, and the liquid crystal layer is aligned according to the degree of alignment of the liquid crystal layer. The image can be represented in a manner that controls the amount of light that passes through layer 14.

The gate wiring 13 transfers a pulse voltage driving a gate electrode, which is a first electrode of the thin film transistor T, and the data wiring 15 receives a source electrode, which is a second electrode of the thin film transistor T. It is a means for transmitting the driving signal voltage.

The signal is applied to the liquid crystal through the pixel electrode through the drain electrode, and the liquid crystal is oriented according to the applied signal so that the image can be displayed by controlling the amount of light incident from the lower backlight to be emitted to the outside. have.

2 is an enlarged plan view showing some pixels of an array substrate for a liquid crystal display device.

As shown, the array substrate 22 is composed of a plurality of pixel regions P, and pixels include a thin film transistor T, a pixel electrode 17, and a storage capacitor as switching elements. It consists of an storage capacitor (C).

The thin film transistor T includes a gate electrode 26, a source electrode 28, a drain electrode 30, and an active layer 55. The source electrode 28 is a data line 15. The gate electrode 13 is connected to the gate line 13 crossing the data line 15 to define the pixel area P.

In this case, the data line 15 is formed to overlap the active layer 55 in a planar manner, and the storage capacitor C is a storage on gate structure, and a metal connected to the pixel electrode 17. The electrode layer 15 'and the lower gate wiring 13 become upper and lower electrodes of the storage capacitor and are formed of M / I / M (metal / insulator / metal). In this case, the location and configuration of the storage capacitor may vary.

The manufacturing process of the lower substrate 22 manufactured as described above is often determined by what material is used for each device to be made or designed according to the specification.

For example, in the past, a small liquid crystal display was not a problem, but in the case of a large area liquid crystal display of 12 inches or more, the intrinsic resistance of the material used for the gate wiring is an important factor in determining the superiority of the image quality. Therefore, in the case of a large area liquid crystal display element, it is preferable to use a metal with low resistance, such as aluminum or an aluminum alloy.

Hereinafter, a method of manufacturing an array substrate will be described with reference to FIGS. 3A to 3C.

3A to 3C are process cross-sectional views cut along the line II-II ′ of FIG. 2 and described in the order of the processes, and the steps up to the process of forming the gate wiring and the gate electrode are described.

As shown in FIG. 3A, first, aluminum (Al) or aluminum alloy (AlNd) is deposited on the substrate 22 to form the first conductive metal layer 31. Next, molybdenum is deposited on the first conductive metal layer to form a second conductive metal layer 33.

As such, the reason for forming the gate wiring as the double metal layer is as follows.

In order to reduce the RC delay which is important for the operation of the liquid crystal display device, aluminum having a low resistance as the gate wiring metal is the mainstream, but pure aluminum has a weak chemical corrosion resistance, cause wiring defects due to hillock formation,

Therefore, as described above, in the case of aluminum wiring, it may be used in the form of an alloy or a laminated structure may be applied.

At this time, it is preferable that the thickness of the second metal layer is thinly formed at about 500 kPa.

Next, as shown in FIG. 3B, a photoresist is deposited on the entire surface of the substrate 22 on which the second metal layer 33 is formed to form a PR layer 35, and a mask. Exposure processing using the above step is performed.

After the exposure process, a process of developing an exposed portion of the photoresist is performed. At this time, a photoresist of the exposed portion is removed using a developer.

Next, as shown in FIG. 3C, the exposed portion of the PR layer is etched to expose a portion of the second metal layer.

Next, the second metal layer 33 and the lower first metal layer 31 are patterned to form a plurality of gate wirings 13 extending in one direction, and a gate electrode protruding and extending from the gate wiring to a predetermined area. 26).

Next, a process of removing the photoresist 35 ′ remaining on the gate wiring 13 and the gate electrode 26 is performed.

In this process, since the second metal layer forming the gate wiring is thin, the first metal layer, which is made of aluminum, is partially exposed to the lower portion of the second metal layer due to a defect appearing in the deposition process.

At this time, in the process of exposing and developing the photoresist, galvanic corrosion occurs between aluminum exposed by the developer and the molybdenum.

Galvanic phenomena are potential differences when two dissimilar metals are immersed in a solution, and thus electrons move between them, and the corrosion rate of metals with a negative potential is reduced and the corrosion of metals with active potentials is reduced. Speed is accelerated. In other words, the former becomes a cathode and the latter becomes an anode.

Corrosion caused by this phenomenon is called galvanic corrosion.

Therefore, in the conventional gate wiring structure, due to the corrosion of the wiring during the process of patterning the gate wiring, a light leakage phenomenon occurs in which light generated from the backlight configured under the liquid crystal panel is transmitted to the corroded portion of the wiring.

Accordingly, in order to solve the above problems, the present invention provides the first metal layer from a developing solution which removes the photoresist through an oxide film between the first metal layer and the second metal layer constituting the gate wiring. The purpose of the present invention is to prevent corrosion of the wiring due to the galvanic phenomenon between two dissimilar metals generated by the developer.

1 is an exploded perspective view showing a general color liquid crystal display device;

2 is an enlarged plan view showing some pixels of a conventional array substrate for a liquid crystal display device;

3A to 3C are cross-sectional views taken along the line II-II ′ of FIG. 2 and shown according to a conventional process sequence.

4A to 4F are cross-sectional views taken along the line II-II ′ of FIG. 2 and shown in the process sequence of the present invention.

<Brief description of symbols for the main parts of the drawings>

113: gate wiring 115: data wiring

126: gate electrode 159: source electrode

161: drain electrode 165: protective layer

167: drain contact hole 169: storage contact hole

171 pixel electrode

According to another aspect of the present invention, there is provided an array substrate for a liquid crystal display device, the method including: providing a substrate; Forming a first aluminum-based conductive metal layer having low resistance on the substrate; Forming an oxide film on the first conductive metal layer; Forming a second corrosion resistant metal layer on the substrate on which the oxide film is formed; Depositing a photoresist on the second conductive metal layer to form a PR layer; The PR layer is subjected to a mask exposure to simultaneously etch the exposed second conductive metal layer and the first conductive metal layer below to form a gate wiring and a gate electrode in which the first conductive metal layer / insulating film / second conductive metal layer is stacked. Making a step; Forming a data wiring, a source electrode and a drain electrode to define a pixel region by crossing the gate wiring and a gate insulating layer therebetween; Forming an active layer formed between the gate insulating film and the source and drain electrodes; Forming a pixel electrode in contact with the drain electrode.

The active layer is composed of amorphous silicon (a-Si: H).

Preferably, the insulating film is made of aluminum oxide (Al ₂ O ₃ ).

The second metal layer is deposited to a thickness in the range of 500 kPa to 600 kPa.

The second metal layer is formed by depositing one selected from the group of conductive metals composed of molybdenum (Mo), tungsten (W), and copper (Cu).

An array substrate for a liquid crystal display device according to a feature of the present invention includes a substrate; A gate wiring and a gate electrode formed on the substrate and composed of the first conductive metal layer / insulating film / second conductive metal layer; A data wiring formed by crossing the gate wiring and the insulating layer therebetween, a source electrode connected to the data wiring, and a drain electrode; An island-like semiconductor layer formed to overlap the source electrode, the drain electrode, and the gate electrode at the same time; And a pixel electrode in contact with the drain electrode.

The first conductive metal layer is formed by depositing one selected from the group of low resistance conductive metals composed of aluminum and an aluminum alloy.

Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings.

Example

In order to prevent galvanic corrosion, an embodiment of the present invention proposes a structure and a method of interposing an oxide film between metal wirings of a double layer constituting the gate wiring.

Hereinafter, a process of forming an inverted staggered thin film transistor having a back channel etch (BCE) structure will be described as an example.

4A through 4F are cross-sectional views taken along the line II-II ′ of FIG. 2 and according to the process sequence of the present invention.

First, as shown in FIG. 4A, an aluminum-based metal is deposited on a transparent substrate 111 to form a first conductive metal layer 131.

Next, an aluminum oxide (Al ₂ O ₃ ) layer 133 is formed on the first conductive metal layer 131. The aluminum oxide may be formed in various ways, and in the present invention, aluminum oxide is formed on the surface of the aluminum-based metal using O ₂ plasma in a sputter chamber.

In addition to the aluminum oxide, an insulating film may be formed by depositing a silicon oxide film (SiO ₂ ) or a silicon nitride film (SiO ₂ ).

Next, as shown in FIG. 4B, a second conductive metal layer 135 is formed by depositing a conductive metal layer including molybdenum (Mo) and chromium (Cr) on the entire surface of the substrate 111 on which the aluminum oxide layer 133 is formed. To form.

At this time, the second conductive metal layer is deposited to a thickness of 500 kPa to 600 kPa.

Next, a photoresist is deposited on the conductive metal layer to form a PR layer 137.

Next, as shown in FIG. 4C, the PR layer 137 is subjected to a mask exposure process to remove the exposed portion, and partially expose the lower second metal layer 135.

Next, as shown in FIG. 4D, first, the exposed second metal layer (135 of FIG. 4C), the insulating film (133 of FIG. 4C) below the second metal layer, and the first metal layer (FIG. 4C) below the insulating film The 131 is collectively etched to form the gate electrode 126 and the gate wiring 113 formed of the first metal layer / insulating film / second metal layer.

As shown in FIG. 4E, an inorganic insulating material group including a silicon nitride film (SiN _x ), a silicon oxide film (SiO ₂ ), and the like on the entire surface of the substrate 111 on which the gate electrode 126 and the gate wiring 113 are formed. And one selected from the group of organic insulating materials including benzo cyclobutene, acryl-based resin, and the like, to form a gate insulating layer 128.

Subsequently, pure silicon and impurities containing amorphous silicon are deposited on the gate insulating layer 128 and patterned to form an active layer 155 and an ohmic contact layer 156 overlying the gate electrode 126 in an island form. ).

Next, as illustrated in FIG. 4F, a conductive metal group including molybdenum (Mo), tungsten (W), chromium (Cr), and the like on the entire surface of the substrate 111 on which the ohmic contact layer 156 is formed on the uppermost layer. After depositing a selected one of the pattern pattern, the source and drain electrodes 159, 161 and the source electrode 161 that extends at a predetermined interval on both sides of the ohmic contact layer (ohmic contact layer) extends vertically and the gate wiring The data line 115 defining the pixel area is formed to intersect with 113.

At the same time, an island-type source / drain metal layer 163 is formed on the gate wiring 113 serving as the storage first electrode.

Next, a protective layer 165 is formed by depositing or applying the above-described insulating material on the substrate 111 on which the source and drain electrodes 159 and 161 are formed, and then patterning the pattern on the drain electrode 161. The storage contact hole 169 is formed on the drain contact hole 167 and the source / drain metal layer 163.

Next, a transparent conductive metal group including indium-tin-oxide (ITO) and indium-zinc-oxide (IZO), etc., is formed on the patterned protective layer 165. A pixel is deposited and patterned so that one side contacts the drain electrode 161 through the drain contact hole 167, and the other surface contacts the source / drain metal layer 163 through the storage contact hole 169. The electrode 171 is formed.

In this case, the source / drain metal layer 163 functions as a second electrode of the storage capacitor constituting the storage capacitor together with the lower gate wiring that is the first electrode of the storage capacitor.

Such a method can produce an array substrate for a liquid crystal display device according to the present invention.

In the present invention, the development of the photoresist used to pattern the second metal layer even if a defect occurs on the surface of the second metal layer via an oxide film between the first metal layer and the second metal layer constituting the gate wiring. Since the solution is blocked from contacting the first metal layer through the defect of the second metal layer, it is possible to prevent light leakage caused by galvanic corrosion between the first metal layer and the second metal layer by the photoresist developer. It has the effect of improving the yield of the product.

Claims (13)

Providing a substrate; Forming a first aluminum-based conductive metal layer having low resistance on the substrate; Forming an oxide film on a surface of the first conductive metal layer; Forming a second corrosion resistant metal layer on the substrate on which the oxide film is formed; Simultaneously patterning the second conductive metal layer and the first conductive metal layer thereunder to form a gate wiring and a gate electrode having a structure in which a first conductive metal layer / insulating film / second conductive metal layer is stacked; Forming data lines, a source electrode, and a drain electrode to define a pixel area by crossing the gate line and the gate insulating layer therebetween; Forming an active layer formed between the gate insulating film and the source and drain electrodes; Forming a pixel electrode in contact with the drain electrode Array substrate manufacturing method for a liquid crystal display device comprising a. The method of claim 1, And the active layer is formed of amorphous silicon (a-Si: H). The method of claim 1, The insulating layer is an aluminum oxide (Al ₂ O ₃ ) array substrate manufacturing method for a liquid crystal display device. The method of claim 1, And a thickness of the second conductive metal layer is 500 kW to 600 kW. The method of claim 1, And the second conductive metal layer is one selected from a group of conductive metals composed of molybdenum (Mo) and tungsten (W). The method of claim 1, And the pixel electrode is one selected from a group of transparent conductive metals consisting of ITO and IZO. A substrate; A gate wiring and a gate electrode formed on the substrate and composed of the first conductive metal layer / insulating film / second conductive metal layer; A data wiring formed by crossing the gate wiring and the insulating layer therebetween, a source electrode connected to the data wiring, and a drain electrode; An island-like semiconductor layer formed to overlap with the source electrode, the drain electrode, and the gate electrode; A pixel electrode in contact with the drain electrode Array substrate for a liquid crystal display device comprising a. The method of claim 7, wherein And the first conductive metal layer is one selected from the group of low resistance conductive metals composed of aluminum and aluminum alloy. The method of claim 7, wherein And the active layer is formed of amorphous silicon (a-Si: H). The method of claim 7, wherein The insulating layer is an aluminum oxide (Al ₂ O ₃ ) array substrate for a liquid crystal display device. The method of claim 7, wherein An array substrate for liquid crystal display devices, wherein the second conductive metal layer has a thickness of 500 kPa to 600 kPa. The method of claim 7, wherein And the second conductive metal layer is one selected from a group of conductive metals composed of molybdenum (Mo) and tungsten (W). The method of claim 7, wherein And the pixel electrode is one selected from a group of transparent conductive metals composed of ITO and IZO.