CN1845310A - Method for manufacturing pixel array substrate - Google Patents
Method for manufacturing pixel array substrate Download PDFInfo
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- CN1845310A CN1845310A CN 200610058401 CN200610058401A CN1845310A CN 1845310 A CN1845310 A CN 1845310A CN 200610058401 CN200610058401 CN 200610058401 CN 200610058401 A CN200610058401 A CN 200610058401A CN 1845310 A CN1845310 A CN 1845310A
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- 229920002120 photoresistant polymer Polymers 0.000 claims description 29
- 238000000059 patterning Methods 0.000 claims description 27
- 239000000463 material Substances 0.000 claims description 23
- 238000002161 passivation Methods 0.000 claims description 21
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- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 7
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 6
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- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 6
- 229910052719 titanium Inorganic materials 0.000 description 6
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- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
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Abstract
The manufacture method for a pixel array substrate comprises: first, forming multiple grids, scanning lines, data wire designs, and pixel electrode designs; then, forming multiple channels on grid and multiple contact hole openings to expose the wire design; forming multiple contact holes in the openings to electric connect with the wire design, source electric connected to the wire design, and drains electric connected with the pixel electrodes. This invention can improve the delay on signal transmission with low cost.
Description
Technical field
The present invention relates to a kind of manufacture method of semiconductor element substrate, and particularly relevant for a kind of manufacture method of image element array substrates.
Background technology
Along with the modern video development of technology, various display has been used on the display screen of consumption electronic products such as mobile phone, notebook computer, digital camera and PDA(Personal Digital Assistant) in large quantities.In these displays, because advantage such as that LCD (LCD) and organic electro-luminescent display (OLED) have is in light weight, volume is little and power consumption is low makes it become the main flow on the market.No matter be LCD or organic electro-luminescent display, its manufacturing process includes with semiconductor technology and forms image element array substrates.The shown color of each pixel in the corresponding adjustment image element array substrates, display can produce image.
Fig. 1 is the partial top view of known a kind of image element array substrates, and Fig. 2 A～2E is the generalized section of manufacturing process of the image element array substrates of Fig. 1, and its section line is the A-A ' line among Fig. 1.Please refer to Fig. 1, known image element array substrates 100 comprises a substrate 110 and is disposed at a plurality of thin-film transistors 120 on the substrate 110, multi-strip scanning line 130, many data wires 140 and a plurality of pixel electrode 150, wherein the grid 122 of each thin-film transistor 120, source electrode 124 and to drain 126 be to be electrically connected to corresponding scanning line 130, data wire 140 and pixel electrode 150 respectively.Generally speaking, these data wires 140 and scan line 130 are to be staggered with ranks, and define a plurality of pixel regions (not indicating).Particularly, scan line 130 is to arrange with column direction, and data wire 140 is to arrange with line direction, and thin-film transistor 120 is the confluces that are adjacent to scan line 130 and data wire 140.
Accept above-mentionedly, thin-film transistor 120 is sweep signals of coming according to scan line 130 transmission and determine it is to be in to open or closing state.When thin-film transistor 120 was in the state of unlatching, pixel electrode 150 can receive via thin-film transistor 120 by data wire 140 and transmit the data-signal of coming, so that the color that corresponding pixel adjustment shows.Because technologic consideration, the thickness of data wire 140 can be less than the thickness of scan line 130 usually, so makes the face resistance of data wire 140 greater than the face resistance of scan line 130.This can cause the phenomenon of data-signal propagation delay, thereby reduces the display quality of image element array substrates 100.Particularly, can make that the phenomenon of data-signal propagation delay is even more serious along with image element array substrates 100 sizes constantly increase.
Below, the manufacturing process with narration image element array substrates 100 please refer to Fig. 2 A, at first carries out one first road masking process on substrate 110, defining grid 122, and forms scan line 130 (as shown in Figure 1) simultaneously in this step.Please refer to Fig. 2 B, then on substrate 110, form a dielectric layer 160 with cover gate 122, and carry out one second road masking process to define a passage 128 in grid 122 tops.Please refer to Fig. 2 C, carry out one the 3rd road masking process afterwards to define source electrode 124, drain electrode 126 and data wire 140, wherein grid 122, source electrode 124, drain electrode 126 and passage 128 promptly constitute thin-film transistor 120.Please refer to Fig. 2 D, form a passivation layer 170 with cover film transistor 120 in substrate 110 tops again, and carry out one the 4th road masking process in passivation layer 170, to define a contact hole opening 172, to expose part drain electrode 126.Please also refer to Fig. 1 and Fig. 2 E, carry out one the 5th road masking process at last, to define pixel electrode 150 on passivation layer 170, wherein partial pixel electrode 150 is inserted contact hole opening 172, so that pixel electrode 150 is electrically connected at drain electrode 126.So far step is promptly finished the making of image element array substrates 100.
Accept above-mentioned, one of prime cost of making image element array substrates 100 is the manufacturing expense of mask, and known skill must use five different masks and carries out the five road masking process beginning and can form image element array substrates 100, so the manufacturing cost of image element array substrates 100 can't reduce.Particularly along with the increase of substrate size, must usable floor area bigger mask so more increases the cost of manufacture of image element array substrates 100 to form image element array substrates 100.
Summary of the invention
The technical problem to be solved in the present invention is: a kind of manufacture method of image element array substrates is provided, can reduces the cost of manufacture of image element array substrates, and improve the phenomenon of data-signal propagation delay.
For reaching above-mentioned or other purposes, the present invention proposes a kind of manufacture method of image element array substrates, at first on a substrate, form a transparency conducting layer and one first conductive layer in regular turn, and then carry out one first road masking process, with patterning first conductive layer and transparency conducting layer, and the multi-strip scanning line, a plurality of data wire pattern and a plurality of pixel electrode pattern that form a plurality of grids, electrically connect with these grids.Above substrate, form a dielectric layer and semi-conductor layer afterwards in regular turn, and carry out one second road masking process with pattern dielectric layer and semiconductor layer, and in each grid top formation one passage, and form and to expose a plurality of contact hole openings of these data wire patterns, and first conductive layer that removes these pixel electrode pattern is to form a plurality of pixel electrodes.Above substrate, form one second conductive layer subsequently, and second conductive layer can be inserted these contact hole openings and form a plurality of contact holes that electrically connect with these data wire patterns, and then carry out one the 3rd road masking process with patterning second metal level, and form a plurality of connecting portions of electrically connecting with these contact holes, a plurality of source electrodes that electrically connect with these data wire patterns and a plurality of drain electrodes that electrically connect with these pixel electrodes, and remove second conductive layer on each pixel electrode.Wherein, these data wire patterns that are positioned at identical delegation are to be electrically connected to each other by these connecting portions and these contact holes, to constitute a data wire.
In addition, for reaching above-mentioned or other purposes, the present invention proposes a kind of manufacture method of image element array substrates in addition, at first on a substrate, form a transparency conducting layer and one first conductive layer in regular turn, and then carry out one first road masking process, patterning first conductive layer and transparency conducting layer, and a plurality of scan line patterns, many data wires and a plurality of pixel electrode pattern that form a plurality of grids, electrically connect with these grids.Above substrate, form a dielectric layer and semi-conductor layer afterwards in regular turn, and then carry out one second road masking process, pattern dielectric layer and semiconductor layer, and in each grid top formation one passage, and form and to expose a plurality of contact hole openings of these scan line patterns, and first conductive layer that removes these pixel electrode pattern is to form a plurality of pixel electrodes.Above substrate, form one second conductive layer subsequently, and second conductive layer can be inserted these contact hole openings and form a plurality of contact holes that electrically connect with these scan line patterns, and then carry out one the 3rd road masking process, patterning second metal level, and form a plurality of connecting portions of electrically connecting with these contact holes, a plurality of source electrodes that electrically connect with these data wires and a plurality of drain electrodes that electrically connect with these pixel electrodes, and remove second conductive layer on each pixel electrode.Wherein, these scan line patterns that are positioned at mutually same row are to be electrically connected to each other by these connecting portions and these contact holes, to constitute the one scan line.
In one embodiment of this invention, after the 3rd above-mentioned road masking process, more comprise the following steps: at first above substrate, to form in regular turn a passivation layer and a photoresist layer, be mask then with these grids, source electrode, drain electrode, scan line and data wire, carry out a back-exposure technology and a developing process, to form a patterning photoresist layer.Be the mask etching passivation layer with the patterning photoresist layer afterwards,, remove the patterning photoresist layer at last to expose pixel electrode.
In one embodiment of this invention, in the first above-mentioned road masking process, more comprise forming a plurality of weld pads, and each weld pad is an end that is connected in corresponding scanning line or data wire.In the second above-mentioned road masking process, more comprise the dielectric layer and the semiconductor layer of reserve part weld pad top, and remove first conductive layer of part of solder pads.In the 3rd above-mentioned road masking process, more comprise second conductive layer that removes the part of solder pads top.
In one embodiment of this invention, in the first above-mentioned road masking process, more comprise forming a plurality of bottom electrodes.In the second above-mentioned road masking process, more comprise keeping dielectric layer and the semiconductor layer that is positioned at these bottom electrode tops.In the 3rd above-mentioned road masking process, more comprise and form a plurality of top electrodes, be positioned on the semiconductor layer of part bottom electrode top, wherein, these bottom electrodes and these top electrodes constitute a plurality of capacitors, and each bottom electrode and corresponding scanning line electrically connect, and each top electrode and corresponding pixel electrode electric connection.
In one embodiment of this invention, in the 3rd above-mentioned road masking process, more comprise the segment thickness that removes these passages.
In one embodiment of this invention, above-mentioned semiconductor layer comprises a channel material layer and an ohmic contact material layer.
In one embodiment of this invention, the thickness of the first above-mentioned conductive layer is greater than the thickness of second conductive layer.
Comprehensively above-mentioned, in image element array substrates of the present invention and manufacture method thereof, because the material of data wire pattern and the material identical (being the material of first conductive layer) of scan line, and data wire is made of the data wire pattern, therefore the face resistance of data wire can be close with the face resistance of scan line, and then can improve the phenomenon of data-signal propagation delay.In addition, must use five masks to carry out for five road masking process beginnings compared to known skill and can make image element array substrates, the present invention only must use three masks to carry out three road masking process and promptly finish the making image element array substrates, so the cost of manufacture of image element array substrates can reduce.
Description of drawings
Fig. 1 is the partial top view of known a kind of image element array substrates.
Fig. 2 A～2E is the generalized section of manufacturing process of the image element array substrates of Fig. 1.
Fig. 3 is the partial top view according to the image element array substrates of one embodiment of the invention.
Fig. 4 A～4F is the generalized section of manufacturing process of the image element array substrates of Fig. 3.
Fig. 4 G～4J is the generalized section that forms the manufacturing process of passivation layer according to the image element array substrates of one embodiment of the invention.
Fig. 5 A and Fig. 5 B illustrate the vertical view after Fig. 4 B and Fig. 4 D technology respectively.
Fig. 6 is the partial top view according to the image element array substrates of another embodiment of the present invention.
The main element symbol description:
100: image element array substrates
110: substrate 120: thin-film transistor
122: grid 124: source electrode
126: drain electrode 128: passage
130: scan line 140: data wire
150: pixel electrode 160: dielectric layer
170: passivation layer 172: the contact hole opening
300,600: image element array substrates
310: substrate 320: active element
322: grid 324: source electrode
326: drain electrode 328: passage
330: scan line 340: data wire
342: data wire pattern 344: connecting portion
346: contact hole 350: pixel electrode
350 ': pixel electrode pattern 360: capacitor
362: bottom electrode 364: top electrode
370: weld pad 510: transparency conducting layer
532: contact hole opening 540: semiconductor layer
542: channel material layer 544: ohmic contact layer
570: photoresist layer 572: the patterning photoresist layer
630: scan line 632: scan line pattern
634: connecting portion 640: data wire
Embodiment
For technique scheme of the present invention, feature and advantage can be become apparent, preferred embodiment cited below particularly, and conjunction with figs. are described in detail below.
Fig. 3 is the partial top view according to the image element array substrates of one embodiment of the invention, and Fig. 4 A～4F is the generalized section of manufacturing process of the image element array substrates of Fig. 3, and its section line is B-B ' line and the C-C ' line among Fig. 3.Please refer to Fig. 3, image element array substrates 300 of the present invention comprises a substrate 310 and is disposed at a plurality of active elements 320 on the substrate 310, multi-strip scanning line 330, many data wires 340 and a plurality of pixel electrode 350 that wherein each active element 320 electrically connects with corresponding scanning line 330, data wire 340 and pixel electrode 350 respectively.In addition, each data wire 340 comprises a plurality of data wire patterns 342 and a plurality of connecting portion 344, wherein connecting portion 344 is and data wire pattern 342 electrically connects, and each connecting portion 344 can cross over wherein scan line 330, but does not electrically connect with scan line 330.
Particularly, data wire 340 is made of data wire pattern 342, and wherein data wire pattern 342 is identical with the material of scan line 330, and is to form simultaneously.For avoiding scan line 330 and data wire 340 to be short-circuited in the confluce, connecting portion 344 is to cross over scan line 330 to be electrically connected between the two adjacent data wire patterns 342.Thus, because data wire pattern 342 has the electrical characteristics identical with scan line 330, so the face resistance of data wire 340 integral body can be close with the face resistance of scan line 330, and then can improve the phenomenon of data-signal propagation delay.
In the present embodiment, active element 320 can be a thin-film transistor.In detail, the grid 322 of active element 320 is connected to corresponding scanning line 330, and the source electrode 324 of active element 320 is connected to corresponding data line 340, and the drain electrode 326 of active element 320 is connected to corresponding pixel electrode 350.In addition, image element array substrates 300 may further include a plurality of capacitors 360 and a plurality of weld pad 370 is disposed on the substrate 310, wherein capacitor 360 is to use so that pixel electrode 350 is kept stable voltage, and weld pad 370 is to be connected in a scan line 330 or an end of data wire 340, with as pin.
Below, will in detail the manufacturing process of image element array substrates 300 of the present invention be described in detail in conjunction with the accompanying drawings.Please refer to Fig. 4 A, at first on substrate 310, form a transparency conducting layer 510 and one first conductive layer 520 in regular turn, wherein the material of transparency conducting layer 510 can be tin indium oxide (Indium Tin Oxide, ITO) or indium zinc oxide (Indium Zinc Oxide, and the material of first conductive layer 520 can be selected from aluminium (Al), molybdenum (Mo), molybdenum nitride (MoN), titanium (Ti), titanium nitride (TiN), chromium (Cr), chromium nitride (CrN) or its combination IZO).In the present embodiment, first conductive layer 520 can be titanium nitride/aluminium/four layers of structure of piling up of titanium/titanium nitride, and wherein the preferred thickness of aluminium is between 500 ～2000 , and the preferred thickness of titanium or titanium nitride is between 300 ～1000 .
For making the accompanying drawing contrast clear, Fig. 5 A illustrates the vertical view after Fig. 4 B technology.Please refer to Fig. 4 B and Fig. 5 A, then carry out one first road masking process, the patterned transparent conductive layer 510 and first conductive layer 520, to form a plurality of grids 322, multi-strip scanning line 330, a plurality of data wire pattern 342 and a plurality of pixel electrode pattern 350 ', wherein each grid 322 electrically connects with corresponding scanning line 330.
Subsidiary one carry be, the first road masking process comprises prior to patterned transparent conductive layer 510 and first conductive layer, 520 tops and forms a photoresist layer (not illustrating), and utilizes a mask (not illustrating) that photoresist layer is carried out exposure imaging technology to form a patterning photoresist layer (not illustrating).Be that mask (cover curtain) carries out etching technics to the patterned transparent conductive layer 510 and first conductive layer 520 then, and define above-mentioned a plurality of element with the patterning photoresist layer.At last, the patterning photoresist layer is removed promptly finish the first road masking process.Those who are familiar with this art are when all no longer the detailed step of masking process being given unnecessary details more afterwards with reference to the detailed step of aforementioned and clear understanding masking process.
In addition, in this step of present embodiment, more can form a plurality of weld pads 370 and a plurality of bottom electrode 362 simultaneously, wherein bottom electrode 362 is the important components that constitute capacitor 360, and each bottom electrode 362 is to be electrically connected at corresponding scanning line 330.Subsidiary one carry be, be the aperture opening ratio that promotes image element array substrates 300, the present invention is not provided with a zone especially with ccontaining bottom electrode 362, but utilizes partly scan line 330 as bottom electrode 362.
Please refer to Fig. 4 C, form a dielectric layer 530 and semi-conductor layer 540 afterwards in regular turn above substrate 310, wherein the material of dielectric layer 530 for example is silicon nitride (SiN
x), silica (SiO
x) or silicon oxynitride (SiO
xN
y) with as insulating barrier.In addition, for promoting the electrical characteristics of semiconductor layer 540, in the present embodiment, semiconductor layer 540 can comprise a channel material layer 542 and an ohmic contact layer 544, wherein the material of channel material layer 542 for example is uncrystalline silicon (amorphous silicon, α-Si), and the material of ohmic contact layer 544 for example is heavily doped uncrystalline silicon (n+amorphoussilicon, n+ α-Si).
For making the accompanying drawing contrast clear, Fig. 5 B illustrates the vertical view after Fig. 4 D technology.Please refer to Fig. 4 D and Fig. 5 B, then carry out one second road masking process, pattern dielectric layer 530 and semiconductor layer 540, and form a passage 328 in each grid 322 top.In this step, also remove first conductive layer 520 of pixel electrode pattern 350 ' simultaneously, and the transparency conducting layer 510 that exposes pixel electrode 350 ' is to form a plurality of pixel electrodes 350.It should be noted that the present invention forms a plurality of contact holes (contact hole) opening 532 to expose data wire pattern 342 in dielectric layer 530 and semiconductor layer 540, wherein these contact hole openings 532 are positioned near the two ends of data wire pattern 342.Thus, can after technology in a plurality of data wire patterns 342 of identical delegation are electrically connected to form data wire 340 mutually.
In addition, in this step of present embodiment, can keep the part dielectric layer 530 and semiconductor layer 540 of weld pad 370 tops simultaneously, and remove part first conductive layer 520 of weld pad 370, to expose the partially transparent conductive layer 510 of weld pad 370.In addition, can also retain the dielectric layer 530 and semiconductor layer 540 of electrode 362 tops.
Please refer to Fig. 4 E, continue to form one second conductive layer 550 above substrate, and second conductive layer 550 can insert contact hole opening 532 and form a plurality of contact holes 346, wherein each contact hole 346 is and corresponding data line pattern 342 electrically connects.The material of second conductive layer 550 can be selected from aluminium (Al), molybdenum (Mo), molybdenum nitride (MoN), titanium (Ti), titanium nitride (TiN), chromium (Cr), chromium nitride (CrN) or its combination.In the present embodiment, second conductive layer 550 can be the structure of titanium/aluminium/titanium nitride three level stack, and wherein the preferred thickness of aluminium is between 500 ～2000 , and the preferred thickness of titanium or titanium nitride is between 300 ～1000 .In addition, the thickness of first conductive layer 520 for example is greater than second conductive layer 550.
Please refer to Fig. 4 F and Fig. 3, wherein Fig. 3 also is the vertical view after Fig. 4 F technology.Then carry out one the 3rd road masking process, patterning second conductive layer 550 and form a plurality of connecting portions 344, wherein connecting portion 344 is and corresponding contact hole 346 electrically connects.Thus, the data wire pattern 342 that is positioned at identical delegation can be electrically connected to each other with contact hole 346 by the connecting portion 344 of correspondence, with composition data line 340.Because data wire 340 is made of data wire pattern 342, and data wire pattern 342 has the electrical characteristics (be first conductive layer 520) identical with scan line 330, so the face resistance of data wire 340 integral body can be close with the face resistance of scan line 330.Therefore, the image element array substrates 300 that is disclosed the method made with the present invention can improve the phenomenon of data-signal propagation delay.
Accept above-mentionedly, in this step, also form source electrode 324 simultaneously and drain 326, wherein draining 326 is to be electrically connected to corresponding pixel electrode 324, and source electrode 324 is to be electrically connected to corresponding data line 342.Particularly, source electrode 324 is to be connected to corresponding connecting portion 344, and electrically connects with data wire pattern 342 by contact hole 346.Thus, grid 322, source electrode 324, drain electrode 326 promptly constitute active element 320 with passage 328.Subsidiary one carry be, the present invention also can remove the segment thickness of passage 328 simultaneously in this step, in detail, can remove the part ohmic contact layer 544 of passage 328, and expose the part channel material layer 542 of passage 328, to avoid source electrode 324 and to drain 326 phenomenons that are short-circuited.
It should be noted that so far step is promptly finished making image element array substrates 300 of the present invention.Because the present invention only uses three masks to carry out three road masking process and promptly finishes making image element array substrates 300, therefore can reduce the cost of manufacture of image element array substrates 300.
In addition, in this step of present embodiment, can form a plurality of top electrodes 364, and top electrode 364 is to be positioned on the semiconductor layer 540 of part bottom electrode 362 tops, and electrically connects with corresponding pixel electrode 350.Thus, bottom electrode 362 can constitute capacitor 360 so that pixel electrode 350 is kept stable voltage with top electrode 364.In addition, can also remove part second conductive layer 550 of weld pad 370 tops, and in the present embodiment, be that second conductive layer 550 with weld pad 370 tops Removes All.
For further promoting the quality of image element array substrates, the present invention can form passivation layer (protective layer) again to protect the element of its below, so that image element array substrates is not subject to ectocine and damages.Fig. 4 G～4J is the generalized section that forms the manufacturing process of passivation layer according to one embodiment of the invention, and wherein Fig. 4 G is a hookup 4F flow process afterwards.Please refer to Fig. 4 G, at first above substrate 310, form a passivation layer 560 and a photoresist layer 570, wherein the material of passivation layer 560 for example is silicon nitride, silica or silicon oxynitride, and in order to isolated extraneous, and the kenel of photoresist layer 570 for example is the eurymeric photoresist.Be mask then, photoresist layer 570 is carried out back-exposure technology with grid 322, source electrode 324, drain electrode 326, scan line (not illustrating), data wire 340 and other elements (as capacitor 360) with shaded effect.
Please refer to Fig. 4 H, afterwards photoresist layer 570 is carried out developing process, 570 of the part photoresist layers that wherein is not exposed can not be developed and form patterning photoresist layer 572.Constituted because the material of pixel electrode 350 is the transparency conducting layers 510 by light-permeable, therefore the photoresist layer 570 in pixel electrode 350 tops can be developed because of exposure, to expose passivation layer 560.Similar aforementioned, but because part of solder pads 370 tops do not have the element of shaded effect, so the passivation layer 560 of part of solder pads 370 tops also can be exposed.
Please refer to Fig. 4 I, is mask etching passivation layer 560 with patterning photoresist layer 572, to expose pixel electrode 350 and part of solder pads 370 subsequently.Please refer to Fig. 4 J, carry out stripping (stripper) technology at last to remove patterning photoresist layer 572, promptly to finish the making of image element array substrates 300 with passivation layer.It should be noted that in the process of above-mentioned formation passivation layer, is to carry out back-exposure technology with the element with shaded effect as mask to be finished, and does not therefore need additionally to set up mask, so can reduce the cost of manufacture of image element array substrates 300 again.
In the image element array substrates of previous embodiment, be data wire is electrically connected with the data wire pattern of a plurality of segmentations and to constitute, so can make data wire have the face resistance close to improve the phenomenon that the signal data postpones with scan line.But, aforesaid method is not in order to limiting the present invention, and for example, the present invention can also be resolved into scan line a plurality of scan line patterns, again these scan line patterns are electrically connected, below with the conjunction with figs. explanation.
Fig. 6 is the partial top view according to the image element array substrates of another embodiment of the present invention.Please refer to Fig. 6, the image element array substrates 600 of present embodiment is similar with image element array substrates 300 (as shown in Figure 3), its difference is that each scan line 630 comprises a plurality of scan line patterns 632 and a plurality of connecting portion 634, wherein connecting portion 634 is to electrically connect with scan line pattern 632, and each connecting portion 634 can be crossed over wherein data wire 640, but does not electrically connect with data wire 640.
In addition, the manufacture method of the manufacture method of image element array substrates 600 and image element array substrates 300 is similar, below will describe at the difference place.When carrying out the first road masking process, present embodiment is to form a plurality of scan line patterns 632 and data wire 640.When carrying out the second road masking process, present embodiment is to form contact hole opening (not illustrating) in part of scanning line pattern 632 tops, and forms contact hole subsequently to electrically connect scan line pattern 632 in the contact hole opening.When carrying out the 3rd road masking process, present embodiment is to form connecting portion 634, and connecting portion 634 is to electrically connect with contact hole.Thus, the scan line pattern 632 that is positioned at mutually same row can be electrically connected to each other with contact hole by the connecting portion 634 of correspondence, to constitute scan line 630.Those who are familiar with this art just no longer draw herein and show it when deducing voluntarily with reference to previous embodiment.
Subsidiary one what carry is that the notion of segmentation of the present invention does not limit and can only be used for scan line or data wire.Setting must be staggered when any two kinds of dissimilar leads (as bridging line (common line), power line (powerline), patch cord (repair line) etc.), and when needing close electrical characteristics, just can adopt the notion of segmentation of the present invention, wherein a kind of lead is divided into a plurality of wire patterns, these wire patterns is got up to electric connection again.Those who are familiar with this art just repeat no more when releasing easily herein.
In sum, the manufacture method of image element array substrates of the present invention has following advantage at least:
One, must use five mask beginnings can make image element array substrates Comparatively speaking with known technology, the present invention only need use three masks promptly to finish the making image element array substrates, so the cost of manufacture of image element array substrates can reduce.
Two, the manufacture method of image element array substrates of the present invention and existing processes are compatible, therefore need not increase extra process equipment.
Three, because data wire pattern and scan line are to form simultaneously with same material, so it has identical electrical characteristics.Add that data wire is made of the data wire pattern,, so can improve the phenomenon of data-signal propagation delay so the face resistance of data wire integral body can be close with the face resistance of scan line.
Though the present invention discloses with specific embodiment; but it is not in order to limit the present invention; any those skilled in the art; the displacement of the equivalent assemblies of under the prerequisite that does not break away from design of the present invention and scope, having done; or, all should still belong to the category that this patent is contained according to equivalent variations and modification that scope of patent protection of the present invention is done.
Claims (14)
1. the manufacture method of an image element array substrates, it comprises:
On a substrate, form a transparency conducting layer and one first conductive layer in regular turn;
Carry out one first road masking process, this first conductive layer of patterning and this transparency conducting layer, and the multi-strip scanning line, a plurality of data wire pattern and a plurality of pixel electrode pattern that form a plurality of grids, electrically connect with these grids;
Above this substrate, form a dielectric layer and semi-conductor layer in regular turn;
Carry out one second road masking process, this dielectric layer of patterning and this semiconductor layer, and in each above-mentioned grid top formation one passage, and formation exposes a plurality of contact hole openings of described data wire pattern, and remove this first conductive layer of described pixel electrode pattern, to form a plurality of pixel electrodes;
Above this substrate, form one second conductive layer, and this second conductive layer can be inserted described contact hole opening and form a plurality of contact holes that electrically connect with described data wire pattern; And
Carry out one the 3rd road masking process, this second metal level of patterning, and form a plurality of connecting portions of electrically connecting with described contact hole, a plurality of source electrodes that electrically connect with described data wire pattern and a plurality of drain electrodes that electrically connect with described pixel electrode, and remove this second conductive layer on each pixel electrode;
Wherein, the described data wire pattern that is positioned at identical delegation is to be electrically connected to each other by described connecting portion and described contact hole, to constitute a data wire.
2. the manufacture method of image element array substrates as claimed in claim 1 is characterized in that, after the 3rd road masking process, more comprises:
Above this substrate, form a passivation layer and a photoresist layer in regular turn;
With described grid, described source electrode, described drain electrode, described scan line and described data wire is mask, carries out a back-exposure technology and a developing process, to form a patterning photoresist layer;
With this patterning photoresist layer is this passivation layer of mask etching, to expose this pixel electrode; And
Remove this patterning photoresist layer.
3. the manufacture method of image element array substrates as claimed in claim 1 is characterized in that:
In this first road masking process, more comprise forming a plurality of weld pads, and each weld pad is to be connected in this a corresponding scan line or an end of this data wire;
In this second road masking process, more comprise this dielectric layer of part and this semiconductor layer of part of keeping this weld pad top, and remove this first conductive layer of part of this weld pad; And
In the 3rd road masking process, more comprise this second conductive layer of part that removes this weld pad top.
4. the manufacture method of image element array substrates as claimed in claim 1 is characterized in that:
In this first road masking process, more comprise forming a plurality of bottom electrodes;
In this second road masking process, more comprise keeping this dielectric layer and this semiconductor layer that is positioned at described bottom electrode top; And
In the 3rd road masking process, more comprise forming a plurality of top electrodes, be positioned on this semiconductor layer of part bottom electrode top;
Wherein, described bottom electrode and described top electrode constitute a plurality of capacitors, and each bottom electrode and this corresponding scan line electric connection, and each top electrode and this corresponding pixel electrode electric connection.
5. the manufacture method of image element array substrates as claimed in claim 1 is characterized in that, in the 3rd road masking process, more comprises the segment thickness that removes described passage.
6. the manufacture method of image element array substrates as claimed in claim 1 is characterized in that, this semiconductor layer comprises a channel material layer and an ohmic contact material layer.
7. the manufacture method of image element array substrates as claimed in claim 1 is characterized in that, the thickness of this first conductive layer is greater than the thickness of this second conductive layer.
8. the manufacture method of an image element array substrates comprises:
On a substrate, form a transparency conducting layer and one first conductive layer in regular turn;
Carry out one first road masking process, this first conductive layer of patterning and this transparency conducting layer, and a plurality of scan line patterns, many data wires and a plurality of pixel electrode pattern that form a plurality of grids, electrically connect with described grid;
Above this substrate, form a dielectric layer and semi-conductor layer in regular turn;
Carry out one second road masking process, this dielectric layer of patterning and this semiconductor layer, and in each above-mentioned grid top formation one passage, and form and to expose a plurality of contact hole openings of described scan line pattern, and this first conductive layer that removes described pixel electrode pattern is to form a plurality of pixel electrodes;
Above this substrate, form one second conductive layer, and this second conductive layer can be inserted described contact hole opening and form a plurality of contact holes that electrically connect with described scan line pattern; And
Carry out one the 3rd road masking process, this second metal level of patterning, and form a plurality of connecting portions of electrically connecting with described contact hole, a plurality of source electrodes that electrically connect with described data wire and a plurality of drain electrodes that electrically connect with described pixel electrode, and remove this second conductive layer on each pixel electrode;
Wherein, the described scan line pattern that is positioned at mutually same row is to be electrically connected to each other by described connecting portion and described contact hole, to constitute the one scan line.
9. the manufacture method of image element array substrates as claimed in claim 8 is characterized in that, after the 3rd road masking process, more comprises:
Above this substrate, form a passivation layer and a photoresist layer in regular turn;
With described grid, described source electrode, described drain electrode, described scan line and described data wire is mask, carries out a back-exposure technology and a developing process, to form a patterning photoresist layer;
With this patterning photoresist layer is this passivation layer of mask etching, to expose this pixel electrode; And
Remove this patterning photoresist layer.
10. the manufacture method of image element array substrates as claimed in claim 8 is characterized in that:
In this first road masking process, more comprise forming a plurality of weld pads, and each weld pad is to be connected in this a corresponding scan line or an end of this data wire;
In this second road masking process, more comprise this dielectric layer of part and this semiconductor layer of part of keeping this weld pad top, and remove this first conductive layer of part of this weld pad; And
In the 3rd road masking process, more comprise this second conductive layer of part that removes this weld pad top.
11. the manufacture method of image element array substrates as claimed in claim 8 is characterized in that:
In this first road masking process, more comprise forming a plurality of bottom electrodes;
In this second road masking process, more comprise keeping this dielectric layer and this semiconductor layer that is positioned at described bottom electrode top; And
In the 3rd road masking process, more comprise forming a plurality of top electrodes, be positioned on this semiconductor layer of part bottom electrode top;
Wherein, described bottom electrode and described top electrode constitute a plurality of capacitors, and each bottom electrode and this corresponding scan line electric connection, and each top electrode and this corresponding pixel electrode electric connection.
12. the manufacture method of image element array substrates as claimed in claim 8 is characterized in that, in the 3rd road masking process, more comprises the segment thickness that removes described passage.
13. the manufacture method of image element array substrates as claimed in claim 8 is characterized in that, this semiconductor layer comprises a channel material layer and an ohmic contact material layer.
14. the manufacture method of image element array substrates as claimed in claim 8 is characterized in that, the thickness of this first conductive layer is greater than the thickness of this second conductive layer.
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| CNB2006100584018A CN100386866C (en) | 2006-03-22 | 2006-03-22 | Method for manufacturing pixel array substrate |
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| CNB2006100584018A CN100386866C (en) | 2006-03-22 | 2006-03-22 | Method for manufacturing pixel array substrate |
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| CN102496618A (en) * | 2011-12-06 | 2012-06-13 | 华映视讯（吴江）有限公司 | Pixel structure and manufacturing method thereof |
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