CN102479692B - Gate forming method - Google Patents
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- CN102479692B CN102479692B CN201010568295.4A CN201010568295A CN102479692B CN 102479692 B CN102479692 B CN 102479692B CN 201010568295 A CN201010568295 A CN 201010568295A CN 102479692 B CN102479692 B CN 102479692B
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Abstract
The invention discloses a gate forming method comprising the following steps: providing a substrate; forming a gate dielectric layer on the surface of the substrate, forming a tungsten nitride layer on the surface of the gate dielectric layer and forming a tungsten layer on the surface of the tungsten nitride layer; patterning the tungsten nitride layer and the tungsten layer; etching part of patterned tungsten nitride layer and tungsten layer by using a wet process, and forming a false gate, wherein the speed for etching the tungsten nitride by using the wet process is larger than the speed for etching tungsten, and the false gate is T-shaped and comprises the tungsten nitride layer and the tungsten layer which are etched by using the wet process; forming a dielectric layer to cover the gate dielectric layer, wherein the surface of the dielectric layer is level with the surface of the false gate; removing the false gate to form a T-shaped gate trench; and filling gate materials in the gate trench to form a gate. The gate forming method is beneficial to filling the gate materials, and formed gaps can be avoided or at least reduced; and the method is simple, and the defect that the substrate is damaged in the prior art can be avoided.
Description
Technical field
The present invention relates to technical field of semiconductors, relate in particular to the method that forms grid.
Background technology
In prior art, the technique that forms grid can be divided into front grid (gate first) technique and rear grid (gate last) technique.Front grid technique refers to and first deposits gate dielectric layer, forms gate electrode on gate dielectric layer, then carries out source and leaks injection, carries out afterwards annealing process with the ion in activation of source leakage.Its processing step of front grid technique is simple, but in the time annealing, gate electrode inevitably will bear high temperature, causes the threshold voltage vt drift of metal-oxide-semiconductor, affects pipe performance.Rear grid technique refers to after annealing process,, after high-temperature step, etches away the pseudo-grid of polysilicon, form pseudo-gate groove, then with suitable metal filled pseudo-gate groove with form gate electrode, can make like this gate electrode avoid high temperature, avoid the threshold voltage vt drift of metal-oxide-semiconductor, affect pipe performance.
Rear grid technique can be widened the range of choice of the material of gate electrode greatly, more complicated but technique becomes.In the time forming metal gate electrode, along with dimensions of semiconductor devices is more and more less, particularly in 32nm and following technique, because pseudo-gate groove width diminishes, make the charging efficiency of metal material be difficult to reach absolutely, in the middle of the metal of inserting in pseudo-gate groove, can exist certain gap, gap not only can increase the dead resistance of gate electrode, but also can cause the problems such as metal-oxide-semiconductor reliability reduction.
The Chinese patent application disclosed " integrated circuit metal gate structure and manufacture method thereof " that on February 24th, 2010, disclosed publication number was " CN101656205A " discloses a kind of method that forms metal gates, comprising: Semiconductor substrate is provided; In described Semiconductor substrate, form dummy gate structure, wherein, described dummy gate structure comprises polysilicon; Remove described dummy gate structure, so that the groove with top and bottom to be provided, wherein said top and described bottom have the first width; Increase the top width of described groove, so that the second width to be provided; And, in the described groove that comprises described the second width, forming grid, the step of wherein said formation grid comprises the first metal is deposited in described groove.The method of disclosed formation metal gates in this patent documentation, removing after dummy gate structure, increases the width at groove top, after being beneficial to, in groove, fills metal, improves the fillibility of metal.But, in this patent documentation, utilize argon (Ar) sputtering technology to increase groove top width, easy like this substrate is damaged.
Summary of the invention
The problem that the present invention solves is the method for the formation grid of prior art, easily substrate is caused to damage.
For addressing the above problem, the invention provides a kind of method that forms grid, comprising:
Substrate is provided;
Form gate dielectric layer at described substrate surface, form tungsten nitride layer on described gate dielectric layer surface, form tungsten layer on described tungsten nitride layer surface;
Graphical described tungsten nitride layer and tungsten layer;
Wet etching is removed described tungsten nitride layer and the tungsten layer after graphical of part, and described wet etching is greater than the etch rate to tungsten to the etch rate of tungsten nitride, form dummy grid, described dummy grid is T-shaped, and described dummy grid comprises tungsten nitride layer and the tungsten layer after wet etching;
Form dielectric layer, cover described gate dielectric layer, the surface of described dielectric layer is equal with the surface of dummy grid;
Remove described dummy grid, form gate trench, described gate trench is T-shaped;
In described gate trench, fill grid material, form grid.
Optionally, utilize chemical vapour deposition (CVD) to form tungsten nitride layer on described gate dielectric layer; The gas using in described chemical vapour deposition (CVD) comprises: WF
6, H
2, N
2.
Optionally, described WF
6flow be 3～10sccm, described N
2flow be 50～200sccm, described H
2flow be 100～1000sccm.
Optionally, the time of described chemical gas phase reaction is 5～15 seconds.
Optionally, utilize chemical vapour deposition (CVD) or physical vapour deposition (PVD) to form tungsten layer on described tungsten nitride layer.
Optionally, the solution using in described wet etching is selected from H
2sO
4solution, NH
4oH solution, HF solution one of them.
Optionally, utilize dry etching to remove dummy grid.
Optionally, the gas using in described dry etching comprises: Cl
2, SF
6.
Optionally, described gate dielectric layer comprise silicon dioxide layer, silicon oxynitride layer, silicon nitride layer one of them, or their combination in any.
Optionally, described gate dielectric layer also comprises at least one floor height k dielectric layer, and described k value is greater than 4.5.
Optionally, also comprise: form after dummy grid, before forming dielectric layer, around described dummy grid, form side wall.
Optionally, described grid material is selected from metal silicide one of them or theys' of metal carbides, the conduction of metal nitride, the conduction of hafnium, zirconium, titanium, aluminium, thallium, palladium, platinum, cobalt, nickel, tungsten, silver, copper, gold, conduction combination.
Compared with prior art, the present invention has the following advantages:
The method of formation grid of the present invention, while utilizing wet etching tungsten nitride and tungsten, the etch rate of tungsten nitride is greater than to the feature of the etch rate to tungsten, on substrate, form patterned tungsten nitride layer and tungsten layer, tungsten layer is positioned on tungsten nitride layer, when tungsten nitride layer after utilizing wet etching removal part graphical like this and tungsten layer, therefore can form T-shaped dummy grid, the top width of dummy grid is also just greater than bottom width like this.Form after dielectric layer, remove after dummy grid, just can form T-shaped gate trench, the top width of gate trench is also just greater than bottom width like this.In gate trench, fill grid material, while forming grid, be conducive to the filling of grid material, avoid forming space, or at least can reduce the space of formation; And technique is simple, can avoid the shortcoming that substrate is caused to damage described in the prior.
Brief description of the drawings
Fig. 1 is the flow chart of the method for the formation grid of the specific embodiment of the present invention;
The cross-sectional view of the method for the formation grid that Fig. 2 a～Fig. 2 h is the specific embodiment of the invention.
Embodiment
Inventor is through long-term studying intensively, and hope can find simple technique to form the gate trench that top width is greater than bottom width, is conducive to the filling of grid material, avoids forming space, or at least can reduce the space of formation; And, can avoid the shortcoming that substrate is caused to damage described in the prior.Read through a large amount of data, inventor finds unexpectedly, when " Enrico Bellandi; Cinzia De Marco; Antonio Truscello; Jeffery W.Butterbaugh " disclosed wet etching tungsten nitride and tungsten in " Future Fab International; Volume30; July 2009 " disclosed article " resist removal and cleaning for TANOS metal gatenonvolatile memories ", the etch rate of tungsten nitride is greater than to the feature of the etch rate to tungsten.
The method of the formation grid of the specific embodiment of the invention, while utilizing wet etching tungsten nitride and tungsten, the etch rate of tungsten nitride is greater than to the feature of the etch rate to tungsten, on substrate, form patterned tungsten nitride layer and tungsten layer, tungsten layer is positioned on tungsten nitride layer, when tungsten nitride layer after utilizing wet etching removal part graphical like this and tungsten layer, therefore can form T-shaped dummy grid, the top width of dummy grid is also just greater than bottom width like this.Form after dielectric layer, remove after dummy grid, just can form T-shaped gate trench, the top width of gate trench is also just greater than bottom width like this.In gate trench, fill grid material, while forming grid, be conducive to the filling of grid material, avoid forming space, or at least can reduce the space of formation; And technique is simple, can avoid the shortcoming that substrate is caused to damage described in the prior.
For those skilled in the art be can better understand the present invention, describe the specific embodiment of the present invention in detail below in conjunction with accompanying drawing.
Fig. 1 is the flow chart of the method for the formation grid of the specific embodiment of the present invention, ginseng Fig. 1, and the method for the formation grid of the specific embodiment of the invention comprises:
Step S11, provides substrate;
Step S12, forms gate dielectric layer at described substrate surface, forms tungsten nitride layer on described gate dielectric layer surface, forms tungsten layer on described tungsten nitride layer surface;
Step S13, graphical described tungsten nitride layer and tungsten layer;
Step S14, wet etching is removed described tungsten nitride layer and the tungsten layer after graphical of part, and described wet etching is greater than the etch rate to tungsten to the etch rate of tungsten nitride, forms dummy grid, described dummy grid is T-shaped, and described dummy grid comprises tungsten nitride layer and the tungsten layer after wet etching;
Step S15, forms dielectric layer, covers described gate dielectric layer, and the surface of described dielectric layer is equal with the surface of described dummy grid;
Step S16, removes described dummy grid, forms gate trench, and being of described gate trench is T-shaped;
Step S17 fills grid material in described gate trench, forms grid.
The cross-sectional view of the method for the formation grid that Fig. 2 a～Fig. 2 h is the specific embodiment of the invention, in order to make those skilled in the art can better understand the present invention the method for the formation grid of embodiment, below in conjunction with specific embodiment and in conjunction with the method that describes the formation grid of the specific embodiment of the invention with reference to figure 1 and Fig. 2 a～Fig. 2 h in detail.
In conjunction with reference to figure 1 and Fig. 2 a, perform step S11, substrate 20 is provided.In the specific embodiment of the invention, the material of substrate 20 can be monocrystalline silicon, monocrystalline germanium or single-crystal silicon Germanium; Also can be silicon-on-insulator (SOI); Or can also comprise other material, the III-V compounds of group such as such as GaAs.In described substrate 20, be formed with device architecture (not shown), such as isolation trench structure etc.
In conjunction with reference to figure 1 and Fig. 2 b, execution step S12, forms gate dielectric layers 21 on described substrate 20 surfaces, forms tungsten nitrides (WN) layer 22 on described gate dielectric layer 21 surfaces, forms tungsten layers 23 on described tungsten nitride layer 22 surfaces.
In the specific embodiment of the invention, the material of described gate dielectric layer 21 comprises silicon dioxide (SiO
2), silicon oxynitride (SiON), silicon nitride (SiN) one of them, or their combination in any, that is to say, gate dielectric layer 21 can be silicon dioxide layer, or be silicon oxynitride layer, or silicon nitride layer, also can be silicon dioxide layer, for the combination in any of silicon oxynitride layer, silicon nitride layer, it can be single layer structure, also can be laminated construction, the double-layer structure of for example silicon dioxide layer and silicon nitride layer composition, the three-decker of silicon dioxide layer, silicon oxynitride layer, silicon nitride layer composition.And in the specific embodiment of the invention, described gate dielectric layer 21 can also comprise at least one floor height k dielectric layer, described k value is greater than 4.5, and the material of high K medium layer is selected from hafnium oxide (HfO
2), silicon hafnium oxide (HfSiO), nitrogen hafnium oxide (HfON), nitrogen hafnium silicon oxide (HfSiON), lanthana (La
2o
3), zirconia (ZrO
2), silicon zirconia (ZrSiO), titanium oxide (TiO
2), yittrium oxide (Y
2o
3).For example, gate dielectric layer 21 is double-decker, comprises silicon oxide layer and is positioned at silicon hafnium oxide (HfSiO) layer on silicon oxide layer.
In the specific embodiment of the invention, utilize chemical vapour deposition (CVD) to form tungsten nitride layer 22 on described gate dielectric layer 21.The gas using in described chemical vapour deposition (CVD) comprises: WF
6(tungsten hexafluoride), H
2(hydrogen), N
2(nitrogen), reaction equation is: WF
6+ H
2+ N
2→ WN+HF.WF
6flow be 3～10sccm, N
2flow be 50～200sccm.H
2flow be 100～1000sccm, and in the specific embodiment of the invention, the gas of use also comprises Ar (argon) gas, its flow is 300～1000sccm.Air pressure in reaction chamber is 3～5Torr (millitorr), and radio-frequency power is 200～500W, and the temperature range in reaction chamber is 400～500 DEG C, and the reaction time is 5～15 seconds.
In the specific embodiment of the invention, the method that forms tungsten layer 23 is physical vapour deposition (PVD) (PVD) or chemical vapour deposition (CVD).
In conjunction with reference to figure 1 and Fig. 2 c, perform step S13, graphical described tungsten nitride layer 22 and tungsten layer 23.Be specially: on tungsten layer 23, form photoresist layer, the method that forms photoresist layer can be spin-coating method, drop-coating or spread coating, in the specific embodiment of the invention, utilize spin-coating method to form photoresist layer.Afterwards, photoresist layer is exposed, developed, form patterned photoresist layer; Then,, taking patterned lithography layer as mask etching tungsten layer 23, tungsten nitride layer 22, is transferred to tungsten layer 23, tungsten nitride layer 22 by the figure on patterned photoresist layer.In this step, not etching gate dielectric layer 21, this gate dielectric layer 21 after wet etching corrosion tungsten nitride and when tungsten, be used for protecting substrate 20 injury-free.
In conjunction with reference to figure 1 and Fig. 2 d, execution step S14, wet etching is removed described tungsten nitride layer 22 and the tungsten layer 23 after graphical of part, and described wet etching is greater than the etch rate to tungsten to the etch rate of tungsten nitride, form dummy grid, described dummy grid is T-shaped, and described dummy grid comprises tungsten nitride layer 22 and the tungsten layer 23 after wet etching.In the specific embodiment of the invention, the solution using in described wet etching is selected from H
2sO
4solution, NH
4oH solution, HF solution one of them.In the specific embodiment of the invention, select NH
4oH solution wet etching tungsten nitride layer 22 and tungsten layer 23, because the etch rate of tungsten nitride is greater than the etch rate to tungsten, therefore can form T-shaped dummy grid, and the top width of dummy grid is also just greater than bottom width like this.
With reference to figure 2e, in the specific embodiment of the invention, form after dummy grid, Semiconductor substrate 20 is carried out to source and leak injection, in Semiconductor substrate 20, form source region and drain region (not shown).Afterwards, form dielectric layer, cover the surface that described gate dielectric layer 21 and dummy grid form, return afterwards dielectric layer at quarter, formation side wall 24 around dummy grid.
In conjunction with reference to figure 1 and Fig. 2 f, perform step S15, form dielectric layer 25, cover described gate dielectric layer 21, the surface of described dielectric layer 25 is equal with the surface of described dummy grid.Be specially: form dielectric layer 25, cover the surface of described gate dielectric layer 21 and side wall 24, dummy grid formation, afterwards, utilize chemical-mechanical planarization (CMP) to remove the surperficial dielectric layer that exceeds dummy grid, namely remove the dielectric layer that exceeds tungsten layer 23 surfaces, form the dielectric layer 25 equal with the surface of described dummy grid, i.e. the dielectric layer 25 equal with the surface of described tungsten layer 23.The present invention, the material of dielectric layer 25 is low-k materials, it can well known to a person skilled in the art low-k materials for silica (SiO2), fluorine silica (SiOF), silicon oxide carbide (SiCO) etc.In the specific embodiment of the invention, select the material of silica as dielectric layer 25.
In conjunction with reference to figure 1 and Fig. 2 g, perform step S16, remove described dummy grid (in conjunction with reference to figure 2f), form gate trench 26, described gate trench 26 is T-shaped.Because dummy grid is T-shaped, to remove after dummy grid, natural gate trench 26 is T-shaped, and the top width of gate trench 26 is greater than bottom width like this.In the present invention, utilize dry etching to remove and comprise tungsten nitride layer 22 after wet etching and the dummy grid of tungsten layer 23, in the specific embodiment of the invention, the gas using in described dry etching comprises: Cl
2, SF
6.
In conjunction with reference to figure 1 and Fig. 2 h, perform step S17, at the interior filling grid material of described gate trench 26, form grid 27.In the specific embodiment of the invention, the material of described grid 27 is selected from metal silicide one of them or theys' of metal carbides, the conduction of metal nitride, the conduction of hafnium, zirconium, titanium, aluminium, thallium, palladium, platinum, cobalt, nickel, tungsten, silver, copper, gold, conduction combination.The method that forms grid 27 is specially: utilize vapour deposition, for example physical vapour deposition (PVD) (PVD), chemical vapour deposition (CVD) (CVD) are filled grid material in described gate trench 26, and fill up gate trench 26, afterwards, utilize flatening process, for example cmp planarized gate material, finally forms grid 27.In the specific embodiment of the invention, select metallic aluminium as grid material.Utilize physical gas-phase deposite method to fill metallic aluminium in described gate trench 26, and in the time of plated metal aluminium, on the surface of dielectric layer 25, also deposit metallic aluminium, utilize afterwards flatening process to remove the lip-deep metallic aluminium of dielectric layer 25, form grid 27, the surface of grid 27 is equal with the surface of dielectric layer 25.In the present invention, because gate trench is T-shaped, the top width of gate trench is also just greater than bottom width like this.In gate trench, fill grid material, while forming grid, be conducive to the filling of grid material, avoid forming space, or at least can reduce the space of formation.
Although the present invention with preferred embodiment openly as above; but it is not for limiting the present invention; any those skilled in the art without departing from the spirit and scope of the present invention; can utilize method and the technology contents of above-mentioned announcement to make possible variation and amendment to technical solution of the present invention; therefore; every content that does not depart from technical solution of the present invention; any simple modification, equivalent variations and the modification above embodiment done according to technical spirit of the present invention, all belong to the protection range of technical solution of the present invention.
Claims (10)
1. a method that forms grid, is characterized in that, comprising:
Substrate is provided;
Form gate dielectric layer at described substrate surface, form tungsten nitride layer on described gate dielectric layer surface, form tungsten layer on described tungsten nitride layer surface; Utilize chemical vapour deposition (CVD) to form tungsten nitride layer on described gate dielectric layer; The gas using in described chemical vapour deposition (CVD) comprises: WF
6, H
2, N
2, described WF
6flow be 3～10sccm, described N
2flow be 50～200sccm, described H
2flow be 100～1000sccm;
Graphical described tungsten nitride layer and tungsten layer;
Wet etching is removed described tungsten nitride layer and the tungsten layer after graphical of part, and described wet etching is greater than the etch rate to tungsten to the etch rate of tungsten nitride, form dummy grid, described dummy grid is T-shaped, and described dummy grid comprises tungsten nitride layer and the tungsten layer after wet etching;
Form dielectric layer, cover described gate dielectric layer, the surface of described dielectric layer is equal with the surface of dummy grid;
Remove described dummy grid, form gate trench, described gate trench is T-shaped;
In described gate trench, fill grid material, form grid.
2. the method for formation grid as claimed in claim 1, is characterized in that, the time of described chemical gas phase reaction is 5～15 seconds.
3. the method for formation grid as claimed in claim 1, is characterized in that, utilizes chemical vapour deposition (CVD) or physical vapour deposition (PVD) to form tungsten layer on described tungsten nitride layer.
4. the method for formation grid as claimed in claim 1, is characterized in that, the solution using in described wet etching is selected from H
2sO
4solution, NH
4oH solution, HF solution one of them.
5. the method for formation grid as claimed in claim 1, is characterized in that, utilizes dry etching to remove dummy grid.
6. the method for formation grid as claimed in claim 5, is characterized in that, the gas using in described dry etching comprises: Cl
2, SF
6.
7. the method for formation grid as claimed in claim 1, is characterized in that, described gate dielectric layer comprise silicon dioxide layer, silicon oxynitride layer, silicon nitride layer one of them, or their combination in any.
8. the method for formation grid as claimed in claim 7, is characterized in that, described gate dielectric layer also comprises at least one floor height k dielectric layer, and described k value is greater than 4.5.
9. the method for formation grid as claimed in claim 1, is characterized in that, also comprises: form after dummy grid, before forming dielectric layer, around described dummy grid, form side wall.
10. the method for formation grid as claimed in claim 1, it is characterized in that, described grid material is selected from metal silicide one of them or theys' of metal carbides, the conduction of metal nitride, the conduction of hafnium, zirconium, titanium, aluminium, thallium, palladium, platinum, cobalt, nickel, tungsten, silver, copper, gold, conduction combination.
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|---|---|---|---|
| CN201010568295.4A CN102479692B (en) | 2010-11-30 | 2010-11-30 | Gate forming method |
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|---|---|---|---|
| CN201010568295.4A CN102479692B (en) | 2010-11-30 | 2010-11-30 | Gate forming method |
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| CN102479692B true CN102479692B (en) | 2014-06-04 |
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Families Citing this family (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103531455B (en) * | 2012-07-03 | 2017-06-06 | 中国科学院微电子研究所 | Semiconductor devices and its manufacture method |
| CN103871886B (en) * | 2012-12-18 | 2017-12-01 | 中芯国际集成电路制造(上海)有限公司 | The forming method of transistor |
| CN104112657B (en) * | 2013-04-18 | 2016-12-28 | 中芯国际集成电路制造(上海)有限公司 | A kind of manufacture method of MOS device |
| US9780213B2 (en) * | 2014-04-15 | 2017-10-03 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor device having a reversed T-shaped profile in the metal gate line-end |
| CN105097696B (en) * | 2014-05-22 | 2018-07-20 | 中芯国际集成电路制造(上海)有限公司 | A kind of semiconductor devices and its manufacturing method, electronic device |
| CN105762079A (en) * | 2014-12-17 | 2016-07-13 | 中芯国际集成电路制造(上海)有限公司 | Method of forming transistor |
| CN105810638B (en) * | 2014-12-31 | 2019-02-22 | 上海格易电子有限公司 | A kind of 3D NAND flash memory structure and production method |
| US10622214B2 (en) * | 2017-05-25 | 2020-04-14 | Applied Materials, Inc. | Tungsten defluorination by high pressure treatment |
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| CN100527359C (en) * | 2007-05-15 | 2009-08-12 | 中芯国际集成电路制造(上海)有限公司 | Etching method of polycrystalline silicon |
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