CN100527359C - Etching method of polycrystalline silicon - Google Patents
Etching method of polycrystalline silicon Download PDFInfo
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- CN100527359C CN100527359C CNB2007100406424A CN200710040642A CN100527359C CN 100527359 C CN100527359 C CN 100527359C CN B2007100406424 A CNB2007100406424 A CN B2007100406424A CN 200710040642 A CN200710040642 A CN 200710040642A CN 100527359 C CN100527359 C CN 100527359C
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Abstract
The invention provides a method to fashion an inverted trapezoid-shaped polysilicon section, relating to semiconductor manufacturing technique. Conventional dry etching methods fail to produce inverted trapezoid-shaped polysilicon sections which are identical in shape with even feature linewidth. The method described by the invention includes the following steps: firstly, a base plate is provided and a gate oxide layer is developed on the base plate; then a plurality of polysilicon layers are deposited sequentially on the gate oxide layer and the polysilicon layers gradually decrease in doping concentration; after that, the polysilicon layers are processed with dry etching so that vertical sections can be developed on the polysilicon layers; the polysilicon layers are processed with wet etching so that inverted trapezoid-shaped sections can be developed on the polysilicon layers. The method of the invention can produce an inverted trapezoid-shaped polysilicon section with the upper part wide and the lower part narrow and can ensure even feature linewidth.
Description
Technical field
The present invention relates to process for fabrication of semiconductor device, relate in particular to the lithographic method of polysilicon.
Background technology
At nonvolatile memory, for example in the manufacturing process of NAND Logic door (NAND) flash cell, wish to form the class cross section of falling the trapezoidal polysilicon wide at the top and narrow at the bottom.Because if the polysilicon cross section is vertical or up-narrow and down-wide shape, then after filling, oxide carries out again in the process of grid etch follow-up finishing, be difficult to etching polysilicon totally, need to carry out extra cleanup step and remove the residual polysilicon in bottom.
Fall trapezoidal polysilicon cross section if adopt traditional dry etching processing procedure to obtain class, then, can't obtain shape unanimity and characteristic line breadth homogeneity polysilicon cross section preferably because etching process is difficult to control.
Summary of the invention
The object of the present invention is to provide a kind of lithographic method of polysilicon, obtaining the class cross section of falling the trapezoidal polysilicon wide at the top and narrow at the bottom, and guarantee good characteristic line breadth homogeneity.
To achieve the above object, the invention provides a kind of lithographic method of polysilicon, it comprises: a substrate a) is provided, and forms a gate oxide on substrate; B) deposit number layer polysilicon layer successively on described gate oxide, and the doping content of these several layers of polysilicon layers reduces successively; C) described several layers of polysilicon layer are carried out dry etching, to form vertical cross-section; And d) adopts nitric acid and hydrofluoric acid that described several layers of polysilicon layer are carried out wet etching, fall the trapezoid cross section with the formation class.
In above-mentioned method, step b) is 2~10 layers of polysilicon layer of deposit on gate oxide.
In above-mentioned method,, can adjust the inclined degree of polysilicon cross section side by the doping content of change polysilicon layer or the reaction time of wet etching.
The polysilicon layer that the present invention reduces successively by deposit several layers doping content on gate oxide, utilize doping content to become the principle of monotonic increase relation with etch rate, these polysilicon layers etch rate in the wet etching process is reduced successively, to form the class cross section of falling the trapezoidal polysilicon wide at the top and narrow at the bottom, thereby can etching polysilicon is clean in follow-up grid etch process, need not to carry out extra cleanup step and remove residual polycrystalline silicon.In addition, by effective control, also can guarantee the uniformity of characteristic line breadth to doping content, reaction time.
Description of drawings
Polycrystalline silicon etching method of the present invention is provided by following embodiment and accompanying drawing.
Fig. 1 a~Fig. 1 e is the flow chart of the specific embodiment of the invention.
Embodiment
Below will the lithographic method of polysilicon of the present invention be described in further detail.
Fig. 1 a~Fig. 1 e is the flow chart that method of the present invention is applied to an embodiment in the making of NAND Logic door, and this making flow process comprises the following steps:
At first, as shown in Figure 1a, provide a substrate 10, and on substrate 10, form a gate oxide 20.
Then, shown in Fig. 1 b, deposit number layer polysilicon layer successively on gate oxide 20, in present embodiment, adopt four layers of polysilicon, and the doping content of these four layers of polysilicons 31,32,33,34 reduces successively, in order that in follow-up wet etching process, obtain different etch rates.
Then, shown in Fig. 1 c,, and etch corresponding live width according to the requirement of characteristic size at the hard mask of polysilicon layer 34 surface depositions.Certainly, according to different device fabrications, also can be at other material of polysilicon layer 34 surface depositions.
Subsequently, shown in Fig. 1 d, on the basis of the hard mask etching of back, again polysilicon layer 31~34 is carried out dry etching, to form vertical polysilicon cross section.In this step, the uniformity of characteristic line breadth can obtain good control.
At last, adopt nitric acid and hydrofluoric acid that polysilicon layer 31~34 is carried out wet etching.Because etch rate becomes monotonic increase relation with the doping content of polysilicon, therefore, the etch rate of polysilicon layer 31~34 reduces successively, thereby the wide at the top and narrow at the bottom class of formation shown in Fig. 1 e fallen the trapezoid cross section.
In other embodiments of the invention, can be according to the requirement of polysilicon cross section side planarization, 2~10 layers of polysilicon layer of deposit, the number of plies is many more, and the thickness of each layer is more little, and the side in the polysilicon cross section that finally obtains is smooth more, and its shape also approaches trapezoidal more.In addition, because polysilicon doping concentration is high more, the wet etching time is long more, its etch rate side big more, that form the polysilicon cross section tilts more.Therefore, by to polysilicon doping concentration and the control of wet etching time, can adjust the inclined degree of polysilicon cross section side.
Claims (3)
1, a kind of lithographic method of polysilicon is characterized in that, comprising:
A) provide a substrate, and on substrate, form a gate oxide;
B) deposit number layer polysilicon layer successively on described gate oxide, and the doping content of these several layers of polysilicon layers reduces successively;
C) described several layers of polysilicon layer are carried out dry etching, to form vertical cross-section; And
D) adopt nitric acid and hydrofluoric acid that described several layers of polysilicon layer are carried out wet etching, fall the trapezoid cross section with the formation class.
2, the lithographic method of polysilicon as claimed in claim 1 is characterized in that: in the step b) on gate oxide 2~10 layers of polysilicon layer of deposit.
3, the lithographic method of polysilicon as claimed in claim 1 is characterized in that: the doping content by changing polysilicon layer or the reaction time of wet etching are adjusted the inclined degree of polysilicon cross section side.
Priority Applications (1)
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CNB2007100406424A CN100527359C (en) | 2007-05-15 | 2007-05-15 | Etching method of polycrystalline silicon |
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CNB2007100406424A CN100527359C (en) | 2007-05-15 | 2007-05-15 | Etching method of polycrystalline silicon |
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CN101308787A CN101308787A (en) | 2008-11-19 |
CN100527359C true CN100527359C (en) | 2009-08-12 |
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Families Citing this family (9)
Publication number | Priority date | Publication date | Assignee | Title |
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CN101752233B (en) * | 2008-12-04 | 2012-02-29 | 上海华虹Nec电子有限公司 | Method for in-place doping polysilicon gate |
CN102468145A (en) * | 2010-11-01 | 2012-05-23 | 中芯国际集成电路制造(上海)有限公司 | Method for forming metal grid |
CN102479691A (en) * | 2010-11-30 | 2012-05-30 | 中芯国际集成电路制造(上海)有限公司 | Forming methods of metal gate and MOS (Metal Oxide Semiconductor) transistor |
CN102479692B (en) * | 2010-11-30 | 2014-06-04 | 中芯国际集成电路制造(北京)有限公司 | Gate forming method |
JP2014116707A (en) * | 2012-12-07 | 2014-06-26 | Seiko Epson Corp | Method of manufacturing vibrator |
CN105226021A (en) * | 2014-06-26 | 2016-01-06 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
CN109887842A (en) * | 2019-01-08 | 2019-06-14 | 上海华虹宏力半导体制造有限公司 | The lithographic method of polysilicon |
CN111508835A (en) * | 2020-04-26 | 2020-08-07 | 深圳市昭矽微电子科技有限公司 | Pattern structure and forming method thereof |
CN115995486A (en) * | 2021-10-15 | 2023-04-21 | 长鑫存储技术有限公司 | Method for manufacturing semiconductor structure and semiconductor structure |
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Effective date of registration: 20111117 Address after: 201203 No. 18 Zhangjiang Road, Shanghai Co-patentee after: Semiconductor Manufacturing International (Beijing) Corporation Patentee after: Semiconductor Manufacturing International (Shanghai) Corporation Address before: 201203 No. 18 Zhangjiang Road, Shanghai Patentee before: Semiconductor Manufacturing International (Shanghai) Corporation |