CN103730418A - Method for manufacturing semiconductor device - Google Patents
Method for manufacturing semiconductor device Download PDFInfo
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- CN103730418A CN103730418A CN201210383134.7A CN201210383134A CN103730418A CN 103730418 A CN103730418 A CN 103730418A CN 201210383134 A CN201210383134 A CN 201210383134A CN 103730418 A CN103730418 A CN 103730418A
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- 238000000034 method Methods 0.000 title claims abstract description 58
- 239000004065 semiconductor Substances 0.000 title claims abstract description 39
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 8
- 239000010410 layer Substances 0.000 claims abstract description 82
- 229910052751 metal Inorganic materials 0.000 claims abstract description 40
- 239000002184 metal Substances 0.000 claims abstract description 40
- 238000001312 dry etching Methods 0.000 claims abstract description 32
- 239000000758 substrate Substances 0.000 claims abstract description 24
- 230000004888 barrier function Effects 0.000 claims abstract description 17
- 239000011229 interlayer Substances 0.000 claims abstract description 17
- 238000002156 mixing Methods 0.000 claims abstract description 16
- 238000001039 wet etching Methods 0.000 claims abstract description 15
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 claims abstract description 13
- 238000005530 etching Methods 0.000 claims abstract description 12
- 239000000463 material Substances 0.000 claims description 24
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 14
- 229920005591 polysilicon Polymers 0.000 claims description 14
- 239000007769 metal material Substances 0.000 claims description 11
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 claims description 6
- 230000006835 compression Effects 0.000 claims description 4
- 238000007906 compression Methods 0.000 claims description 4
- 229910000147 aluminium phosphate Inorganic materials 0.000 claims description 3
- 238000011065 in-situ storage Methods 0.000 claims description 3
- 230000008569 process Effects 0.000 abstract description 10
- 150000002500 ions Chemical class 0.000 abstract description 3
- 230000000873 masking effect Effects 0.000 abstract 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 8
- 239000007789 gas Substances 0.000 description 7
- 238000005229 chemical vapour deposition Methods 0.000 description 6
- 238000000059 patterning Methods 0.000 description 5
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 4
- 229920002120 photoresistant polymer Polymers 0.000 description 4
- 238000005240 physical vapour deposition Methods 0.000 description 4
- 239000000377 silicon dioxide Substances 0.000 description 4
- 238000009825 accumulation Methods 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- MCMNRKCIXSYSNV-UHFFFAOYSA-N Zirconium dioxide Chemical compound O=[Zr]=O MCMNRKCIXSYSNV-UHFFFAOYSA-N 0.000 description 2
- 150000001450 anions Chemical class 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 229910052735 hafnium Inorganic materials 0.000 description 2
- VBJZVLUMGGDVMO-UHFFFAOYSA-N hafnium atom Chemical compound [Hf] VBJZVLUMGGDVMO-UHFFFAOYSA-N 0.000 description 2
- 239000001307 helium Substances 0.000 description 2
- 229910052734 helium Inorganic materials 0.000 description 2
- SWQJXJOGLNCZEY-UHFFFAOYSA-N helium atom Chemical compound [He] SWQJXJOGLNCZEY-UHFFFAOYSA-N 0.000 description 2
- 229910044991 metal oxide Inorganic materials 0.000 description 2
- 150000004706 metal oxides Chemical class 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 229910052757 nitrogen Inorganic materials 0.000 description 2
- 238000001020 plasma etching Methods 0.000 description 2
- 238000002360 preparation method Methods 0.000 description 2
- 229910000077 silane Inorganic materials 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 239000010936 titanium Substances 0.000 description 2
- 229910004129 HfSiO Inorganic materials 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 1
- CEPICIBPGDWCRU-UHFFFAOYSA-N [Si].[Hf] Chemical compound [Si].[Hf] CEPICIBPGDWCRU-UHFFFAOYSA-N 0.000 description 1
- 239000004411 aluminium Substances 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 239000006117 anti-reflective coating Substances 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 239000000428 dust Substances 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- ZQXQADNTSSMHJI-UHFFFAOYSA-N hafnium(4+) oxygen(2-) tantalum(5+) Chemical compound [O-2].[Ta+5].[Hf+4] ZQXQADNTSSMHJI-UHFFFAOYSA-N 0.000 description 1
- BHEPBYXIRTUNPN-UHFFFAOYSA-N hydridophosphorus(.) (triplet) Chemical compound [PH] BHEPBYXIRTUNPN-UHFFFAOYSA-N 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 238000010884 ion-beam technique Methods 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 238000000608 laser ablation Methods 0.000 description 1
- 230000035800 maturation Effects 0.000 description 1
- QSHDDOUJBYECFT-UHFFFAOYSA-N mercury Chemical compound [Hg] QSHDDOUJBYECFT-UHFFFAOYSA-N 0.000 description 1
- 229910052753 mercury Inorganic materials 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 239000002210 silicon-based material Substances 0.000 description 1
- 238000003892 spreading Methods 0.000 description 1
- 230000007480 spreading Effects 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- 238000001947 vapour-phase growth Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823828—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66545—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66613—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation
- H01L29/66621—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation using etching to form a recess at the gate location
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
The invention discloses a method for manufacturing a semiconductor device. The method includes the following steps: providing a semiconductor substrate, forming a P-MOS pseudo gate laminated structure and an N-MOS pseudo gate laminated structure on the semiconductor substrate, forming an interlayer dielectric layer surrounding the pseudo gate laminated structures on the semiconductor substrate, forming a metal masking layer for shielding the N-MOS pseudo gate laminated structure on the interlayer dielectric layer, and etching to remove the pseudo gate in the P-MOS pseudo gate laminated structure with a mixing method. The P-MOS pseudo gate is removed with the dry-wet mixing etching method, chargers gathered in a titanium nitride barrier layer during dry etching are counteracted through ions in a solution during the wet etching process, the chargers generated by dry etching are prevented from being gathered to the titanium nitride barrier layer, plasma damage is accordingly avoided, the overall performance of the semiconductor device is improved, and the yield of the semiconductor device is improved.
Description
Technical field
The present invention relates to semiconductor fabrication process, relate in particular to a kind of method of removing dummy grid.
Background technology
Along with semiconductor integrated circuit (IC) industrial technology maturation day by day, the developing rapidly of ultra-large integrated circuit, components and parts size is more and more less, and the integrated level of chip is more and more higher.Because of the high density of device, undersized requirement also becomes increasingly conspicuous to semiconductor technogenic influence.IC integrated level constantly increases that to need device size to continue scaled, but the operating voltage of electrical equipment remains unchanged sometimes, makes actual metal oxide semiconductor (MOS) device produce higher electrical source consumption.Polysilicon and silicon dioxide are normally used for forming grid and the inter-level dielectric of MOS transistor.
Along with grid size foreshortens to tens nanometers, the thickness of gate oxide layers is down to below 3nm, has caused that resistance is excessive, gate leakage increases and the problems such as vague and general phenomenon appear in the polysilicon utmost point.Therefore, people invest metal gate technique again by sight again, and metal gate technique adopts has more low-resistance metal as grid, and adopts the material with larger dielectric constant as interlayer dielectric layer.Meanwhile, the function of N-MOS and P-MOS is different, the grid of the different structure therefore needing.
Metal gate technique comprises and first forms grid (Gate-first) technique and rear formation grid (Gate-last) technique.Gate-last process characteristic is to form metal gates after silicon chip is leaked/source region Implantation operation and high-temperature annealing step subsequently complete again, and wherein removing polysilicon dummy grid (DPGR) is one of committed step.Conventionally select dry etching to remove polysilicon dummy grid, because dry etching is higher than the efficiency of wet etching, the impact that the variation of etch rate is not adulterated, but dry etching can cause higher leakage.
In prior art, disclose a kind of method of removing dummy grid, as shown in Figure 1A, provide Semiconductor substrate 100.In Semiconductor substrate 100, form N-MOS dummy grid stacked structure and P-MOS dummy grid stacked structure, it from bottom to top comprises high K medium layer 101, barrier layer 102 and dummy grid 104,105 successively.The high K medium layer 101 forming, can effectively prevent that the workfunction layers forming subsequently from spreading in Semiconductor substrate 100, and then avoid the threshold voltage of MOS to increase.Barrier layer 102 is for the protection of the high K medium layer 101 of its below.Dummy grid 104,105 materials are polysilicons.In Semiconductor substrate 100, form the interlayer dielectric layer 103 that surrounds dummy grid stacked structure, then through cmp planarization.
As shown in Figure 1B, on interlayer dielectric layer 103, form the mask layer 106 with figure, the preferred titanium nitride of described mask layer 106 material.As shown in Figure 1 C, adopt dry etching to remove P-MOS dummy grid 104 completely, obtain gate trench 107.As shown in Fig. 1 D, remove mask layer 106.As shown in Fig. 1 E, at P-MOS gate trench 107, deposit first layer metal 108, then on first layer metal layer 108, deposit second layer metal 109, metal material fills up gate trench, through cmp planarization, forms metal gates.As Fig. 1 F adopts dry etching, remove N-MOS dummy grid 105 completely, obtain gate trench 110, therein deposit metallic material.Follow the making that follow-up work completes total.
But in the process of traditional removal dummy grid, there will be semiconductor device to be subject to the problem of plasma damage (PID), the electric leakage that has increased metal-oxide-semiconductor.This be due to, in traditional technique, generally can adopt dry etching to remove P-MOS dummy grid.Conventionally adopt lower radio-frequency (RF) energy and can produce low pressure and highdensity plasma gas is realized the dry etching of polysilicon, because plasma gas has just (+) attribute, in removal P-MOS dummy grid technique, on titanium nitride barrier layer 102, continue accumulation positive charge, to attract anion, these anions are mostly electronics, in high K medium layer 101 and Semiconductor substrate 100, be captured, the titanium nitride barrier layer 102 having charged produces electric discharge phenomena by high K medium layer and Semiconductor substrate 100 to substrate, thereby has changed the change of characteristic of semiconductor.The electric leakage that the plasma damage producing in high K medium layer and Semiconductor substrate 100 can increase metal-oxide semiconductor (MOS) (MOS) pipe, can cause scrapping of metal-oxide-semiconductor when serious.Especially in the time of below IC technology arrives 65nm node, damage effect of plasma can cause the damage of other various devices, causes device overall performance to decline.
Therefore, need a kind of new method, can eliminate the damage effect of plasma causing when removing dummy grid, reduce the leakage current to device, to improve the overall performance of device, improve the yields of semiconductor device.
Summary of the invention
In summary of the invention part, introduced the concept of a series of reduced forms, this will further describe in embodiment part.Summary of the invention part of the present invention does not also mean that key feature and the essential features that will attempt to limit technical scheme required for protection, does not more mean that the protection range of attempting to determine technical scheme required for protection.
In order to solve problems of the prior art, the present invention proposes a kind of method of making semiconductor device, comprise the following steps, semi-conductive substrate is provided; In described Semiconductor substrate, form P-MOS dummy grid stacked structure, N-MOS dummy grid stacked structure; In described Semiconductor substrate, form the interlayer dielectric layer that surrounds described dummy grid stacked structure; On described interlayer dielectric layer, form the metal mask layer that covers described N-MOS dummy grid stacked structure; Mixing method etching is removed the dummy grid in described P-MOS dummy grid stacked structure.
Preferably, described dummy grid stacked structure comprises the high K medium layer, barrier layer and the described dummy grid that stack gradually.
Preferably, described barrier material is titanium nitride.
Preferably, described dummy grid material is in-situ doped polysilicon.
Preferably, the material of described metal mask layer is titanium nitride.
Preferably, the thickness of described metal mask layer is 10～500 dusts.
Preferably, described mixing method etching comprises first carries out a dry etching, then carries out a wet etching.
Preferably, wherein dry etching is removed the dummy grid of 70-90%, and then wet etching is removed remaining dummy grid, forms P-MOS gate trench.
Preferably, described wet etching solution is hot phosphoric acid.
Preferably, also comprise the following steps, before carrying out described wet etching, also comprise the step of removing described metal mask layer.
Preferably, metal mask layer described in use SC1 solution removal.
Preferably, also comprise the following steps, in described P-MOS gate trench, fill the metal material of compression, then carry out cmp.
Preferably, also comprise the following steps, use dry etching to remove described N-MOS dummy grid, form N-MOS gate trench.
Preferably, also comprise the following steps, in described N-MOS gate trench, fill the metal material of tensile stress.
Preferably, first dry etching is removed described N-MOS dummy grid, and then mixing method is removed described P-MOS dummy grid.
To sum up, method of the present invention is removed P-MOS dummy grid by dry-lithographic method that wet mixing is closed, is gathered in the electric charge of titanium nitride barrier layer when the ion of solution is offset dry etching in wet etching process.Prevent that the accumulation that dry etching produces from arriving titanium nitride barrier layer, form electrical potential difference generation current with high K medium layer and Semiconductor substrate, so just avoided plasma damage, improve the overall performance of semiconductor device, improve semi-conductive yields.
Accompanying drawing explanation
Following accompanying drawing of the present invention is used for understanding the present invention in this as a part of the present invention.Shown in the drawings of embodiments of the invention and description thereof, be used for explaining principle of the present invention.In the accompanying drawings,
Figure 1A-F is the schematic diagram that tradition is removed dummy grid;
Fig. 2 A-G is the cross-sectional view of the device that obtains by each step of dry-legal etching P-MOS dummy grid of wet mixing according to one embodiment of the present invention;
Fig. 3 makes according to one embodiment of the present invention by the process chart of dry-legal etching P-MOS dummy grid of wet mixing.
Embodiment
In the following description, a large amount of concrete details have been provided to more thorough understanding of the invention is provided.But, it will be apparent to one skilled in the art that the present invention can be implemented without one or more these details.In other example, for fear of obscuring with the present invention, for technical characterictics more well known in the art, be not described.
In order thoroughly to understand the present invention, will detailed step be proposed in following description, so that how explanation the present invention adopts dry-wet mixing to close the problem of the plasma damage causing when lithographic method is removed P-MOS dummy grid.Detailed being described below of obvious preferred embodiment of the present invention, but remove outside these detailed descriptions, the present invention can also have other execution modes.
In order to overcome the problem of the plasma damage causing when tradition is removed P-MOS dummy grid, the present invention proposes to adopt dry-wet mixing to close etching and removes P-MOS dummy grid.With reference to Fig. 2 A to Fig. 2 G, illustrate according to the cutaway view of each step of the embodiment of one aspect of the invention.
As shown in Figure 2 A, provide Semiconductor substrate 200, comprise shallow channel isolation area (not shown), multiple oxide regions (not shown) and being pre-formed in N trap or P trap (not shown) wherein.In Semiconductor substrate 200, form N-MOS and P-MOS dummy grid stacked structure, it from bottom to top comprises high K medium layer 201, barrier layer 202 and dummy grid 204,205 successively.High K medium layer 201 material can be selected high k material, and depositional mode can be by the mode of chemical vapor deposition (CVD) or ald (ALD).Material can be a kind of in hafnium silica (HfSiO), hafnium silicon oxynitride (HfSiON), hafnium tantalum oxide (HffaO), hafnium zirconia (HfZrO) or their combination in any, can also be perovskite-type material.Barrier layer 202 depositional modes can be passed through other methods such as ALD, CVD, physical vapor deposition (PVD), sputter, the preferred titanium nitride of described barrier layer 202 material, thickness range 10～20 dusts.Dummy grid 104,105 materials are selected from a kind of in silicon, germanium, germanium silicon, silicon nitride, silica or their combination in any, and the material of dummy grid of the present invention is in-situ doped polycrystalline silicon material, thickness range 400～800 dusts.The formation method of polysilicon layer can be selected low-pressure chemical vapor phase deposition (LPCVD) technique.The process conditions that form polysilicon layer comprise: reacting gas is silane (SiH
4), the range of flow of silane can be 100～200 cc/min (sccm), as 150sccm; In reaction chamber, temperature range can be 700～750 degrees Celsius; Reaction chamber internal pressure can be 250～350 millimetress of mercury (mTorr), as 300mTorr; In reacting gas, also can comprise buffer gas, buffer gas can be helium (He) or nitrogen (N), and the range of flow of helium and nitrogen can be 5～20 liters/min (slm), as 8slm, 10slm or 15slm.In Semiconductor substrate 200, form the interlayer dielectric layer 203 (IDL0) that surrounds dummy grid stacked structure, adopt CVD mode to deposit interlayer dielectric layer 203, material can be silica or phosphorous oxide, and interlayer dielectric layer 203 is through cmp planarization.
As shown in Figure 2 B, form the metal mask layer 206 with figure on interlayer dielectric layer 203, the method for preparation can be selected CVD or PVD, the preferred titanium nitride of metal mask layer 206 material of the present invention, and the thickness of metal mask layer can be 10-500 dust.The method that forms described metal mask layer 206 can be for depositing the photoresist (can contain or not contain bottom antireflective coating) of described metal mask layer material and patterning on described interlayer dielectric layer, the photoresist of described patterning exposes P-MOS dummy gate region, then carries out a dry etching to remove the described metal mask layer material exposing.
Then, as shown in Figure 2 C, by dry etching, remove the polysilicon of 70-90%, adopt lower radio-frequency (RF) energy and can produce low pressure and highdensity plasma gas the dry etching of realizing polysilicon.Conventional dry etching technics, for example combination in any of reactive ion etching, ion beam etching, plasma etching, laser ablation or these methods.After dry etching, obtain remaining polysilicon layer 207.Then, use SC1(standard cleaning-1) solution removal metal mask layer 206.
As shown in Figure 2 D, by wet etching, remove remaining polysilicon layer 207, wet etching can be but not limit hot phosphoric acid etching, obtain P-MOS gate trench 208.
As shown in Figure 2 E, fill the metal material with compression in described P-MOS gate trench 208, preferably, form the first metal layer 209 in P-MOS gate trench 208, material can be titanium (Ti) material; Then on the first metal layer 210, form the second metal level 210, material can be aluminium (Al) material, and preparation method can select PVD, CVD.Metal material fills up gate trench 208, afterwards, utilizes cmp planarization, finally forms P-MOS metal gates.
As shown in Figure 2 F, by dry etching, remove N-MOS dummy grid 205 completely, obtain N-MOS gate trench 211.
As shown in Figure 2 G, in above-mentioned N-MOS gate trench 211, fill the metal material with tensile stress.Fill up gate trench 211, afterwards, utilize cmp planarization, finally form N-MOS metal gates.
The order of above-mentioned formation P-MOS metal gates and N-MOS metal gates can be exchanged.For example first dry etching is removed described N-MOS dummy grid, then adopts mixing method to remove described P-MOS dummy grid.
With reference to Fig. 3, wherein show the flow chart of the legal etching removal of dry-wet mixing P-MOS dummy grid manufacture method, for schematically illustrating the flow process of whole manufacturing process.
In step 301, provide Semiconductor substrate 200.In step 302, in Semiconductor substrate 200, form interlayer dielectric layer 203, P-MOS dummy grid stacked structure and N-MOS dummy grid stacked structure.Interlayer dielectric layer 203 is through cmp planarization.Dummy grid stacked structure from bottom to top comprises high K medium layer 201, barrier layer 202 and dummy grid 204,205 successively.In step 303, on interlayer dielectric layer 203, form the photoresist of metal mask layer and patterning.The photoresist of described patterning exposes P-MOS dummy gate region, and then dry etching is removed the described metal mask layer exposing, and forms the metal mask layer 206 of patterning.In step 304, dry etching is removed the dummy grid of 70-90%, then uses SC1 solution removal metal mask layer 206.In step 305, wet etching is removed remaining P-MOS dummy grid, forms gate trench 208.In step 306, in the gate trench in P-MOS region, fill the metal material with compression, adopt cmp planarization, form P-MOS metal gates.In step 307, adopt dry etching to remove N-MOS dummy grid completely, obtain N-MOS gate trench 211.In step 308, in described N-MOS gate trench, fill the metal material with tensile stress, adopt cmp planarization, form N-MOS metal gates.
To sum up, method of the present invention is removed P-MOS dummy grid by dry-lithographic method that wet mixing is closed, the electric charge producing when the ion of solution is offset dry etching in wet etching process, prevent that the accumulation of dry etching generation is to barrier layer 202, form electrical potential difference generation current with high K medium layer 201 and Semiconductor substrate 200, so just avoided the plasma damage occurring in dry etching process.
The present invention is illustrated by above-described embodiment, but should be understood that, above-described embodiment is the object for giving an example and illustrating just, but not is intended to the present invention to be limited in described scope of embodiments.In addition it will be appreciated by persons skilled in the art that the present invention is not limited to above-described embodiment, can also make more kinds of variants and modifications according to the present invention, these variants and modifications all drop in the present invention's scope required for protection.Protection scope of the present invention is defined by the appended claims and equivalent scope thereof.
Claims (15)
1. a method of making semiconductor device, comprising:
Semi-conductive substrate is provided;
In described Semiconductor substrate, form P-MOS dummy grid stacked structure, N-MOS dummy grid stacked structure;
In described Semiconductor substrate, form the interlayer dielectric layer that surrounds described dummy grid stacked structure;
On described interlayer dielectric layer, form the metal mask layer that covers described N-MOS dummy grid stacked structure;
Mixing method etching is removed the dummy grid in described P-MOS dummy grid stacked structure.
2. the method for claim 1, is characterized in that, described dummy grid stacked structure comprises the high K medium layer, barrier layer and the described dummy grid that stack gradually.
3. method as claimed in claim 2, is characterized in that, described barrier material is titanium nitride.
4. the method for claim 1, is characterized in that, described dummy grid material is in-situ doped polysilicon.
5. the method for claim 1, is characterized in that, the material of described metal mask layer is titanium nitride.
6. method as claimed in claim 5, is characterized in that, the thickness of described metal mask layer is 10～500 dusts.
7. the method for claim 1, is characterized in that, described mixing method etching comprises first carries out a dry etching, then carries out a wet etching.
8. method as claimed in claim 7, is characterized in that, wherein dry etching is removed the dummy grid of 70-90%, and then wet etching is removed remaining dummy grid, forms P-MOS gate trench.
9. method as claimed in claim 7, is characterized in that, described wet etching solution is hot phosphoric acid.
10. method as claimed in claim 7, is characterized in that, also comprises the step of removing described metal mask layer before carrying out described wet etching.
11. methods as claimed in claim 10, is characterized in that, use metal mask layer described in SC1 solution removal.
12. methods as claimed in claim 8, is characterized in that, fill the metal material of compression in described P-MOS gate trench, then carry out cmp.
13. the method for claim 1, is characterized in that, use dry etching to remove described N-MOS dummy grid, form N-MOS gate trench.
14. methods as claimed in claim 13, is characterized in that, fill the metal material of tensile stress in described N-MOS gate trench.
15. methods as claimed in claim 13, is characterized in that, first dry etching is removed described N-MOS dummy grid, and then mixing method is removed described P-MOS dummy grid.
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