CN110970313B - Welding pad structure and preparation method of semiconductor structure - Google Patents
Welding pad structure and preparation method of semiconductor structure Download PDFInfo
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- CN110970313B CN110970313B CN201911112907.6A CN201911112907A CN110970313B CN 110970313 B CN110970313 B CN 110970313B CN 201911112907 A CN201911112907 A CN 201911112907A CN 110970313 B CN110970313 B CN 110970313B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/11—Manufacturing methods
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
- H01L2224/116—Manufacturing methods by patterning a pre-deposited material
- H01L2224/1162—Manufacturing methods by patterning a pre-deposited material using masks
- H01L2224/11622—Photolithography
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/1301—Shape
- H01L2224/13016—Shape in side view
- H01L2224/13018—Shape in side view comprising protrusions or indentations
- H01L2224/13019—Shape in side view comprising protrusions or indentations at the bonding interface of the bump connector, i.e. on the surface of the bump connector
Abstract
The invention provides a welding pad structure and a preparation method of a semiconductor structure, which comprises the following steps: sequentially forming an adhesive layer, a welding pad metal layer, an anti-reflection layer and a photoresist layer on the metal interlayer dielectric layer, wherein the metal interlayer dielectric layer comprises a sealing ring and a contact window, the sealing ring penetrates through the metal interlayer dielectric layer and extends into a semiconductor substrate of the device structure, and the contact window is electrically connected with the device structure; patterning the photoresist layer to form a first etching window; sequentially removing the anti-reflection layer and the welding pad metal layer by dry etching through the first etching window to form a second etching window; and removing the bonding layer by wet etching through the second etching window to form third windows, and forming a welding pad structure between every two adjacent third windows. The welding pad structure formed by the method can effectively eliminate the generation of accumulated charges under the condition of keeping the whole outline unaffected, and the finally obtained welding pad structure has the excellent performance of a sandwich structure and cannot affect the performance of a device structure in a chip.
Description
Technical Field
The present invention relates to the field of semiconductor manufacturing, and in particular, to a pad structure and a method for manufacturing a semiconductor structure.
Background
In the fabrication of semiconductor chips, a Seal ring (Seal ring) structure is required to Seal the chip. The sealing ring structure is surrounded on the periphery of the chip, the sealing ring structure can release and obstruct the stress generated by the chip in the packaging process, the chip is prevented from cracking, the performance of the chip is ensured to be stable for a long time, and the water vapor of the chip in the manufacturing and using processes is obstructed, so that the deterioration caused by the moisture in the chip is avoided.
In the back-end process of the semiconductor chip manufacturing process, after the top metal wiring layer is manufactured, a metal interlayer dielectric layer and a metal welding pad are required to be manufactured on the top metal wiring layer, and the metal welding pad becomes a connection point of subsequent packaging interconnection. When a metal pad is formed in the prior art, a metal pad material layer is formed on a metal interlayer dielectric layer, and then the metal pad material layer is etched by a dry method according to specific requirements on the distribution pattern of the metal pad on a chip to form the metal pad, but accumulated charges can be formed on a contact window in the chip in the etching process, and can not be effectively led out from the chip through a seal ring structure, so that the problem of Plasma Induced Damage (PID) can be caused, and the damage of the PID to the chip can not be recovered, so that the performance of the chip can be influenced.
Disclosure of Invention
In view of the above-mentioned drawbacks of the prior art, an object of the present invention is to provide a pad structure and a method for manufacturing a semiconductor structure, which are used to solve the problem that when a metal pad is formed on a semiconductor chip in the prior art, accumulated charges are easily generated on a contact window of the chip, and the accumulated charges cannot be effectively led out from the chip through a seal ring structure, thereby causing damage to the performance of the chip.
In order to achieve the above and other related objects, the present invention provides a method for manufacturing a pad structure, the method at least comprising the following steps:
sequentially forming an adhesive layer, a welding pad metal layer, an anti-reflection layer and a photoresist layer on the metal interlayer dielectric layer, wherein the metal interlayer dielectric layer comprises a sealing ring and a contact window, the sealing ring penetrates through the metal interlayer dielectric layer and extends into a semiconductor substrate of a device structure, and the contact window is electrically connected with the device structure;
patterning the photoresist layer to form a first etching window;
sequentially removing the anti-reflection layer and the welding pad metal layer by dry etching through the first etching window to form a second etching window so that accumulated charges generated in the dry etching process enter the sealing ring through the bonding layer and are released through the semiconductor substrate;
and removing the bonding layer by wet etching through the second etching window to form third windows, and forming a welding pad structure between every two adjacent third windows.
Optionally, the adhesion layer includes titanium, the pad metal layer includes aluminum, and the anti-reflection layer includes titanium nitride.
Optionally, the adhesive layer has a thickness between
The thickness of the pad metal layer is between
The thickness of the anti-reflection layer is between
In the meantime.
Optionally, the etching gas used in the dry etching includes chlorine gas and boron chloride.
Optionally, the etching solution used in the wet etching includes H2SO4And H2O2。
Optionally, the metal interlayer dielectric layer includes silicon oxide or silicon nitride.
Optionally, the removing the bonding layer by wet etching further includes: and forming a passivation layer covering the anti-reflection layer and the third etching window and patterning the passivation layer to expose the welding pad structure.
Optionally, the device structure includes a 3D memory device, the 3D memory device including a peripheral circuit and a memory cell array.
Optionally, the method further comprises: and forming the peripheral circuit and the memory cell array on different wafers, and connecting the peripheral circuit and the memory cell array together in a bonding mode, wherein the peripheral circuit is arranged below the memory cell array, and the welding pad structure is arranged above the memory cell array.
The invention also provides a preparation method of the semiconductor structure, which at least comprises the following steps:
and forming a device structure layer and a welding pad structure which are sequentially overlapped on the semiconductor substrate, wherein the welding pad structure is manufactured by adopting the preparation method of the welding pad structure.
As mentioned above, the bonding pad structure of the present invention is prepared by using a sandwich structure of an adhesive layer, a bonding pad metal layer and an anti-reflection layer, first etching off the anti-reflection layer and the bonding pad metal layer with a thicker total thickness by dry etching, accumulated charges can enter the sealing ring through the adhesive layer and be released through the semiconductor substrate during etching to obtain the approximate outline of the welding pad structure, and then the very thin adhesive layer is etched away by wet etching, because the bonding layer is thin, the outline of the welding pad structure is not greatly influenced in the corrosion process, and the accumulated charge effect can not be brought by wet etching, therefore, the generation of accumulated charges on the contact window is effectively avoided, the generation of the accumulated charges is effectively eliminated under the condition that the whole outline of the welding pad structure is not influenced, and the finally obtained welding pad structure has the excellent performance of the sandwich structure and cannot influence the performance of a device structure in a chip.
Drawings
Fig. 1 to 3 are cross-sectional views illustrating steps of a method for fabricating a pad structure in the prior art.
Fig. 4 is a schematic flow chart illustrating a method for fabricating a pad structure according to the present invention.
Fig. 5 to 9 are cross-sectional views illustrating steps of a method for fabricating a pad structure according to the present invention.
Description of the element reference numerals
10, 20 metal interlayer dielectric layer
11 pad material layer
12, 24 photoresist layer
13, 25 sealing ring
14, 26 contact window
15 graphic window
16 etching channel
21 adhesive layer
22 pad metal layer
23 anti-reflection layer
27 first etch Window
28 second etch Window
29 third etch Window
30 passivation layer
S1-S4
Detailed Description
The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention.
Please refer to fig. 1 to 9. It should be noted that the drawings provided in the present embodiment are only for illustrating the basic idea of the present invention, and the drawings only show the components related to the present invention rather than being drawn according to the number, shape and size of the components in actual implementation, and the type, quantity and proportion of each component in actual implementation may be changed arbitrarily, and the layout of the components may be more complicated.
With the rapid development of semiconductor integrated circuit technology, the size of CMOS (complementary metal oxide semiconductor) devices is also decreasing, and in the back-end process of the semiconductor manufacturing process, after the top metal wiring layer is fabricated, a metal interlayer dielectric layer and a metal bonding pad are also fabricated on the top metal wiring layer, and the metal bonding pad becomes a connection point for subsequent packaging and interconnection. The prior art process for forming a metal pad structure generally includes the following steps: as shown in fig. 1, firstly, a pad material layer 11 and a photoresist layer 12 are sequentially deposited on an inter-metal dielectric layer 10; as shown in fig. 2, then, performing photolithography to remove the photoresist layer 12 in the region to be etched, and forming a pattern window 15; finally, as shown in fig. 3, the pad material layer 11 is removed by dry etching through the pattern window 15 to form an etched trench 16, and the photoresist layer 12 is removed at the same time, so that the structure between two adjacent etched trenches 16 forms a pad structure.
However, in the dry etching process, high-energy plasma is often used to physically bombard and/or chemically react the material to be etched, and an unrecoverable damage, i.e., an electrostatic breakdown phenomenon caused by charge accumulation, is often generated during the etching process, and is generally referred to as Plasma Induced Damage (PID). Specifically, during the process of etching the pad material layer 11 through the pattern window 15, the electrically neutral environment of the plasma changes, and there are unequal amounts of positive charges and negative charges, and before the pad material layer 11 is completely opened, uneven charges (i.e., accumulated charges, generally located on the sidewall and the bottom of the etched trench 16) enter the seal ring 13 through the pad material layer 11 that is not etched, so that the uneven charges are released into the semiconductor substrate through the seal ring 13 that extends to the semiconductor substrate, and static electricity is released, but after the pad material layer 11 is opened, the release path of the accumulated charges is also interrupted, and the accumulated charges above the contact window 14 cannot be released, and thus can enter the contact window 14. Since the contact 14 is electrically connected to the device structure, the accumulated charge can enter the device structure, causing irrecoverable damage to the performance of the device structure.
Taking 3D NAND memory as an example, 3D NAND memory includes a memory cell array and peripheral circuits. The memory cell array wafer has memory cell transistors, i.e., memory cell strings, formed therein with vertical direction strings on a lateral substrate. Peripheral circuitry can be understood to be the periphery of the 3D NAND memory, including any suitable digital, analog, and/or mixed signal peripheral circuitry to facilitate 3D memory operations. For example, peripheral circuitry may include one or more of page buffers, decoders (e.g., row and column decoders), sense amplifiers, drivers, charge pumps, current or voltage references, or any active or passive components in circuitry (e.g., transistors, diodes, resistors, or capacitors), typically formed using complementary metal-semiconductor (CMOS) technology, so that the wafer includes several transistors. In the 3D NAND memory, the peripheral circuit and the memory cell array may be formed on the same wafer, and the peripheral circuit is disposed below the memory cell array, and the pad structure is disposed above the memory cell array; in addition, the peripheral circuit and the memory cell array may also be formed on different wafers, and then the peripheral circuit wafer and the memory cell array wafer are electrically connected by bonding, so that the peripheral circuit is disposed below the memory cell array and the pad structure is disposed above the memory cell array. In the two modes, the welding pad structure is formed above the memory cell array, when the welding pad structure is formed by dry etching, accumulated charges can enter the memory cell array and/or a peripheral circuit through the contact window and are distributed on the thin gate oxide layer, and when enough accumulated charges are accumulated, the gate oxide layer generates a leakage phenomenon, so that the problems of threshold voltage drift, transconductance degradation, gate leakage and the like of the whole 3D NAND memory occur, and the performance of the whole 3D NAND memory is influenced.
Based on the above problems and by analyzing various factors in detail, the inventor determines the main cause of the performance reduction of the device, and based on the main cause, provides a method for manufacturing a bonding pad structure, which comprises the following steps:
sequentially forming an adhesive layer, a welding pad metal layer, an anti-reflection layer and a photoresist layer on the metal interlayer dielectric layer, wherein the metal interlayer dielectric layer comprises a sealing ring and a contact window, the sealing ring penetrates through the metal interlayer dielectric layer and extends into a semiconductor substrate of a device structure, and the contact window is electrically connected with the device structure;
patterning the photoresist layer to form a first etching window;
sequentially removing the anti-reflection layer and the welding pad metal layer by dry etching through the first etching window to form a second etching window so that accumulated charges generated in the dry etching process enter the sealing ring through the bonding layer and are released through the semiconductor substrate;
and removing the bonding layer by wet etching through the second etching window to form a third window, and forming a welding pad structure between the adjacent third windows.
The sandwich-shaped welding pad structure comprises an adhesive layer, a welding pad metal layer and an anti-reflection layer, wherein the adhesive layer can effectively improve the adhesiveness between a metal interlayer dielectric layer and the welding pad metal layer, and can also reduce the contact resistance between the metal interlayer dielectric layer and the welding pad metal layer. The method for preparing the welding pad structure based on the sandwich structure not only can obtain the welding pad structure with better performance, but also can reduce the damage to the device structure in the chip when the welding pad structure is formed, and particularly, dry etching is firstly adopted to etch the anti-reflection layer and the welding pad metal layer with thicker total thickness, accumulated charges can enter the sealing ring through the bonding layer and are released through the semiconductor substrate during etching, the approximate outline of the welding pad structure is obtained, then wet etching is adopted to etch the very thin bonding layer, the influence on the outline of the welding pad structure is not great during the etching process due to the thinner bonding layer, and the accumulated charges on the contact window can be effectively avoided due to the fact that the wet etching does not bring about the accumulated charges effect, so that the accumulated charges can be effectively eliminated under the condition that the overall outline of the welding pad structure is not influenced, and the finally obtained welding pad structure has the excellent performance of the sandwich structure and cannot cause the damage to the device structure in the chip Performance is affected.
The following will describe in detail a method for manufacturing a pad structure in a 3D NAND memory by way of example with reference to the accompanying drawings, and it is obvious that the described embodiments are only a part of embodiments of the present invention, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
As shown in fig. 4 to 9, the present embodiment provides a method for manufacturing a pad structure, including the following steps:
as shown in fig. 4 and 5, step S1 is performed to sequentially form an adhesion layer 21, a pad metal layer 22, an anti-reflection layer 23, and a photoresist layer 24 on the inter-metal dielectric layer 20, where the inter-metal dielectric layer 20 includes a sealing ring 25 and a contact window 26, the sealing ring 25 penetrates through the inter-metal dielectric layer 20 and extends into a semiconductor substrate of a device structure, and the contact window 26 is electrically connected to the device structure.
In this embodiment, a 3D NAND memory is taken as an example, so the device structure includes a peripheral circuit and a memory cell array, as an example, the peripheral circuit and the memory cell array may be formed on the same wafer, or formed on two different wafers, and then electrically connected by bonding, in addition, the peripheral circuit is disposed below the memory cell array, and the pad structure is disposed above the memory cell array. The seal ring 25 extends into the semiconductor substrate under the peripheral circuits, and the contact windows 26 are electrically connected through the interconnection structures in the memory cell array and in the peripheral circuits. The peripheral circuits are formed using complementary metal-semiconductor (CMOS) technology, including any suitable digital, analog, and/or mixed-signal peripheral circuits used to facilitate memory operations, for example, the peripheral circuits may include one or more of page buffers, decoders (e.g., row and column decoders), sense amplifiers, drivers, charge pumps, current or voltage references, or active or passive components (e.g., transistors, diodes, resistors, or capacitors) in any circuit.
By way of example, the adhesion layer 21 comprises titanium, the pad metal layer 22 comprises aluminum, and the anti-reflection layer 23 comprises titanium nitride. Preferably, the thickness of the adhesive layer 21 is between
The thickness of the pad metal layer 22 is between
The thickness of the anti-reflection layer 23 is between
In the meantime.
The intermetal dielectric layer 20 may include silicon oxide or silicon nitride, for example.
As shown in fig. 4 and 6, step S2 is performed to pattern the photoresist layer 24 and form a first etching window 27.
It should be noted that the pattern of the photoresist layer 24 patterned by photolithography is set according to specific situations and specific requirements, so the patterns may be the same or different, and are not limited herein.
As shown in fig. 4 and fig. 7, step S3 is performed, in which the anti-reflection layer 23 and the pad metal layer 22 are sequentially removed by dry etching through the first etching window 27 to form a second etching window 28, so that the accumulated charges (as shown by the arrow in fig. 7) generated during the dry etching process enter the seal ring 25 through the adhesion layer 21 and are released through the semiconductor substrate.
By way of example, the etching gas used in the dry etching process includes chlorine gas and boron chloride.
In the dry etching process, end point detection is adopted to enable the dry etching to stay on the bonding layer, and the etching end point is determined by detecting the change of the etching rate, the type change of the corrosion product removed in the etching, the change of the active reactant in gas discharge or the change of a light emission spectrum and the like.
As shown in fig. 4 and fig. 8, step S4 is finally performed, in which the second etching window 28 is used to remove the adhesive layer 21 by wet etching, so as to form a third window 29, and a pad structure is formed between two adjacent third windows 29.
As an example, when the adhesion layer 21 is removed by wet etching, H may be used2SO4And H2O2The mixed solution of (3) was etched at a ratio of about 5:1 at 210 ℃.
As shown in fig. 9, as an example, after removing the adhesive layer 21 by wet etching, a step of forming a passivation layer 30 covering the anti-reflection layer 23 and the third etching window 29 and patterning the passivation layer 30 to expose the pad structure is further included.
Based on the above method for manufacturing a pad structure, this embodiment further provides a method for manufacturing a semiconductor structure, including the steps of: and forming a device structure layer and a welding pad structure which are sequentially stacked on the semiconductor substrate, wherein the welding pad structure is manufactured by adopting the preparation method of the welding pad structure described in the embodiment.
As an example, the device structure layer includes a 3D memory device, the 3D memory device including a peripheral circuit and a memory cell array, the peripheral circuit being disposed below the memory cell array, and the pad structure being disposed above the memory cell array.
In summary, the present invention provides a method for fabricating a bonding pad structure, in which the bonding pad structure employs a sandwich structure of an adhesive layer, a bonding pad metal layer and an anti-reflection layer, the anti-reflection layer and the bonding pad metal layer having a relatively thick total thickness are etched away by dry etching, accumulated charges can enter the sealing ring through the adhesive layer and be released through the semiconductor substrate during etching to obtain the approximate outline of the welding pad structure, then the very thin adhesive layer is corroded away by wet etching, because the bonding layer is thin, the outline of the welding pad structure is not greatly influenced in the corrosion process, and the accumulated charge effect can not be brought by wet etching, therefore, the generation of accumulated charges on the contact window is effectively avoided, the generation of the accumulated charges is effectively eliminated under the condition that the whole outline of the welding pad structure is not influenced, and the finally obtained welding pad structure has the excellent performance of the sandwich structure and cannot influence the performance of a device structure in a chip. Therefore, the invention effectively overcomes various defects in the prior art and has high industrial utilization value.
The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.
Claims (10)
1. A method for manufacturing a bonding pad structure is characterized by at least comprising the following steps:
sequentially forming an adhesive layer, a welding pad metal layer, an anti-reflection layer and a photoresist layer on the metal interlayer dielectric layer, wherein the metal interlayer dielectric layer comprises a sealing ring and a contact window, the sealing ring penetrates through the metal interlayer dielectric layer and extends into a semiconductor substrate of a device structure, and the contact window is electrically connected with the device structure;
patterning the photoresist layer to form a first etching window;
sequentially removing the anti-reflection layer and the welding pad metal layer by dry etching through the first etching window to form a second etching window so that accumulated charges generated in the dry etching process enter the sealing ring through the bonding layer and are released through the semiconductor substrate;
and removing the bonding layer by wet etching through the second etching window to form third etching windows, and forming a welding pad structure between every two adjacent third etching windows.
2. The method of claim 1, wherein: the bonding layer comprises titanium, the pad metal layer comprises aluminum, and the anti-reflection layer comprises titanium nitride.
3. The method of claim 2, wherein: the thickness of the bonding layer is between
The thickness of the pad metal layer is between
The thickness of the anti-reflection layer is between
In the meantime.
4. The method of claim 2, wherein: the etching gas adopted by the dry etching comprises chlorine and boron chloride.
5. The method of claim 2, wherein: the etching liquid adopted by the wet etching comprises H2SO4And H2O2。
6. The method of claim 1, wherein: the metal interlayer dielectric layer comprises silicon oxide or silicon nitride.
7. The method for preparing a bond pad structure of claim 1, further comprising, after removing the adhesion layer by wet etching: and forming a passivation layer covering the anti-reflection layer and the third etching window and patterning the passivation layer to expose the welding pad structure.
8. The method of claim 1, wherein: the device structure includes a 3D memory device, the 3D memory device including a peripheral circuit and a memory cell array.
9. The method for preparing a solder pad structure of claim 8, further comprising: and forming the peripheral circuit and the memory cell array on different wafers, and connecting the peripheral circuit and the memory cell array together in a bonding mode, wherein the peripheral circuit is arranged below the memory cell array, and the welding pad structure is arranged above the memory cell array.
10. A method for manufacturing a semiconductor structure, the method comprising at least the steps of:
forming a device structure layer and a bonding pad structure stacked in sequence on a semiconductor substrate, wherein the bonding pad structure is manufactured by the method for manufacturing the bonding pad structure according to any one of claims 1 to 9.
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| US5679213A (en) * | 1993-11-08 | 1997-10-21 | Fujitsu Limited | Method for patterning a metal film |
| JPH08321507A (en) * | 1995-05-26 | 1996-12-03 | Mitsubishi Electric Corp | Forming method for wiring layer |
| JP2006114722A (en) * | 2004-10-15 | 2006-04-27 | Matsushita Electric Ind Co Ltd | Method for manufacturing semiconductor device |
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| CN103295970A (en) * | 2013-06-05 | 2013-09-11 | 京东方科技集团股份有限公司 | Array substrate and manufacturing method thereof and display device |
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