JP2006114722A - Method for manufacturing semiconductor device - Google Patents

Method for manufacturing semiconductor device Download PDF

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JP2006114722A
JP2006114722A JP2004301169A JP2004301169A JP2006114722A JP 2006114722 A JP2006114722 A JP 2006114722A JP 2004301169 A JP2004301169 A JP 2004301169A JP 2004301169 A JP2004301169 A JP 2004301169A JP 2006114722 A JP2006114722 A JP 2006114722A
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groove
silicon substrate
film
etching
semiconductor device
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Yoichi Yoshida
洋一 吉田
Yasuyuki Kamata
泰幸 鎌田
Kiyoyuki Morita
清之 森田
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Panasonic Holdings Corp
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Matsushita Electric Industrial Co Ltd
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Abstract

<P>PROBLEM TO BE SOLVED: To provide such a method that an oxide film having a low plane direction dependency is formed and a rounding oxidation is efficiently made. <P>SOLUTION: In forming a groove in a silicon substrate, a plasma damage on the silicon substrate is decreased by utilizing a wet etching method, and a stress and an electric field concentration are decreased at a distal end by a shape control at the end of the groove by adjustment of an etching time period. By using an oxygen radical oxidation heat treating method when the rounding oxidation is made, a plane direction film thickness dependency of the oxide film to be formed can be considerably suppressed. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

本発明は、シリコン基板の薬液を用いたエッチング技術に関するものである。   The present invention relates to an etching technique using a chemical solution for a silicon substrate.

近年、CMOS−LSIの素子分離プロセスとしてSTI(Shallow Trench Isoration)技術が注目されている。以下、従来のSTIの形成方法について説明する(例えば、特許文献1参照)。   In recent years, STI (Shallow Trench Isolation) technology has attracted attention as an element isolation process of CMOS-LSI. Hereinafter, a conventional STI formation method will be described (for example, see Patent Document 1).

まず、半導体基板上に溝を形成し、少なくとも前記溝に絶縁膜を充填させる。その後、一回以上の平坦化手段により前記半導体基板上の絶縁膜を除去し、前記溝内にのみ絶縁膜を残す。この一回以上の平坦化の内、最後の平坦化手段にウェットエッチング法を用いず、鏡面研磨法により平坦化を行う。   First, a groove is formed on a semiconductor substrate, and at least the groove is filled with an insulating film. Thereafter, the insulating film on the semiconductor substrate is removed by one or more planarization means, leaving the insulating film only in the trench. Of these one or more times of flattening, the final flattening means is flattened by the mirror polishing method without using the wet etching method.

このため、素子分離絶縁膜形成の際に素子分離絶縁膜の端に生ずる凹部分を防止できると共に、製造工程を減少させ、形成が容易で歩留まりの高い、STIの形成方法を実現している。
特開平10−50822号公報
For this reason, it is possible to prevent a concave portion generated at the end of the element isolation insulating film during the formation of the element isolation insulating film, reduce the number of manufacturing steps, and realize an STI formation method that is easy to form and has a high yield.
Japanese Patent Laid-Open No. 10-50822

しかしながら、従来の形成方法では、半導体装置に応用する際には以下のような課題が残る。   However, in the conventional formation method, the following problems remain when applied to a semiconductor device.

まず、従来の形成方法のように、エッチング工程全てにドライエッチングを用いて溝形成する場合には、基板へのプラズマダメージが大きく、形成された溝をデバイスの一部として使用する際に物理的脆弱性を生ずるという問題が起きる。   First, when grooves are formed using dry etching in the entire etching process as in the conventional formation method, plasma damage to the substrate is large, and the formed grooves are physically used as part of the device. The problem of creating a vulnerability occurs.

また、形成された溝底部のテーパー角度が87〜90°となり、溝底面と溝側面とが交わる箇所では電界集中や応力集中が起こりやすいという問題が起きる。   Further, the taper angle of the formed groove bottom portion is 87 to 90 °, and there is a problem that electric field concentration and stress concentration are likely to occur at a portion where the groove bottom surface and the groove side surface intersect.

また、特許文献1の出願当時の技術では、丸め酸化処理の際にファーナス処理が量産技術として一般的であったが、この方法では面方位の異なるシリコン基板部溝の内側壁に形成される酸化膜の膜厚のバラツキが非常に大きく、均一な膜を形成することが難しいため、電界集中や応力集中が起こりやすいという問題が起きる。   Further, in the technology at the time of filing of Patent Document 1, the furnace processing is generally used as the mass production technology in the rounding oxidation processing. However, in this method, the oxidation formed on the inner side walls of the silicon substrate grooves having different plane orientations. The variation in film thickness is very large, and it is difficult to form a uniform film, which causes a problem that electric field concentration and stress concentration tend to occur.

そこで、本発明は、上記の課題を克服するSTIの形成方法を提供することを目的とする。   Therefore, an object of the present invention is to provide a method for forming an STI that overcomes the above-described problems.

本願において開示される発明の概要は以下の通りである。   The outline of the invention disclosed in the present application is as follows.

まず、本発明は、従来の形成方法のように、エッチング工程にドライエッチングだけを用いるのではなく、アルカリ溶液を用いたウェットエッチングを一部利用することにより、シリコン基板へのプラズマダメージを軽減させることができ、これによりイオン衝撃による物理的強度の劣化を解決することができる。   First, the present invention reduces plasma damage to a silicon substrate by partially using wet etching using an alkaline solution instead of using only dry etching in the etching process as in the conventional formation method. Thus, the physical strength deterioration due to ion bombardment can be solved.

また、本発明は、アルカリ溶液を用いた異方性エッチング処理を(111)面に沿って進行させるが、エッチング露出面が全て(111)面になる前に処理を停止させることにより、溝先端部がV字型になることを回避することができ、これにより電界集中及び応力集中の問題を解決することができる。   In the present invention, an anisotropic etching process using an alkaline solution is allowed to proceed along the (111) plane, but the process is stopped before all of the etching exposed surfaces become the (111) plane, so that the groove tip The portion can be prevented from being V-shaped, thereby solving the problems of electric field concentration and stress concentration.

また、本発明は、分離溝形成後の丸め酸化を従来のファーナスではなく、酸素ラジカル酸化法を用いるので、形成される酸化膜の面方位膜厚依存性を大幅に抑えることが可能となり、これからも電界集中及び応力集中の問題を解決することができる。   In addition, since the present invention uses the oxygen radical oxidation method instead of the conventional furnace for the rounding oxidation after the formation of the separation groove, it is possible to greatly suppress the surface orientation film thickness dependency of the formed oxide film. Can also solve the problems of electric field concentration and stress concentration.

本発明によると、分離溝のエッチング処理において、アルカリ溶液を用いたウェットエッチングにより、シリコン基板へのプラズマダメージを軽減させると共に溝先端部が台形状になり、溝先端部での応力集中及び電界集中を回避することができる。また、分離溝の酸化処理において、酸素ラジカル酸化法を用いた丸め酸化により、酸化膜厚の面方位依存性が大幅に減少して均一な酸化膜が形成され、前記効果と相乗して電界集中及び応力集中をより一層回避することができる。従って、形成が容易で歩留まりの高い、STIを実現することができる。   According to the present invention, in the etching process of the separation groove, wet etching using an alkaline solution reduces plasma damage to the silicon substrate and the groove tip becomes trapezoidal, and stress concentration and electric field concentration at the groove tip. Can be avoided. In addition, in the oxidation treatment of the separation groove, rounding oxidation using the oxygen radical oxidation method greatly reduces the plane orientation dependency of the oxide film thickness, and forms a uniform oxide film. In addition, stress concentration can be further avoided. Therefore, it is possible to realize an STI that is easy to form and has a high yield.

以下、本発明の実施形態を図面に基づいて詳細に説明する。   Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

図1〜図2は、本発明の実施形態に係る半導体装置の製造方法の各工程を示す断面図である。   1 to 2 are cross-sectional views showing respective steps of a method for manufacturing a semiconductor device according to an embodiment of the present invention.

まず、図1(a)に示すように、(100)主面のシリコン基板100上にSiO2膜(下地膜)101、ポリシリコン膜102、窒化シリコン膜(酸化防止膜)103、反射防止膜(ARC膜)104及び露光開口処理されたレジストパターン105が形成されている。 First, as shown in FIG. 1A, an SiO 2 film (underlying film) 101, a polysilicon film 102, a silicon nitride film (antioxidation film) 103, an antireflection film are formed on a silicon substrate 100 on the (100) main surface. An (ARC film) 104 and a resist pattern 105 subjected to exposure opening processing are formed.

なお、図1(a)は活性領域用マスク露光工程後の状態を示しており、レジスト開口部の径の大きさによっては、以後行われるエッチング処理により形成される溝形状が異なってくるので、応用するデバイスによっては開口部形状の調整が必要となってくる。   FIG. 1A shows the state after the active region mask exposure step, and the groove shape formed by the etching process to be performed later varies depending on the diameter of the resist opening. Depending on the device to be applied, it is necessary to adjust the shape of the opening.

次に、図1(b)に示すように、反射防止膜104、窒化シリコン膜103、ポリシリコン膜102及びSiO2膜101をドライエッチング及び酸素アッシング処理にて除去し、シリコン基板100が開口部に露出するように形成されている。その後、レジストパターン105及び反射防止膜104を除去する。 Next, as shown in FIG. 1B, the antireflection film 104, the silicon nitride film 103, the polysilicon film 102, and the SiO 2 film 101 are removed by dry etching and oxygen ashing, so that the silicon substrate 100 is opened. It is formed so as to be exposed. Thereafter, the resist pattern 105 and the antireflection film 104 are removed.

次に、図1(c)に示すように、アルカリ溶液を用いたウェットエッチングとして、硫酸及び水酸化アンモニウムを使用してシリコン基板100をエッチングする。その際、シリコン基板100の露出部全てが(111)面になる前に処理を停止させるようにして異方性エッチング処理を行う。   Next, as shown in FIG. 1C, the silicon substrate 100 is etched using sulfuric acid and ammonium hydroxide as wet etching using an alkaline solution. At that time, the anisotropic etching process is performed so that the process is stopped before all the exposed portions of the silicon substrate 100 become the (111) plane.

次に、図2(a)に示すように、ドライエッチングを用いてシリコン基板100の露出部にて(100)面に沿って約250〜400nmの溝深化処理を行う。   Next, as shown in FIG. 2A, a trench deepening process of about 250 to 400 nm is performed along the (100) plane at the exposed portion of the silicon substrate 100 using dry etching.

次に、図2(b)に示すように、ワンバスのウェットエッチング処理の後、分離溝の保護酸化として、酸素ラジカル酸化法としてISSG(In-Situ Steam Generation)アニールを用いて1000〜1150℃で酸化処理して分離溝の丸め酸化(図示せず)を行う。   Next, as shown in FIG. 2 (b), after the wet etching process of one bath, the protective oxidation of the separation groove is performed at 1000 to 1150 ° C. using ISSG (In-Situ Steam Generation) annealing as an oxygen radical oxidation method. Oxidation treatment is performed to round the separation groove (not shown).

次に、図2(c)に示すように、従来と同様にして、分離溝に絶縁膜(例えば、CVD−SiO2膜)106を充填させた後、研磨法により半導体基板上の絶縁膜106を除去して分離溝内にのみ絶縁膜106を残す。その後、窒化シリコン膜103及びポリシリコン膜102を除去して、本発明による素子分離層のSTIが形成される。 Next, as shown in FIG. 2C, after the isolation trench is filled with an insulating film (for example, a CVD-SiO 2 film) 106 as in the prior art, the insulating film 106 on the semiconductor substrate is polished by a polishing method. And the insulating film 106 is left only in the isolation trench. Thereafter, the silicon nitride film 103 and the polysilicon film 102 are removed, and the STI of the element isolation layer according to the present invention is formed.

以上のように、本実施形態よると以下の代表的な効果が得られる。
(1)エッチング工程にドライエッチングだけを用いるのではなく、アルカリ溶液を用いたウェットエッチングを一部利用することにより、シリコン基板へのプラズマダメージを軽減させることができ、これによりイオン衝撃による物理的強度の劣化を防止することができる。
(2)アルカリ溶液を用いた異方性エッチング処理を(111)面に沿って進行させるが、エッチング露出面が全て(111)面になる前に処理を停止させることにより、溝先端部がV字型になることを回避することができ、これにより電界集中及び応力集中を防止することができる。
(3)分離溝形成後の丸め酸化に酸素ラジカル酸化法を用いるので、形成される酸化膜の面方位膜厚依存性を大幅に抑えることが可能となり、これからも電界集中及び応力集中を防止することができる。
As described above, according to this embodiment, the following representative effects can be obtained.
(1) Rather than using only dry etching in the etching process, plasma damage to the silicon substrate can be reduced by partially using wet etching using an alkaline solution, thereby making physical damage due to ion bombardment possible. Strength deterioration can be prevented.
(2) Anisotropic etching process using an alkaline solution is allowed to proceed along the (111) plane, but the process is stopped before all of the exposed etching surface becomes the (111) plane, so that the groove tip becomes V It is possible to avoid the shape of the letter, thereby preventing electric field concentration and stress concentration.
(3) Since the oxygen radical oxidation method is used for the rounding oxidation after the formation of the separation groove, it is possible to greatly suppress the surface orientation film thickness dependency of the formed oxide film, and to prevent electric field concentration and stress concentration from now on. be able to.

以上説明したように、本発明は、形成が容易で歩留まりの高いSTIを形成する方法等に有用である。   As described above, the present invention is useful for a method of forming an STI that is easy to form and has a high yield.

本発明の実施形態に係る半導体装置の製造方法の各工程を示す断面図Sectional drawing which shows each process of the manufacturing method of the semiconductor device which concerns on embodiment of this invention 本発明の実施形態に係る半導体装置の製造方法の各工程を示す断面図Sectional drawing which shows each process of the manufacturing method of the semiconductor device which concerns on embodiment of this invention

符号の説明Explanation of symbols

100 シリコン基板
101 SiO2
102 ポリシリコン膜
103 窒化シリコン膜
104 反射防止膜
105 レジストパターン
106 絶縁膜
100 silicon substrate 101 SiO 2 film 102 polysilicon film 103 a silicon nitride film 104 antireflection film 105 resist pattern 106 insulating film

Claims (3)

シリコン基板上に下地膜と酸化防止膜との積層膜を形成する工程と、
前記積層膜を選択的にドライエッチングして開口部を形成して前記シリコン基板の表面を露出させる工程と、
前記シリコン基板の露出部をエッチングして分離溝を形成する工程と、
前記分離溝に絶縁膜を埋め込んで素子分離層を形成する工程とを備え、
前記分離溝を形成する工程は、ウェットエッチングにより前記シリコン基板の露出部に台形状の溝を形成した後、ドライエッチングにより前記溝底部の形状を保持して溝深化処理を行うことを特徴とする半導体装置の製造方法。
Forming a laminated film of a base film and an antioxidant film on a silicon substrate;
Selectively etching the laminated film to form an opening to expose the surface of the silicon substrate;
Etching the exposed portion of the silicon substrate to form a separation groove;
A step of embedding an insulating film in the isolation trench to form an element isolation layer,
The step of forming the separation groove is characterized in that after forming a trapezoidal groove on the exposed portion of the silicon substrate by wet etching, a groove deepening process is performed by maintaining the shape of the bottom of the groove by dry etching. A method for manufacturing a semiconductor device.
前記ウェットエッチングは、アルカリ溶液を用いて前記露出部に(111)面の異方性エッチング処理を行い、エッチング露出面が全て(111)面になる前に前記処理を停止させ、
前記ドライエッチングは、前記(111)面を維持しながらエッチングすることを特徴とする請求項1に記載の半導体装置の製造方法。
In the wet etching, an anisotropic etching process of the (111) plane is performed on the exposed portion using an alkaline solution, and the process is stopped before all the etched exposed surfaces become the (111) plane,
The method of manufacturing a semiconductor device according to claim 1, wherein the dry etching is performed while maintaining the (111) plane.
前記分離溝の形成工程の後、酸素ラジカル酸化法を用いて前記分離溝の丸め酸化を行う工程とをさらに備えたことを特徴とする請求項1又は2に記載の半導体装置の製造方法。 The method for manufacturing a semiconductor device according to claim 1, further comprising a step of performing rounding oxidation of the separation groove using an oxygen radical oxidation method after the step of forming the separation groove.
JP2004301169A 2004-10-15 2004-10-15 Method for manufacturing semiconductor device Withdrawn JP2006114722A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110970313A (en) * 2019-11-14 2020-04-07 长江存储科技有限责任公司 Welding pad structure and preparation method of semiconductor structure

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110970313A (en) * 2019-11-14 2020-04-07 长江存储科技有限责任公司 Welding pad structure and preparation method of semiconductor structure
CN110970313B (en) * 2019-11-14 2021-05-07 长江存储科技有限责任公司 Welding pad structure and preparation method of semiconductor structure

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